PCA9515B SCL0 SDA0 SCL1 SDA1 GND VCC EN I 2 C or SMBus Master (e.g. Processor) I 2 C Slave Devices VCC VCC VCC Product Folder Sample & Buy Technical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. PCA9515B SCPS232B – MARCH 2012 – REVISED MARCH 2016 PCA9515B Dual Bidirectional I 2 C Bus and SMBus Repeater 1 1 Features 1• Two-Channel Bidirectional Buffers • I 2 C Bus and SMBus Compatible • Support for I 2 C Standard Mode (100-kHz) and Fast Mode (400-kHz) • Active-High Repeater-Enable Input • Open-Drain I 2 C Input and Output • 5.5-V Tolerant I 2 C Input and Output and Enable Input Support Mixed-Mode Signal Operation • Lockup-Free Operation • Accommodates Standard Mode, Fast Mode I 2 C Devices, and Multiple Masters • Supports Arbitration and Clock Stretching Across Repeater • Powered-Off High-Impedance I 2 C Pins • Latch-Up Performance Exceeds 100-mA Per JESD 78, Class I • ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 1000-V Charged-Device Model (C101) 2 Applications • Servers • Routers (Telecom Switching Equipment) • Industrial Equipment • Products with Many I 2 C Slaves and Long PCB Traces 3 Description The PCA9515B is a BiCMOS dual bidirectional buffer integrated circuit intended for I 2 C bus and SMBus applications. The device contains two identical bidirectional open-drain buffer circuits that enables I 2 C and similar bus systems to be extended (or add slaves) without degrading system performance. The dual bidirectional I 2 C buffer is operational at 2.3 V to 3.6 V V CC . The PCA9515B buffers both the serial data (SDA) and serial clock (SCL) signals on the I 2 C bus, while retaining all the operating modes and features of the I 2 C system. The device allows two buses, of 400-pF bus capacitance, to be connected in an I 2 C application. Device Information (1) PART NUMBER PACKAGE BODY SIZE (NOM) PCA9515B VSSOP (8) 3.00 mm × 3.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Simplified Schematic
Transcript
PCA9515B
SCL0
SDA0
SCL1
SDA1
GND
VCC EN
I2C or SMBus
Master (e.g.
Processor)
I2C Slave
Devices
VCC VCC VCC
Product
Folder
Sample &Buy
Technical
Documents
Tools &
Software
Support &Community
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,intellectual property matters and other important disclaimers. PRODUCTION DATA.
PCA9515BSCPS232B –MARCH 2012–REVISED MARCH 2016
PCA9515B Dual Bidirectional I2C Bus and SMBus Repeater
1
1 Features1• Two-Channel Bidirectional Buffers• I2C Bus and SMBus Compatible• Support for I2C Standard Mode (100-kHz) and
Fast Mode (400-kHz)• Active-High Repeater-Enable Input• Open-Drain I2C Input and Output• 5.5-V Tolerant I2C Input and Output and Enable
Input Support Mixed-Mode Signal Operation• Lockup-Free Operation• Accommodates Standard Mode, Fast Mode I2C
Devices, and Multiple Masters• Supports Arbitration and Clock Stretching Across
Repeater• Powered-Off High-Impedance I2C Pins• Latch-Up Performance Exceeds 100-mA Per
JESD 78, Class I• ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)– 1000-V Charged-Device Model (C101)
2 Applications• Servers• Routers (Telecom Switching Equipment)• Industrial Equipment• Products with Many I2C Slaves and Long PCB
Traces
3 DescriptionThe PCA9515B is a BiCMOS dual bidirectional bufferintegrated circuit intended for I2C bus and SMBusapplications. The device contains two identicalbidirectional open-drain buffer circuits that enablesI2C and similar bus systems to be extended (or addslaves) without degrading system performance. Thedual bidirectional I2C buffer is operational at 2.3 V to3.6 V VCC.
The PCA9515B buffers both the serial data (SDA)and serial clock (SCL) signals on the I2C bus, whileretaining all the operating modes and features of theI2C system. The device allows two buses, of 400-pFbus capacitance, to be connected in an I2Capplication.
Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)PCA9515B VSSOP (8) 3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum atthe end of the data sheet.
10 Power Supply Recommendations ..................... 1211 Layout................................................................... 13
11.1 Layout Guidelines ................................................. 1311.2 Layout Example .................................................... 13
12 Device and Documentation Support ................. 1412.1 Documentation Support ....................................... 1412.2 Community Resources.......................................... 1412.3 Trademarks ........................................................... 1412.4 Electrostatic Discharge Caution............................ 1412.5 Glossary ................................................................ 14
13 Mechanical, Packaging, and OrderableInformation ........................................................... 14
4 Revision HistoryNOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (May 2013) to Revision B Page
• Added Device Information table, ESD Ratings table, Feature Description section, Device Functional Modes,Application and Implementation section, Power Supply Recommendations section, Layout section, Device andDocumentation Support section, and Mechanical, Packaging, and Orderable Information section. .................................... 1
• Deleted the ordering information. See POA at the end of the datasheet............................................................................... 1
Changes from Original (March 2012) to Revision A Page
• Updated the VOL and VOL - VILC specifications........................................................................................................................ 5
I/O DESCRIPTIONNO. NAME1 NC — No internal connection2 SCL0 I/O Serial clock bus 03 SDA0 I/O Serial data bus 04 GND — Supply ground5 EN I Active-high repeater enable input6 SDA1 I/O Serial data bus 17 SCL1 I/O Serial clock bus 18 VCC — Supply power
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratingsonly, which do not imply functional operation of the device at these or any other conditions beyond those indicated under RecommendedOperating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
6 Specifications
6.1 Absolute Maximum Ratingsover operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNITVCC Supply voltage –0.5 7 VVI Enable input voltage (2) –0.5 7 VVI/O I2C bus voltage (2) –0.5 7 VIIK Input clamp current VI < 0 –50 mAIOK Output clamp current VO < 0 –50 mAIO Continuous output current ±50 mA
Continuous current through VCC or GND ±100 mATstg Storage temperature –65 150 °C
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.2 ESD RatingsVALUE UNIT
V(ESD)Electrostaticdischarge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±2000V
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±1000
(1) VIL specification is for the EN input and the first low level seen by the SDAx and SCLx lines. VILc is for the second and subsequent lowlevels seen by the SDAx and SCLx lines. VILc must be at least 70 mV below VOL.
SDAx,SCLx VI = 3.6 V EN = L or H 0 V to 2.3 V 1 μA
Cin Input capacitanceEN
VI = 3 V or GND3.3 V 7 9
pFSDAx,SCLx EN = H 3.3 V 7 9
6.6 Timing Requirementsover recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
VCC MIN MAX UNIT
tsu Setup time, EN↑ before Start condition2.5 V ± 0.2 V 100
ns3.3 V ± 0.3 V 100
th Hold time, EN↓ after Stop condition2.5 V ± 0.2 V 130
ns3.3 V ± 0.3 V 100
(1) All typical values are at nominal supply voltage (VCC = 2.5 V or 3.3 V) and TA = 25°C.(2) Different load resistance and capacitance alter the RC time constant, thereby changing the propagation delay and transition times.
A. RT termination resistance should be equal to ZOUT of pulse generators.B. CL includes probe and jig capacitance.C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω,
slew rate ≥ 1 V/ns.D. The outputs are measured one at a time, with one transition per measurement.
8.1 OverviewThe PCA9515B is a BiCMOS dual bidirectional buffer integrated circuit intended for I2C bus and SMBusapplications. The device contains two identical bidirectional open-drain buffer circuits that enables I2C andsimilar bus systems to be extended without degrading system performance. This device enables I2C andsimilar bus systems to be extended (and add more slaves) without degradation of performance. The dualbidirectional I2C buffer is operational at 2.3 V to 3.6 V VCC.The PCA9515B buffers both the serial data (SDA) and serial clock (SCL) signals on the I2C bus, whileretaining all the operating modes and features of the I2C system. The device allows two buses, of 400-pFbus capacitance, to be connected in an I2C application.The I2C bus capacitance limit of 400 pF restricts the number of slave devices and bus length. Using thePCA9515B, a system designer can capacitively isolate two halves of a bus, thus accommodating more I2Cdevices and longer trace lengths.The PCA9515B has an active-high enable (EN) input with an internal pull-up. This allows users to selectwhen the repeater is active and isolate malfunctioning slaves on power-up reset. States should never bechanged during an I2C operation. Disabling during a bus operation will hang the bus and enabling part waythrough a bus cycle may confuse the I2C parts being enabled. The EN input should only change state whenthe global bus and the repeater port are in an idle state to prevent system failures.The PCA9515B can also be used to operate two buses, one at 5 V interface levels and the other at 3.3 Vinterface levels. The buses may also function at 400-kHz or 100-kHz operating frequency. If the two busesare operating at different frequencies, the 100-kHz bus must be isolated if the operation of the 400-kHz busis required. If the master is running at 400-kHz, the maximum system operating frequency may be less than400 kHz because of the delays added by the repeater.The low level outputs for each internal buffer are approximately 0.5 V; however, the input voltage of eachinternal buffer must be 70 mV or more below the low level output when the output is driven low internally.This prevents a lockup condition from occurring when the input low condition is released.Two or more PCA9515B devices cannot be used in series. Since there is no direction pin, different valid low-voltage levels are used to avoid lockup conditions between the input and the output of each repeater. A validlow, applied at the input of a PCA9515B, is propagated as a buffered low with a higher value on the enabledoutputs. When this buffered low is applied to another PCA9515B-type device in series, the second devicedoes not recognize it as a valid low and does not propagate it as a buffered low.The device contains a power-up control circuit that sets an internal latch to prevent the output circuits frombecoming active until VCC is at a valid level (VCC = 2.3 V).As with the standard I2C system, pullup resistors are required to provide the logic high levels on the bufferedbus. The PCA9515B has standard open-collector configuration of the I2C bus. The size of the pullup resistorsdepend on the system; however, each side of the repeater must have a pullup resistor. The device isdesigned to work with Standard Mode and Fast Mode I2C devices in addition to SMBus devices.Standard Mode I2C devices only specify a 3 mA termination current in a generic I2C system whereStandard Mode devices and multiple masters are possible. Under certain conditions, high terminationcurrents can be used.
8.3.1 Two-Channel Bidirectional BufferThe PCA9515B is a two-channel bidirectional buffer for open-drain applications like I2C and SMBus.
8.3.2 Bidirectional Voltage-Level TranslationThe PCA9515B allows bidirectional voltage-level translation (up-translation and down-translation) between lowvoltages (down to 2.3 V) and higher voltages (up to 5.5 V).
8.3.3 Active-High Enable InputThe PCA9515B has an active-high enable (EN) input with an internal pull-up to VCC. The enable input needs tobe pulled to GND to disable the PCA9515B and isolate the I2C buses. Pulling-up the enable pin or floating theenable pin causes the PCA9515B to turn on and buffer the I2C bus.
8.4 Device Functional ModesThe PCA9515B has an active-high enable (EN) input with an internal pull-up to VCC, which allows the user toselect when the repeater is active. This can be used to isolate a badly behaved slave on power-up reset. Itshould never change state during an I2C operation, because disabling during a bus operation my hang the bus,and enabling part way through the bus cycles could confuse the I2C parts being enabled. The EN input shouldonly change state when the global bus and repeater port are in the idle state to prevent system failures. Table 1lists the PCA9515B functions.
NOTEInformation in the following applications sections is not part of the TI componentspecification, and TI does not warrant its accuracy or completeness. TI’s customers areresponsible for determining suitability of components for their purposes. Customers shouldvalidate and test their design implementation to confirm system functionality.
9.1 Application InformationThe PCA9515B is typically used to buffer an I2C signal, isolating capacitance from two sides of the bus. Thisallows for longer traces and cables, and a more robust I2C communication. Typical Application section describeshow the PCA9515B may be used to isolate a standard mode and fast mode I2C bus, to allow for fastercommunications when required, but maintaining compatibility with the slower standard mode slave device.
It is critical to keep the VOL and VIL requirements in mind when designing with buffers, especially when usingmultiple buffers/translators on the same node. Care must be taken to not violate the VIL requirement of a buffer,otherwise I2C communication errors will occur. An example of this would be a buffer with a VOL of ~0.5 V, and adevice requires a VIL of less than 0.4 V. Such a connection would result in the slave device being unable torecognize the output low signal as a valid low.
9.2 Typical ApplicationA typical application is shown in Figure 5. In this example, the system master is running on a 3.3 V I2C bus, whilethe slave is connected to a 5-V bus. Both buses run at 100 kHz, unless the slave bus is isolated. If the slave busis isolated (by pulling the EN pin low), the master bus can run at 400 kHz. Master devices can be placed oneither bus, the PCA9515B does not care which side the master is on. Decoupling capacitors are required, but arenot shown in Figure 5 for simplicity.
Figure 5. Typical Application
9.2.1 Design RequirementsTable 2 lists the design requirements.
Table 2. Design RequirementsPARAMETER VALUE
Input-side I2C signal 3.3 VOutput-side I2C signal 5 V
9.2.2 Detailed Design ProcedureThe PCA9515B is 5.5 V tolerant, so it does not require any additional circuitry to translate between the differentbus voltages. When one side of the PCA9515B is pulled low by a device on the I2C bus, a CMOS hysteresis-typeinput detects the falling edge and causes an internal driver on the other side to turn on, thus causing the otherside also to go low. The side driven low by the PCA9515B typically is at VOL = 0.5 V.
Figure 6 and Figure 7 show the waveforms that are seen in a typical application. If the bus master in Figure 5writes to the slave through the PCA9515B, Bus 0 has the waveform shown in Figure 6. The waveform looks likea normal I2C transmission until the falling edge of the eighth clock pulse. At that point, the master releases thedata line (SDA) while the slave pulls it low through the PCA9515B. Because the VOL of the PCA9515B typically isaround 0.5 V, a step in the SDA is seen. After the master has transmitted the ninth clock pulse, the slavereleases the data line.
On the Bus 1 side of the PCA9515B, the clock and data lines have a positive offset from ground equal to the VOLof the PCA9515B. After the eighth clock pulse, the data line is pulled to the VOL of the slave device, which is veryclose to ground in the example.
9.2.3 Application Curves
Figure 6. Bus 0 Waveforms
Figure 7. Bus 1 Waveforms
10 Power Supply RecommendationsFor VCC, a 2.3 V to 3.6 V power supply is required. Standard decoupling capacitors are recommended. Thesecapacitors typically range from 0.1 µF to 1 µF, but the ideal capacitance depends on the amount of noise fromthe power supply.
11.1 Layout GuidelinesFor printed circuit board (PCB) layout of the PCA9515B, common PCB layout practices should be followed. In allPCB layouts, it is a best practice to avoid right angles in signal traces, to fan out signal traces away from eachother upon leaving the vicinity of an integrated circuit (IC), and to use thicker trace widths to carry higheramounts of current that commonly pass through power and ground traces. By-pass and de-coupling capacitorsare commonly used to control the voltage on the VCC pin, using a larger capacitor to provide additional power inthe event of a short power supply glitch and a small capacitor to filter out high-frequency ripple. Thesedecoupling capacitors should be placed as close to the VCC pin of PCA9515B as possible.
The layout example shown in Figure 8 shows a 4 layer board, which is preferable for boards with higher densitysignal routing. On a 4 layer PCB, it is common to route signals on the top and bottom layer, dedicate one internallayer to a ground plane, and one to power plane. In a board layout using planes or split planes for power andground, vias are placed directly next to the surface mount component pad which needs to attach to VCC or GNDand the via is connected electrically to the internal layer on the other side of the board. Vias are also used whena signal trace needs to be routed to the opposite side of the board. This routing and via is not necessary if VCCand GND are both full planes as opposed to the partial planes depicted.
12.1.1 Related DocumentationFor related documentation see the following:• I2C Bus Pullup Resistor Calculation, SLVA689• Maximum Clock Frequency of I2C Bus Using Repeaters, SLVA695• Introduction to Logic, SLVA700• Understanding the I2C Bus, SLVA704
12.2 Community ResourcesThe following links connect to TI community resources. Linked contents are provided "AS IS" by the respectivecontributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms ofUse.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaborationamong engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and helpsolve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools andcontact information for technical support.
12.3 TrademarksE2E is a trademark of Texas Instruments.All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge CautionThis integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled withappropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be moresusceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.5 GlossarySLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable InformationThe following pages include mechanical, packaging, and orderable information. This information is the mostcurrent data available for the designated devices. This data is subject to change without notice and revision ofthis document. For browser-based versions of this data sheet, refer to the left-hand navigation.
PCA9515BDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS& no Sb/Br)
CU NIPDAU |CU NIPDAUAG
Level-1-260C-UNLIM -40 to 85 (7SE ~ 7SF)
(1) The marketing status values are defined as follows:ACTIVE: Product device recommended for new designs.LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availabilityinformation and additional product content details.TBD: The Pb-Free/Green conversion plan has not been defined.Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement thatlead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used betweenthe die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weightin homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
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(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuationof the previous line and the two combined represent the entire Device Marking for that device.
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