AN-B009

Application Notes

206-1000-009 Rev. 1.4, 06/30/2020 1

Chrontel

PCB Layout and Design Guide for CH7036 RGB/HDMI/LVDS Encoder

1.0 Introduction

The CH7036 is specifically designed for consumer electronics device and PC markets in which multiple high definition

content display formats are required. With its advanced video encoder, flexible scaling engine and easy-to-configure

audio interface, the CH7036 satisfies manufactures’ products display requirements and reduce their costs of development

and time-to-market.

This application note focuses only on the basic PCB layout and design guidelines for CH7036 RGB/HDMI/LVDS

Encoder. Guidelines in component placement, power supply decoupling, grounding, input /output signal interface are

discussed in this document.

The discussion and figures that follow reflect and describe connections based on the 88-pin QFN package of the CH7036.

Please refer to the CH7036datasheet for the details of the pin assignments.

2.0 Component Placement and Design Considerations

Components associated with the CH7036 should be placed as close as possible to the respective pins. The following

discussion will describe guidelines on how to connect critical pins, as well as describe the guidelines for the placement

and layout of components associated with these pins.

2.1 Power Supply Decoupling

The optimum power supply decoupling is accomplished by placing a 0.1μF ceramic capacitor to each of the power

supply pins as shown in Figure 1. These 0.1μF capacitors should be connected as close as possible to their respective

power and ground pins using short and wide traces to minimize lead inductance. Whenever possible, a physical

connecting trace should connect the ground pins of the decoupling capacitors to the CH7036 ground pins, in addition to

ground vias.

2.1.1 Ground Pins

The analog and digital grounds of the CH7036 should be connected to a common ground plane to provide a low

impedance return path for the supply currents. Whenever possible, each of the CH7036 ground pins should be connected

to its respective decoupling capacitor ground lead directly, then connected to the ground plane through a ground via.

Short and wide traces should be used to minimize the lead inductance. Refer to Table 1 for the Ground pins assignment.

2.1.2 Power Supply Pins

There are nine power supply pins, VDDH, VDDR, VDDT, DVDD, AVDD, AVDD_PLL, AVDD_DAC, VDDMQ,

VDDMS. Refer to Table 1 for the Power supply pins assignment. Refer to Figure 1 for Power Supply Decoupling.

Table 1: Power Supply Pins Assignment of the CH7036

Pin Assignment # of Pins Type Symbol Description

11,12 2 Power VDDH HDMI supply voltage (3.3V)

23 1 Power VDDR LVDS Input supply voltage (3.3V)

40 1 Power VDDT LVDS Output supply voltage (3.3V)

19,57 2 Power DVDD Digital supply voltage (1.8V)

46,79 2 Power AVDD Analog supply voltage (2.5V~3.3V)

1,20 2 Power AVDD_PLL PLL supply voltage (1.8V)

69,73 2 Power AVDD_DAC DAC power supply (2.5~3.3V)

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2 206-1000-009 Rev. 1.4, 06/30/2020

54,62 2 Power VDDMQ SDRAM output buffer supply voltage (3.3V)

4,61 2 Power VDDMS SDRAM device supply voltage (3.3V)

6,17 2 Ground VSSH HDMI supply ground

22 1 Ground VSSR LVDS Input supply ground

45 1 Ground VSST LVDS Output supply ground

18,56 2 Ground DGND Digital supply ground

50,82 4 Ground AGND Analog supply ground

2,21 2 Ground AGND_PLL PLL supply ground

71,75 2 Ground AGND_DAC DAC supply ground

55,63 2 Ground GNDMQ SDRAM output buffer supply ground

5,60 2 Ground GNDMS SDRAM device supply ground

Thermal

Exposed Pad

Ground Connect to ground plane through thermal via

VCC3_3

VDDRVDDRVDDR

C31

10uf

L11

47R 100MHz

1 2 VDDTVDDT

VCC3_3

VDDTVDDT

C24

0.1uF

C29

10uf

C38

0.1uF

C39

10uf

AVDD_DACL15

47R 100MHz

1 2

C37

0.1uF

VDDH

C34

10uf

AVDD_PLLL13

47R 100MHz

1 2

C23

0.1uF

C35

0.1uF

C36

10uf

U6

CH7035

DVDD19,57

VDDMQ54,62

VDDMS4,61

AVDD46,79

AVDD_PLL1,20

VDDH11,12

DGND18,56

GNDMQ55,63

GNDMS5,60

AGND50,82

AGND_PLL2,21

VSSH6,17

VDDR23

VSSR22

VDDT40

VSST45

AVDD_DAC69,73

AGND_DAC71,75

The

rma

l Pa

d8

9C19

0.1uF

C20

0.1uF

C21

0.1uF

CH7036

C28

0.1uF

C30

10uf

VCC1_8 C25

0.1uF

C41

10uf

C40

0.1uF

VDDMSL16

47R 100MHz

1 2

L9

47R 100MHz

1 2

L10

47R 100MHz

1 2

C26

0.1uF

C42

0.1uF

C43

10uf

VDDMQL17

47R 100MHz

1 2

DVDD

C32

10uf

DVDDL12

47R 100MHz

1 2

C22

0.1uF

VDDRVDDRVDDR

AVDD

C33

0.1uF

L14

47R 100MHz

1 2

Figure 1: Power Supply Decoupling and Distribution

Note: All the Ferrite Beads described in this document are recommended to have an impedance of less than 0.05 Ω at DC; 23 Ω at

25MHz & 47 Ω at 100MHz. Please refer to Fair Rite part #2743019447 for details or an equivalent part can be used for the diagram.

2.2 Power On and Reset

RSTB pin is the chip reset pin of CH7036. CH7036 will be reset when this pin is low. A power reset switch can be

placed on the RSTB pin on the PCB as hardware reset for CH7036 as shown in Figure 5. When the pin is high, the

reset function can also be controlled through the serial port.

There are two reset methods. One is RC reset. The power supply should be valid and stable for at least 9ms before

RSTB becomes invalid as shown in Figure 2. A 1 MΩ and 0.1uF RC reset circuit is recommended.

CHRONTEL AN-B009

206-1000-009 Rev. 1.4, 06/30/2020 3

Power supply(3.3V and 1.8V)

RSTB

T1>9ms

Figure 2: Power on and reset timing of RC

Another method is using an external reset signal. In this case, the power supply should be valid and stable for at least

9ms before the reset signal is valid. The pulse width of valid reset signal should be at least 100us. The timing is shown

in Figure 3.

T2>100usT1>9ms

RSTB

Power supply(3.3V and 1.8V)

Figure 3: Power on and reset timing of external reset

Note: 1. The power supply will be valid when it rises to 90% of standard level.

2. The rising threshold of RSTB is 2.4V.

3. The falling threshold of RSTB is 0.4V.

2.3 General Control Pins

• ISET and RESERVED

ISET pin sets the DAC current. A 1.2 KΩ, 1% tolerance resistor should be connected between this pin and

AGND_DAC using short and wide traces as shown in Figure 4.

The RESERVED pins (Pin3 and Pin66) should be pulled low through 10 KΩ resistors.

• GPI1, GPI2 and PDB

GPI1 and GPI2 can be used as input pins controlled by MCU.

PDB controls to power down the whole chip when it is low. After PDB pin is pulled high again, the CH7036 will be

reset.

R2 10k

R3 10k

U1

CH7036

GPI277

GPI178

PDB49

ISET76

RESERVED3

RESERVED66

AUDDAC48

IRQ85

From_SOC_Control_Pin

From_SOC_Control_Pin

R1 1.2k(1% tolerance) Used as input Pin

Used as input Pin

From_SOC_Control_Pin

Figure 4: General Control Pins (A)

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4 206-1000-009 Rev. 1.4, 06/30/2020

• AUDDAC and IRQ

AUDDAC is Audio control output pin. This pin should be connected to SOC directly.

IRQ is Interrupt output pin. This pin should be connected to SOC directly. This Pins’ default output is 3.3V CMOS level, and

can also work as open drain structure for other voltages.

• XI and XO

If only using RGB output mode, CH7036 has capability to accept external clocks with frequencies from 2.3 MHz to 64

MHz. However, if using HDMI output mode, the crystal must be 27MHz.

The crystal load capacitance, CL, is usually specified in the crystal spec from the vendor. As an example to show the

load capacitors Figure 5 gives a reference design for crystal circuit design.

CH7036

RESETB

U1

RSTB83

XI67

XO68

VCC3_3

SW4

P8058SS-NDC30.1u

R11M

X4

535-9118-1-ND (27 MHz)

GND4

P11

GND2

P23

XI/FIN

XO

C2

18pF1

2C1

18pF

12

Figure 5: General Control Pins (B)

• Reference Crystal Oscillator

CH7036 includes an oscillator circuit that allows a predefined-frequency crystal to be connected directly. Alternatively,

an externally generated clock source may be supplied to CH7036. If an external clock source is used, it should have

CMOS level specifications. The clock should be connected to the XI pin, and the XO pin should be left open. The

external source must exhibit ±50 ppm or better frequency accuracy, and have low jitter characteristics.

If a crystal is used, the designer should ensure that the following conditions are met:

The crystal is specified to be predefined-frequency, ±50 ppm fundamental type and in parallel resonance (NOT series

resonance). The crystal should also have a load capacitance equal to its specified value (CL).

External load capacitors have their ground connection very close to CH7036 (Cext).

To be able to tune, a variable capacitor may be connected from XI to ground.

Note that the XI and XO pins each has approximately 10 pF (Cint) of shunt capacitance internal to the device. To

calculate the proper external load capacitance to be added to the XI and XO pins, the following calculation should be

used:

Cext = (2 x CL) - Cint - 2CS

Where

CHRONTEL AN-B009

206-1000-009 Rev. 1.4, 06/30/2020 5

Cext = external load capacitance required on XI and XO pins.

CL = crystal load capacitance specified by crystal manufacturer.

Cint = capacitance internal to CH7036 (approximately 10-15 pF on each of XI and XO pins).

CS = stray capacitance of the circuit (i.e. routing capacitance on the PCB, associated capacitance of crystal holder from

pin to pin etc.).

In general,

CintXI = CintXO = Cint

CextXI = CextXO = Cext

such that CL = (Cint + Cext) / 2 + CS and Cext = 2 (CL - CS) - Cint=2CL - (2CS + Cint)

Therefore CL must be specified greater than Cint /2 + CS in order to select Cext properly.

After CL (crystal load capacitance) is properly selected, care should be taken to make sure the crystal is not operating in

an excessive drive level specified by the crystal manufacturer. Otherwise, the crystal will age quickly and that in turn

will affect the operating frequency of the crystal.

For detail considerations of crystal oscillator design, please refer to AN-06.

2.4 Serial Port Control for CH7036

• SPC and SPD

SPD and SPC function as a serial interface where SPD is bi-directional data and SPC is an input only serial clock. In

the reference design, SPD and SPC pins are pulled up to AVDD with 5.6 KΩ resistors as shown in Figure 6. If the

driver can support, SMBUS or LVDS DDC can be used to access CH7036 by the serial interface.

• DDC_SC and DDC_SD

DDC_SC and DDC_SD are used to interface with the DDC of HDMI receiver. This DDC pair needs to be pulled up to

5V through R3 and R4 as shown in Figure 6. R3 and R4’s value should be from 1.5 KΩ to 2 KΩ according to the

HDMI Specification. An EEPROM CH9903 can be added in DDC bus. The CH9903 is used to save the HDCP key in

it, and its device address should not be 0x54. • PROM_SC and PROM_SD

This Serial Port is used to load the firmware from external EEPROM CH9904. This serial pair needs to be pulled up to

3.3V through 10 KΩ resistors as shown in Figure 6. The CH9904 device address should be 0xAE.

CH7036

U1

SPC86

DDC_SC64

DDC_SD65

SPD87PROM_SC

81

PROM_SD80

VDD5

U2

CH9904

GP11

GP22

GP33

GND4

SPD5SPC6WE7VCC8

C1

0.1uF

12

R810K

U7

CH9903

GP11

GP22

GP33

GND4

SPD5SPC6WE7VCC8

C2

0.1uF

12

D6SM5817

D7SM5817

R1

5.6K

12

R2

5.6K

12

SPC

DDC_SD

SPD

VCC3_3

R3

1.8K

12

R4

1.8K

12

VDD5_VGA_DDC

VDD5_VGA_DDC

VDD5_VGA_DDC VDD5_HDMI_DDC

VDD5_HDMI_DDC VDD5_HDMI_DDC

To avoid back drive, 2 options

1. Use a low forward voltage diode.

2. Use a independent 5V power supply.

R8

10K

12

DDC_SC

R9

10K

12

R6

10K

12

R5

10K

12

VDD5

DDC_SCR12 10k

R1010k

CH9903 is used to save the HDCP key.

DDC_SD

R7

10K

12

PROM_SDPROM_SC

Figure 6: Serial Port Interface of CH7036

This Serial Port also can be used as the VGA DDC bus. They should be pulled up to 5V through 10 k Ω resistors as

shown in Figure 14.

CHRONTEL AN-B009

6 206-1000-009 Rev. 1.4, 06/30/2020

Note: Because some TV or monitor have internal 5V pull-up resistors on DDC trace, the 5V pull-up voltage will

remain on DDC trace when TV or monitor is in standby mode. In order to avoid back drive, the power for DDC circuit

of CH7036 should be independent 5V power supply. Using a diode with low forward voltage is another option. It is

better that the forward voltage of the diode does not exceed 0.3V to avoid the voltage on pull-up resistors drops too low.

2.5 SPDIF Interface

IIS_D/SPDIF (pin 53) is a multi-function input pin. It can be configured to SPDIF audio input pin or IIS data input pin.

The SPDIF signal has two voltage levels, so there are two input ways for CH7036. If SPDIF signal from audio codec is COMS

or TTL level (3.3V~5V), it can be connected to the CH7036 directly. If SPDIF signal is COAX level (0.5V~1V), a voltage level

shifting is required as shown in Figure 7.

VCC2_5/3_3

5 6

14

7

U22C

74HCU04/SO_0

3 4

14

7

U23B

74HCU04/SO_0

SPDIFSPDIFSPDIFSPDIFSPDIF

R18330

R1975

1

2

H1

H2 J5

SPDIF INR20

10K

R21

100

C27

0.1uF

R22

10K

SPDIF

Figure 7: SPDIF pin of CH7036

Note1: It is recommended that 74HCU04 should be used.

Note2: For 74HCU04/SO, pin7=GND, pin14=VCC=2.5V or 3.3V.

2.6 I2S Interface

I2S audio input can be configured through programming CH7036 registers. An I2S bus design consists of three serial

bus lines: a line with data channel [SD], a word select line [WS], and a clock line [SCK]. Data is transmitted two's

complement, MSB first.

I2S_D/SPDIF53

I2S_CK51

I2S_WS52

U1

CH7036

I2S_D1

I2S_CK3

I2S_WS2

U2

I2S Source

Figure 8: CH7036 I2S Input Pins

2.7 LVDS Input Pins

CH7036 can accept 18bit or 24bit SPWG format data from LVDS transmitter. As shown in Figure 9, Video data

comes from a LVDS transmitter. Since those signals are differential, they must be routed in differential pairs.

A0M2

A1M4

A0P1

A1P3

A2M6A2P5

A3M8A3P7

CLK1M10CLK1P9

U2

LVDS TRANSMITTER

RX024

RX126 RX0B25

RX1B27

RX228

RX2B29

RX3P30

RX3B31

RXC32

RXCB33

U1

CH7036

R5

100

R4

100

R3

100

R2

100

R1

100

Figure 9: CH7036 Data Input Pins

CHRONTEL AN-B009

206-1000-009 Rev. 1.4, 06/30/2020 7

The differential impedance of LVDS pairs should be 100Ω. To maintain constant differential impedance along the

length, it is important to keep the trace width and spacing uniform along the length, as well as maintain good symmetry

between the two lines.

CH7036 LVDS input channel differential pairs have Optional Internal termination resistors of 100Ω inside. It has the

advantage of terminating as close as possible to the receiver (minimizing stubs) and also saving board space and

reducing component count.

It is better to add a termination resistor (100Ω) between the differential pair for backup. The small surface mount

termination resistors should be placed as close to the CH7036 input pins as possible.

CH7036 also support LVDS bypass mode as shown in Figure 10. When only output LVDS signal to Panel, CH7036

can be set to full power down mode to save the current. When using the CH7036 to output HDMI or VGA signal, the

input LVDS pixel clock is up to 75HMz. The LVDS stub trace connected to CH7036 should less than 2 inches.

LVDS Transmiter LCD Panel

CH7036 TVHDMI/VGA

LVDS

Figure 10: CH7036 LVDS bypass mode

2.8 HDMI Outputs

The TLC, TLCB, TDC [2:0], TDCB [2:0] signals are high frequency differential signals that need to be routed with

special precautions. Since those signals are differential, they must be routed in differential pairs.

2.8.1 Differential Pair Impedance

To match the external cable impedance and maintain the maximal energy efficiency it is important to meet the

impedance target of 100 Ω ± 10% for the differential data/clock traces. The restriction of this impedance target is to

prevent any loss of signal strengths resulting from a reflection of unwanted signals. The impedance can be acquired by

proper design of trace length, trace width, signal layer thickness, board dielectric, etc. The HDMI differential pairs

should be routed on the top layer directly to the HDMI connector pads if possible.

2.8.2 Trace Routing Length

To prevent from capacitive and impedance loading, trace lengths should be kept as minimal as possible. Vias and bends

should always be minimized; inductive effects may be introduced, causing spikes in the signals. Trace routing lengths

from CH7036 to the HDMI/DVI connector are limited to a maximum of 2 inches. The CH7036 should be as close to

the HDMI/DVI connector as possible.

2.8.3 Length Matching for Differential Pairs

The HDMI/DVI specifies the intra-pair skew and the inter-pair skew as in Table 2. The intra-pair skew is the

maximum allowable time difference on both low-to-high and high-to-low transitions between the true and complement

CHRONTEL AN-B009

8 206-1000-009 Rev. 1.4, 06/30/2020

signals. The inter-pair skew is the maximum allowable time difference on both low-to-high and high-to-low transitions

between any two single-ended data signals that do not constitute a differential pair.

Table 2: Maximum Skews for the HDMI/DVI Transmitter

Skew Type Maximum at Transmitter

Intra-Pair Skew 0.15 Tbit

Inter-Pair Skew 0.20 TPixel

Where Tbit is defined as the reciprocal of Data Transfer Rate and TPixel is defined as the reciprocal of Clock Rate.

Therefore, TPixel is 10 times Tbit. In other words, the intra-pair length matching is much more stringent than the inter-

pair length matching.

It is recommended that length matching of both signals of a differential pair be within 5 mils. Length matching should

occur on a segment by segment basis. Segments might include the path between vias, resistor pads, capacitor pads, a

pin, an edge-finger pad, or any combinations of them, etc. Length matching from one pair to any other should be within

100 mils.

Note that lengths should only be counted to the pins or pad edge. Additional etch within the edge-finger pad, for

instance, is electrically considered part of the pad itself.

2.8.4 ESD Protection for HDMI/DVI Interface

In order to minimize the hazard of ESD, a set of protection diodes are highly recommended for each

HDMI Outputs (data and clock).

International standard EN 55024:1998 establishes 4kV as the common immunity requirement for contact discharges in

electronic systems. 8kV is also established as the common immunity requirement for air discharges in electronic

systems. International standard EN 61000-4-2:1995 / IEC 1000-4-2:1995 establishes the immunity testing and

measurement techniques.

System level ESD testing to International standard EN 61000-4-2:1995 / IEC 1000-4-2:1995 has confirmed that the

proper implementation of Chrontel's recommended diode protection circuitry, using SEMTECH Rclamp0524P diode

array devices, will protect the CH7036 device from HDMI panel discharges of greater than 8kV (contact) and 16kV

(air). The RClampTM0524P have a typical capacitance of only 0.30pF between I/O pins. This low capacitance won’t

bring too much bad effect on HDMI eye diagram test.

Figure 11 shows the connection of HDMI connectors, including the recommended design of SEMTECH Rclamp0524P

diode array devices. HDMI connector is used to connect the CH7036 HDMI outputs to the display panels.

CHRONTEL AN-B009

206-1000-009 Rev. 1.4, 06/30/2020 9

TLC*

TDC2

TLC

TDC2

TLC*

TDC2*

TLC

RClamp0524P

I/O 11

I/O 79

I/O 22

GND3

I/O 34

I/O 45

I/O 56

I/O 67

GND8

I/O 810

TDC2*

R11.8k

R21.8k

VDD5

TLC*

TLC

TDC1*

TDC1

TDC0*

TDC0

TDC2*

VDD5

C210uf

C10.1ufR3

47k HDMI Conn

TMDA Data2+1

TMDA Data2 Shield2

TMDA Data2-3

TMDA Data1+4

TMDA Data1 Shield5

TMDA Data1-6

TMDA Data0+7

TMDA Data0 Shield8

TMDA Data0-9

TMDA Clock+10

TMDA TMDA Clock Shield11

TMDA Clock-12

CEC13

Reserved14

SCL15

SDA16

DDC/CEC Ground17

+5V Power18

HPDET19

C30.22uf

HPD F1 MINISMDC050CT-ND

TDC2

D9SM5817

DDC_SD

To avoid back drive, 2 options

1. Use a low forward voltage diode.

2. Use a independent 5V power supply.

DDC_SD

TDC1

TDC0

TDC1*

TDC0*

TDC1*

TDC1

TDC0

RClamp0524P

I/O 11

I/O 79

I/O 22

GND3

I/O 34

I/O 45

I/O 56

I/O 67

GND8

I/O 810

TDC0*

DDC_SC

DDC_SC

HPD

DDC_SD

HPD

DDC_SC

RClamp0524P

I/O 11

I/O 79

I/O 22

GND3

I/O 34

I/O 45

I/O 56

I/O 67

GND8

I/O 810

Figure 11: The connection of the HDMI outputs with ESD protection

2.8.5 Description for each HDMI Interface Pins

• HDMI Link Data Channel (TDC [2:0] and TDCB [2:0])

These pins provide HDMI differential outputs for data channel 0 (blue), data channel 1 (green) and data channel 2 (red). It is

recommended that an impedance compensation circuit be added for each differential pair, including HDMI Clock outputs (Refer

to Figure 12).

Figure 12(a) shows the RC bridge between the Differential pairs. These RC bridges can be optional soldered to prevent

the EMI issue. It also can be used as impedance compensation to improve the HDMI eye diagram quality. A

recommended bridge for all the data/clock differential pairs is with 240Ω resistance value as shown in Figure 12(b).

Please note that the optimal bridge RC values may be varied in terms of the impedance characteristics of the PCB

layout. Some CH7036 register setting changes may be required in terms of the bridge construction, refer to Table 3.

R1

TLCB7

TDC2B15

TDC216

TLC8

TDC0B9

TDC010

TDC1B13

TDC114

HPD88

DDC_SD65

DDC_SC64

U1

CH7036

HDMI_TX0B

HDMI_TLCB

R2 C2

R3

HDMI_TX1B

HDMI_TX1C3

R4 HDMI_TX2

HDMI_TX2B

C4

DDC_SD

DDC_SC

HDMI_HPD

C1 HDMI_TLC

HDMI_TX0

(a) Typical RC bridge for each differential pair (b) Recommended bridge for each differential pair

Figure 12: The connection of the HDMI outputs

Table 3: Register change list when using 240 Ω terminal resistors

Address Value

R2_0Ah 0x03

HDMI_TLCB

R1 120

TLCB7

TDC2B15

TDC216

TLC8

TDC0B9

TDC010

TDC1B13

TDC114

HPD88

DDC_SD65

DDC_SC64

U1

CH7036

DDC_SD

DDC_SC

HDMI_HPD

R3 120

HDMI_TX0B

R4 120 HDMI_TX0

R2 120

HDMI_TX1B

R5 120 R6 120 HDMI_TX1

HDMI_TLC

R7 120

HDMI_TX2B

R8 120 HDMI_TX2

CHRONTEL AN-B009

10 206-1000-009 Rev. 1.4, 06/30/2020

R2_0Bh 0xED

R2_0Ch 0x74

R2_0Dh 0x51

• HDMI Link Clock Outputs (TLC and TLCB)

These pins provide the HDMI differential clock outputs for HDMI corresponding to data on the TDC [2:0] and TDCB[2:0]

outputs (Refer to Figure 12).

• HPD (HDMI Hot Plug Detect)

This input pin determines whether the HDMI link is connected to a HDMI panel, it should be pulled low with a 47 k Ω resistor.

When the panel is connected, the HPD will be given a voltage greater than 2.4 volts.

• SCL and SDA (DDC bus)

The Display Data Channel is used by CH7036 to determine the capabilities and characteristics of the Panel by reading the E-

EDID data structure. These two pins should be connected to DDC_SD and DDC_SC of CH7036, and pull up to 5V with 1.8

KΩ resistors.

2.9 LVDS Output Pins

• LVDS output Pins

CH7036 can Output 18bit or 24bit SPWG format data for LVDS Panel, as shown in Figure 13. Since those signals are

differential, they must be routed in pairs. The Differential impedance of differential lines should be the same with the

Panel termination resistor.

A0M2

A1M4

A0P1

A1P3

A2M6 A2P5

A3M8 A3P7

CLK1M10 CLK1P9

U2

LVDS Panel Connector

LDC034

LDC136LDC0B35

LDC1B37

LDC238

LDC2B38

LDC341

LDC3B42

LLC43

LLCB44

U1

CH7036

Figure 13: The connection of the HDMI outputs－CH7036 HDMI connectors

• PWM

This pin is for Backlight brightness adjustment. It has a default output 3.3V CMOS level. It output a square waveform,

and its duty-cycle as well as frequency can be adjusted through the Register.

2.10 RGB Output Pins

DAC0~2

Three on-chip 10-bit high speed DACs provide RGB output. If the DACs require a double termination, a 75

resistor should be placed between each DAC pin and the ground as shown in Figure 14.

HSO and VSO

The HSO and VSO are COMS output Pins, the voltage level is the same with AVDD. The buffer, 74ACT08, have level

shift function. It should be used to make sure CH7036 can drive monitor properly.

CHRONTEL AN-B009

206-1000-009 Rev. 1.4, 06/30/2020 11

R17

10k

12

VSO

HSO

D8SM5817

To avoid back drive, 2 opions:

1. Use a low forward voltage diode.

2. Use a independent 5V power supply.

U4A

74ACT08

A1

B2 Y

3

VC

C14

VDD5 POWER SUPPLY

R

U20B

74ACT08

A4

B5 Y

6

G

MONGREEN

MONBLUE

L3

47R_100MHz

1 2L4

47R_100MHz

1 2

C10

22pF

C11

22pF

L8150-220R 100MHz 1 2

VGA Output Connector

B

L7150-220R 100MHz 1 2

C1

10pF

12

C2

22pF

12

C3

10pF

12

L1

47R_100MHz

1 2

P1

VGA

11

22

33

44

55

66

77

88

99

1010

1111

1212

1313

1414

1515

16

16

17

17

L2

47R_100MHz

1 2

C4

10pF

12

C5

22pF

12

MONRED

C6

10pF

12

MONHSYNC

C7

10pF

12

L5

47R_100MHz

1 2

R1

75R

12

C8

22pF

12

L6

47R_100MHz

1 2

C9

10pF

12

R4 331 2

MONVSYNC

R2

75R

12

R5 331 2

R3

75R

12

VGA_DDC_SC

R23

10k

12U1

CH7036

DAC074

DAC172

DAC270

HSO58

VSO59

PROM_SC81

PROM_SD80 VGA_DDC_SD

VDD5

VGA_DDC_SC

VGA_DDC_SD

D2

AZ5125-01H

D1

AZ5125-01H

D3

AZ5125-01H

D4

AZ5125-01H

D5

AZ5125-01H

VDD5

Figure 14: The CH7036 RGB outputs

2.11 Thermal Exposed Pad Package

The CH7036 is available in 88-pin QFN package with thermal exposed pad package. The advantage of the thermal

exposed pad package is that the heat can be dissipated through the ground layer of the PCB more efficiently. When

properly implemented, the exposed pad package provides a means of reducing the thermal resistance of the CH7036.

Careful attention to the design of the PCB layout is required for good thermal performance. For maximum heat

dissipation, the exposed pad of the package should be soldered to the PCB as shown in Figure 15.

Die

Exposed Pad

Solder

PCB

Pin

Figure 15: Cross-section of exposed pad package

Thermal pad dimension is from 6.6mm to 6.9mm (min to max), 6.6mm x 6.6mm is the minimum size recommended for

the thermal pad, and 6.9mm x 6.9mm is the maximum size. As shown in Figure 16, the thermal land pattern should

have a 5x5 grid array of 1.0 mm pitch thermal vias connected to the ground layer of the PCB. These vias should be

0.3mm in diameter with 1 oz copper via barrel plating.

CHRONTEL AN-B009

12 206-1000-009 Rev. 1.4, 06/30/2020

6.6

mm

6.6 mm Exposed Pad

land pattern

Thermal Via Array

(5x5) 1 mm Pitch

0.3 mm diameter

Figure 16: Thermal Land Pattern

When applying solder paste to the thermal land pattern, the recommended stencil thickness is from 5 to 8 mils. Thermal

resistance was calculated using the thermal simulation program called ANSYS.

2.12 QFN Package Assembly

For the assembly process, it is important to limit the amount of solder paste that is put under the thermal pad. If too

much paste is put on the PCB, the package may float during assembly. Compared with the solder mask of thermal pad,

the paste mask should be shrank to70%~80%. Figure 17 shows a paste mask pattern in gray for the thermal pad.

Figure 17: Thermal Pad Paste Mask Pattern

CHRONTEL AN-B009

206-1000-009 Rev. 1.4, 06/30/2020 13

3.0 Reference Design Example

The figures below are the reference schematic of CH7036, which is provided here for design reference only. Table 4

provides the BOM list for the reference schematic.

3.1 Reference Schematic

HDMI_TX0BHDMI_TX0BHDMI_TX0BHDMI_TX0BHDMI_TX0BHDMI_TX0BHDMI_TX0BHDMI_TX0BHDMI_TX0BHDMI_TX0B

VGA_DAC1

VGA_DAC2

HDMI_TX0BHDMI_TX0B

HDMI_TX2BHDMI_TX2B

HDMI_TX1BHDMI_TX1B

VGA_DAC0

R610k

HDMI_TX1

HDMI_TX1BHDMI_TX1BHDMI_TX1BHDMI_TX1BHDMI_TX1BHDMI_TX1BHDMI_TX1BHDMI_TX1B

There are two voltage level of SPDIF input signal:

(1) CMOS(TTL) 3.3-5V

(2) COAX 0.5-1V

According to different input level there are 3 connect way to CH7036

D0B

_T

XD

1_T

X

D0_T

X

D2B

_T

XD

2_T

XD

1B

_T

X

PROM_SD

PROM_SCPROM_SC

PROM_SD

VDD5_VGA_DDC

HDMI_TX2BHDMI_TX2BHDMI_TX2BHDMI_TX2BHDMI_TX2BHDMI_TX2BHDMI_TX2BHDMI_TX2B

C29 1uF

AVDD

LVDS Input (Only support SPWG format)

SPDIFSPDIFSPDIFSPDIFSPDIF

VGA_VSO

U3A

74HCU04/SO

1 2

14

7

C80.1uF

U3B

74HCU04/SO

3 414

7R1975R

J5

S/PDIF IN

1

2

H1

H2

C31

0.1uF

R91M

R18

100R

R17

10K

SPDIFSPDIFSPDIFSPDIFSPDIF

LVDS_DDCSCLVDS_DDCSD

J7

Serial interf ace

123

HDMI_TX2

VD

DT

R35Reserv ed

VGA_HSO

VCC3_3

Power Supply Input

*Reserved for input timing selection.

For detail information, please contact

with Chrontel application group

SPD

HDMI Output

R410R NF

R420R NF

SPC

Y1

27MHz

PWM

LVDS_DDCSD

LVDS_DDCSC

Note: If the driver can support, the CH7036 can be

accessed by SMBUS or LVDS DDC etc..For detail

information, please contact with Chrontel application group

HDMI_HPD

VCC1_8

VCC3_3

VDD5

+12V

R25 120RR23 120R

AVDD_PLL

HDMI_HPD

PROM_SCPROM_SD

C300.1uF

R14

10k

12

R15

10k

12

R165.6k

R1110k

VDD5

VDD5_VGA_DDC

R1210k

VDD5_VGA_DDC

R1375R

U2

CH9904

GP11

GP22

GP33

GND4

SPD5SPC6WE7VCC8

R20

10k

AGND

VCC3_3

R1

5.6K

12

R2

5.6K

12

VDD5

VDDMS

VCC1_8

VCC3_3

+12V

LVDS Output (Only support SPWG format)

AGNDDGND

CLK

_T

XD

3B

_T

XD

3_T

X

CLK

B_T

X

R24 120R

(B) COAX SPDIF can also connect to CH7036 by AC couple

R26 120R

AVDD_DAC

AVDD_PLL

VDDMQ

XO

C1

18pF

12

XI

C2

18pF

12

VDDHVDDH

R22 120R

HDMI_TX2BHDMI_TX1HDMI_TX1B

HDMI_TX0HDMI_TX0BHDMI_TXCHDMI_TXCB

HDMI_TX2

R27 120RR28 120R

AGNDAGND

AVDD_PLLDVDD

DGNDAGND

J6

CON20

123456789

1011121314151617181920

J3

S/PDIF IN

1

2

H1

H2

R710k

HDMI_TXCB

D1B_TXD1_TX

D0B_TXD0_TX

CLK_TX

D3B_TXD3_TX

D2B_TXD2_TX

CLKB_TX

R40

330RSPDIF

D6SM5817

VGA_VSODGND

VDDMSVDDMQ

DGNDDDC_SCDDC_SD

I2S_CKI2S_WSI2S_D/SPDIFVDDMQ

DGNDDGND

DVDDVGA_HSO

AGNDAVDDPWMAUDDACPDBPDB

AGND

HDMI_TXCB

CH7036

U1

AVDD_PLL1

AGND_PLL2

RESERVED3

VDDMS4

GNDMS5

VSSH6

TLC8

TDC0B9

VDDH11

VDDH12

TDC1B13

TDC114

TDC2B15

TDC216

VSSH17

DGND18

DVDD19

AVDD_PLL20

AGND_PLL21

VSSR22

VD

DR

23

RX

0B

25

RX

126

RX

1B

27

RX

228

RX

2B

29

RX

330

RX

3B

31

RX

C32

RX

CB

33

VD

DT

40

LD

C0

34

LD

C0B

35

LD

C1

36

LD

C1B

37

LD

C2

38

LD

C2B

39

LD

C3

41

LD

C3B

42

VSST45

DDC_SD65

DDC_SC64

GNDMQ63

VDDMQ62

VDDMS61

GNDMS60

VSO59

HSO58

DGND56DVDD57

VDDMQ54GNDMQ55

I2S_D/SPDIF53

I2S_WS52

I2S_CK51

AGND50

PDB49

AUDDAC48

PWM47

AVDD46

HP

D88

SP

D87

SP

C86

IRQ

85

RE

SE

RV

ED

84

RS

TB

83

AG

ND

82

PR

OM

_S

C81

PR

OM

_S

D80

AV

DD

79

GP

I 1

78

GP

I 2

77

ISE

T76

AG

ND

_D

AC

75

DA

C0

74

AV

DD

_D

A C

73

AG

ND

_D

AC

71

DA

C2

70

AV

D D

_D

AC

69

TDC010

RX

024

LLC

43

LLC

B44

RESERVED66

XI

67

XO

68

TLCB7

DA

C1

72

Thermal Pad89

To avoid back drive, 2 options:

1. Use a low forward voltage diode.

2. Use a independent 5V power supply.

AVDDD

1_R

XD

0B

_R

XD

0_R

XV

DD

R

CLK

B_R

XC

LK

_R

XD

3B

_R

XD

3_R

XD

2B

_R

XD

2_R

XD

1B

_R

X

VGA Output

HDMI_TXC

VCC3_3

HDMI_TX0B

(A) CMOS SPDIF(3.3V) Input can connect to CH7036 directly

VCC3_3

R8

10k

12

R4 1.2k(1% tolerance)R3

10k

12

J1

CON20

1234567891011121314151617181920

HDMI_TX0

J2

CONN PWR 8x2-H

910111213141516

12345678

DDC_SCDDC_SC

DGND

VGA_DAC0

HDMI_TXC

HDMI_TX0

DDC_SD

HDMI_TX1B

DDC_SD

IRQ

SP

CS

PD

HD

MI_

HP

D

ISE

TG

PI2

GP

I1A

VD

DP

RO

M_S

DP

RO

M_S

CA

GN

DR

ES

ET

B

XO

AV

DD

_D

AC

VG

A_D

AC

2A

GN

DV

GA

_D

AC

1A

VD

D_D

AC

VG

A_D

AC

0A

GN

D

XI

VGA_HSO

VGA_DAC1

HDMI_TX1

D2B_RXD2_RX

D1B_RXD1_RX

D0B_RXD0_RX

R5 0R

CLKB_RXCLK_RX

D3B_RXD3_RX

J4

S/PDIF IN

1

2

H1

H2

RESETBRESETBRESETB

VGA_DAC2

L1

FB

1 2

VCC1_8

DVDD

VDDR

C3

10uFC40.1uF

C100.1uF

C50.1uF

C110.1uF

AGND

C190.1uF

C180.1uF

HDMI_TX2B

L5

FB

1 2

C14

10uF

C20

10uF

L7

FB

1 2

C240.1uF

C250.1uF

C70.1uF

C26

10uF

L9

FB

1 2

C130.1uF

C150.1uF

C160.1uF

VCC3_3

C220.1uF

C210.1uF

C270.1uF

C280.1uF

C9

10uF

L3

FB

1 2

VDDT

C12

10uF

L4

FB

1 2

VCC3_3L2

FB

1 2

VGA_VSO

VDDMS C6

10uF

L6

FB

1 2

C17

10uF

L8

FB

1 2

C23

10uF

VDDH

R1010k

(C) COAX SPDIF Input Convert to CMOS level then connect to CH7036 will have better signal condition

HDMI_TX2

R21 120R

CHRONTEL AN-B009

14 206-1000-009 Rev. 1.4, 06/30/2020

D4

AZ5125-01H

D5

AZ5125-01H

VDD5_HDMI_DDCVDD5_HDMI_DDCVDD5_HDMI_DDC

HDMI_TX2B

HDMI_TX1B

HDMI_TX1

HDMI_TX2

HDMI_TX1

HDMI_TX2U8

RClamp0524P

I/O 11

N.C.9

I/O 22

GND3

I/O 34

I/O 45

N.C.6

N.C.7

GND8

N.C.10

HDMI_TX1B

HDMI_TX2B

HDMI_TX0

HDMI_TXC

HDMI_TX0

HDMI_TX0B

HDMI_TXCB

HDMI_TXC

U9

RClamp0524P

I/O 11

N.C.9

I/O 22

GND3

I/O 34

I/O 45

N.C.6

N.C.7

GND8

N.C.10

HDMI_TX0B

HDMI_TXCB

DDC_SDDDC_SC

C450.1uF

R36

1.8k

12

R37

1.8k

12

R390R

VDD5

R346.8k

CH9903 is used to save the HDCP key.

VGA_DDC_SD

U7

CH9903

GP11

GP22

GP33

GND4

SPD5SPC6WE7VCC8

D7SM5817

VGA_DDC_SC

VGA_HSO1

VDD5 POWER SUPPLY

VGA_VSO1

U4A

74ACT08

A1

B2 Y

3

VC

C1

4

U4B

74ACT08

A4

B5 Y

6

MONGREEN

MONBLUE

L14

47R_100MHz

1 2L15

47R_100MHz

1 2

C38

22pF

C39

22pF

L13150-220R 100MHz 1 2

VGA Output Connector

L12150-220R 100MHz 1 2

C32

10pF

12

C33

22pF

12

C34

10pF

12

To avoid back drive, 2 options:

1. Use a low forward voltage diode.

2. Use a independent 5V power supply.

P1

VGA

11

22

33

44

55

66

77

88

99

1010

1111

1212

1313

1414

1515

16

16

17

17

L10

47R_100MHz

1 2L11

47R_100MHz

1 2

C35

10pF

12

C36

22pF

12

MONHSYNC

MONRED

C37

10pF

12

C40

10pF

12

L16

47R_100MHz

1 2

R31

75R

12

C41

22pF

12

L17

47R_100MHz

1 2

C42

10pF

12

MONVSYNC

R29 33R1 2

R32

75R

12

R33

75R

12

R30 33R1 2

VGA_DAC21

VGA_DAC11

VGA_DAC01

PROM_SC

PROM_SDVGA_DDC_SD

VGA_DDC_SC

U10

RClamp0524P

I/O 11

N.C.9

I/O 22

GND3

I/O 34

I/O 45

N.C.6

N.C.7

GND8

N.C.10

DDC_SC DDC_SD

DDC_SD DDC_SD

DDC_SCDDC_SC

C430.1uF

C4410uF

U6

HDMI Conn

TMDA Data2+1

TMDA Data2 Shield2

TMDA Data2-3

TMDA Data1+4

TMDA Data1 Shield5

TMDA Data1-6

TMDA Data0+7

TMDA Data0 Shield8

TMDA Data0-9

TMDA Clock+10

TMDA TMDA Clock Shield11

TMDA Clock-12

CEC13

Reserved14

SCL15

SDA16

DDC/CEC Ground17

+5V Power18

HPDET19

R3847k

HDMI_HPD

HDMI_HPD

C460.22uF

HDMI_HPD

DDC_SC

VDD5

F1 MINISMDC050CT-ND

VDD5

HDMI_HPD

HDMI_TXCB

HDMI_TXC

HDMI_TX1B

HDMI_TX1

HDMI_TX0B

HDMI_TX0

HDMI_TX2B

HDMI_TX2

HDMI Output Connector

D1

AZ5125-01H

DDC_SD

D2

AZ5125-01H

D3

AZ5125-01H

3.2 Reference Board Preliminary BOM

Table 4: CH7036 Reference Design BOM List

Item Quantity Reference Part

1 5 D1, D2, D3, D4, D5 AZ5125-01H

2 2 C1, C2 18 pF

3 10 C3, C6, C9, C12, C14, C17, C20, 10 µF

C23, C26, C44

4 21 C4, C5, C7, C8, C10, C11, C13, C15 0.1 µF

C16, C18, C19, C21, C22, C24, C25

C27, C28, C30, C31, C43, C45

5 1 C29 1 µF

6 6 C32, C34, C35, C37, C40, C42 10 pF

7 5 C33, C36, C38, C39, C41 22 pF

8 1 C46 0.22 µF

9 2 D6, D7 SM5817

10 1 F1 MINISMDC050CT-ND

11 2 J1, J6 CON20

12 1 J2 CONN PWR 8x2-H

13 3 J3, J4, J5 S/PDIF IN

14 9 L1, L2, L3, L4, L5, L6, L7, L8, L9 FB

15 6 L10, L11, L14, L15, L16, L17 47R_100MHz

16 2 L12, L13 150-220R 100MHz

CHRONTEL AN-B009

206-1000-009 Rev. 1.4, 06/30/2020 15

17 1 P1 VGA

18 3 R1, R2, R16 5.6 kΩ

19 11 R3, R6, R7, R8, R10, R11, 10 kΩ

R12, R14, R15, R17, R20,

20 1 R4 1.2 kΩ (1% tolerance)

21 2 R5, R39 0 Ω

22 5 R13, R19, R31, R32, R33 75 Ω

23 1 R9 1 MΩ

24 1 R18 100 Ω

25 8 R21, R22, R23, R24, R25, R26, R27, R28 120 Ω

26 2 R29, R30 33 Ω

27 1 R34 6.8 kΩ

28 2 R36, R37 1.8 kΩ

29 1 R38 47 kΩ

30 1 R40 330 Ω

31 1 R35 reserved

32 1 U1 CH7036A

33 1 U2 CH9904

34 1 U3 74HCU04/SO

35 1 U4 74ACT08

36 1 U6 HDMI Connector

37 1 U7 CH9903

38 2 U8, U9, U10 RClamp0524P

39 1 Y1 27MHz

CHRONTEL AN-B009

16 206-1000-009 Rev. 1.4, 06/30/2020

Disclaimer

This document provides technical information for the user. Chrontel reserves the right to make changes at any time

without notice to improve and supply the best possible product and is not responsible and does not assume any

liability for misapplication or use outside the limits specified in this document. CHRONTEL warrants each part to be

free from defects in material and workmanship for a period of one (1) year from date of shipment. Chrontel assumes

no liability for errors contained within this document. The customer should make sure that they have the most recent

data sheet version. Customers should take appropriate action to ensure their use of the products does not infringe

upon any patents. Chrontel, Inc. respects valid patent rights of third parties and does not infringe upon or assist others

to infringe upon such rights.

Chrontel PRODUCTS ARE NOT AUTHORIZED FOR AND SHOULD NOT BE USED WITHIN LIFE SUPPORT

SYSTEMS OR NUCLEAR FACILITY APPLICATIONS WITHOUT THE SPECIFIC WRITTEN CONSENT OF

Chrontel. Life support systems are those intended to support or sustain life and whose failure to perform when used

as directed can reasonably expect to result in personal injury or death.

Chrontel

www.chrontel.com

E-mail: sales@chrontel.com

2020 Chrontel - All Rights Reserved.