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The World Leader in High Performance Signal Processing Solutions
Fundamentals of Laying Out PC Boards
Jack ArdizzoniAnalog DevicesFebruary 2012
2
Todays Agenda
PCB Layout OverviewSchematicCritical Component Location and Signal RoutingPower Supply BypassingParasitics, Vias and PlacementGround PlaneLayout ReviewSummary
3
Overview
What is high speed? For Op Amps we consider anything >50MHz to be high speed.
PCB layout is one of the final steps in the design process and often not given the attention it deserves. High Speed circuit performance is heavily dependant on board layout.
Today we will address Practical layout guidelines that:
Improve the layout processHelp ensure expected circuit performanceReduce design timeLower design cost
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Schematic
5
Schematic
A good layout starts with a good Schematic!The schematic is the blueprint for the PCBSchematic flow and content are essentialInclude as much information as you can
Notes that include tolerance and case sizeCritical component placementTuning or alignment proceduresBoard stack upControlled impedance linesThermal issuesComponent de-rating and reliability information
6
Schematic40 MHz
AD590
ADP667
Linear Regulator
Temperature Sensor+12V +5
V
VOUT
R3562
C10.1uF
U1
ADA4860-1
-
+
Linear Regulator
-12V -5V
+
++
+
+5V
-5V
R6
301
R4210
S1C4
2.2uF
C50.01uF
R5562
C2SAT
C3SAT
C60.01uF
C72.2uF
U2
U3
U4
U5
D11N4148
D21N4148
VIN
VOUT
C810uFCase size 1210
C90.01uF
C110.1uF
C1210uFCase size1210
C1310ufCase size1210 C14
0.1uFC15
0.1uF
C1610uF
Case size1210
+5V
40 MHz OSC Out
2.0 All Resistors in ohms unless noted otherwise.3.0 All capacitors in pF unless noted otherwise.
Must be right at op amp supply
pins
Must be right at op amp supply
pins
Put C4 and C7 on back of board right under the
power supply pin.
-5V
+5V
+5V
R250
R750
6.0 U1 SOIC-14, U2 SOT-23-6, U3, SOIC-8, U4 SOIC-8
R81K
Run 40MHz traces on bottom of the board ensure signal trace is the same length
Place this cap right at pin 14 to digital ground
40 MHz OSC Out
+5V
R11K
FREQUENCY ADJUST1.0 C2=C3, use these 2 capacitors to adjust the -3dB BW
1K
Derating Table
R1
R2
R3
C1
C2
C3
U1
U2
VALUE
1
2
3
4
5
6
7
8
62mW 10mW
ITEM REF DES ACTUALRATING
0.062"
Signal 1 Analog Ground 1
Digital GroundPower plane
Analog Ground 2 Signal 2
BOARD STACK UP1.0 All resistors and capacitors are 0603 case size unless noted otherwise.
4.0 Run analog traces on Signal 1 layer, run digital traces on Signal 2 layer
NOTES:
5.0 Remove ground plane on all layers under the mounting pins of U2
+
+
See critical component placement drawing for location
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Critical Component Placement and Signal Routing
8
Critical Component Placement and Signal Routing
Just as in real estate location is everything!Input/output and power connections on a board
are typically definedCritical Component location and Signal routing
require deliberate thought and planning
Critical Component Placement and Signal Routing
Ground or power
plane
Critical Component Placement and Signal Routing
RF
PowerConditioning
Connector
Analog
ADCDriver
ADCDigital
Temp Sensor
Critical Component Placement and Signal Routing
RF
Connector
Analog
ADCDriver
ADCDigital
Power
Signal
Temp Sensor
Poor Placement
PowerConditioning
Critical Component Placement and Signal Routing
RF
Connector
Analog
ADCDriver
ADC
Digital
Power
Temp Sensor
Improved Placement
PowerConditioning
Signal
DigitalCircuitry
AnalogCircuitry
Re
sist
or
ClockCircuitry
Sensitive Analog Circuitry Disrupted by Digital Supply Noise
ANALOGCIRCUITS
DIGITALCIRCUITSVD VA
+ +
ID
IA
IDIA + ID
VIN
GNDREF
INCORRECT
Critical Component Placement and Signal Routing
Wrong Way
Input Connector
DigitalCircuitry
AnalogCircuitry
Re
sist
or
ClockCircuitry
Sensitive Analog Circuitry Disrupted by Digital Supply Noise
ANALOGCIRCUITS
DIGITALCIRCUITSVD VA
+ +
ID
IA
IDIA + ID
VIN
GNDREF
INCORRECT
Critical Component Placement and Signal Routing
Wrong Way
DigitalCircuitry
AnalogCircuitry
Re
sist
or
ClockCircuitry
Sensitive Analog Circuitry Disrupted by Digital Supply Noise
ANALOGCIRCUITS
DIGITALCIRCUITSVD VA
+ +
ID
IA
IDIA + ID
VIN
GNDREF
INCORRECT
Critical Component Placement and Signal Routing
Wrong Way
DigitalCircuitry
AnalogCircuitry
Re
sist
or
ClockCircuitry
Sensitive Analog Circuitry Disrupted by Digital Supply Noise
ANALOGCIRCUITS
DIGITALCIRCUITSVD VA
+ +
ID
IA
IDIA + ID
VIN
GNDREF
INCORRECT
Critical Component Placement and Signal Routing
Wrong Way
Voltage DropVoltage Drop
DigitalCircuitry
AnalogCircuitry
Re
sist
or
ClockCircuitry
Sensitive Analog Circuitry Safe from Digital Supply Noise
ANALOGCIRCUITS
DIGITALCIRCUITSVD VA
+ +
VIN
ID
IA
ID
IAGNDREF
CORRECT
Critical Component Placement and Signal Routing
Right Way
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Signal Routing
Signal RoutingOp Amp Packaging and Pinout
Packaging plays a large role in high-speed applicationsSmaller packages
Better at high speeds/high frequencyCompact layoutLess parasitics
Analog Devices Low Distortion (dedicated feedback) PinoutCompact layoutStreamline signal flowLower distortion
Op Amp SOIC Packaging
Traditional SOIC-8 layoutFeedback routed around or underneath amplifier
Op Amp SOIC Packaging
Traditional SOIC-8 layoutFeedback routed around or underneath amplifier
Op Amp SOIC Packaging
Traditional SOIC-8 layoutFeedback routed around or underneath amplifier
Analog Devices Low DistortionDedicated Feedback Pinout
Pinout enables compact layout
Lower distortion Improved thermal
performanceLFCSP
AD8099, AD8045, AD8000, ADA4899, ADA4857, ADA4817
Also used on Differential Amplifiers
Disable FB1
2
3
4
8
7
6
5
–IN
–VS
+IN
+VS
VOUT
NC
+
-
Original Pin-Out
NC
Low distortion (dedicated feedback) pinout enables compact and streamline layout
26
AD8099 Harmonic Distortion Vs. Frequency
CSP and SOIC Packages
HA
RM
ON
IC D
ISTO
RTI
ON
(dB
c)
0.1–120
–100
–110
–80
–90
–60
–70
–50
1 10 50
0451
1-0-
085
SOLID LINES – SECOND HARMONICSDOTTED LINES – THIRD HARMONICS
G = +5VOUT = 2V p-pVS = ±5VRL = 100
FREQUENCY (MHz)
SOIC
CSP
Improvement10dB at 1MHz 14dB at 10MHz
00:09:52
27
Signal Routing
Many different signals exist on boardsAnalog, digital, low voltage, high voltage, and RF to name a few
Ground and power planes can help provide shielding Microstrip, stripline
IsolationPhysical separation
Minimize long parallel runsMinimize long trace on adjacent layersRun traces orthogonal on adjacent layers
Guard rings Differential signals
28
Crosstalk and Coupling Capacitive Crosstalk or Coupling
This results from traces running on top of each other, which forms a parasitic capacitor
Solutions run traces orthogonal, to minimize trace coupling and lower area profile
Inductive CrosstalkInductive crosstalk exists due to the magnetic field interaction
between long traces parallel tracesThere are two types of inductive crosstalk; forward and backwardBackward is the noise observed nearest the driver on the victim traceForward is the noise observed farthest from the driver on the driven
line Minimize crosstalk by
Increasing trace separation (improving isolation)Using guard tracesUsing differential signals
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Power Supply Bypassing
Power Supply Bypassing
Bypassing is essential to high speed circuit performance
Power Supply Bypassing
Bypassing is essential to high speed circuit performance
Capacitors right at power supply pins
Power Supply Bypassing
Bypassing is essential to high speed circuit performance
Capacitors right at power supply pinsCapacitors provide low
impedance AC return Provide local charge storage
for fast rising/falling edges
Power Supply Bypassing
Bypassing is essential to high speed circuit performance
Capacitors right at power supply pinsCapacitors provide low
impedance AC return Provide local charge storage
for fast rising/falling edgesKeep trace lengths short
EQUIVALENT DECOUPLED POWER LINE CIRCUIT RESONATES AT:
f =1
2p LCÖ
IC+VS
C1
L1
0.1µF
1nH
f = 16MHz
Power Supply Bypassing
Bypassing is essential to high speed circuit performance
Capacitors right at power supply pinsCapacitors provide low
impedance AC return Provide local charge storage
for fast rising/falling edgesKeep trace lengths short
Power Supply Bypassing
Bypassing is essential to high speed circuit performance
Capacitors right at power supply pinsCapacitors provide low
impedance AC return Provide local charge storage
for fast rising/falling edgesKeep trace lengths shortClose to load return
Helps minimize transient currents in the ground plane
Optimized Load and Bypass Capacitor Placement and Ground Return
Tantalum
Tantalum
C
C
RL
AD
80
XX
RT
RG RF
00
37
Power Supply BypassingBoard Capacitance
4 layer stack up Component/signal side
Ground plane
Power plane
Circuit side
d
K = relative dielectric constantA = area in cm2
d = spacing between plates in cm
A
kA11.3d
C=
Power Supply BypassingPower Plane Capacitance
*Courtesy of Lee Ritchey
*
Power Supply BypassingCapacitor ModelESR (Equivalent Series
Resistance) Rs
CapacitanceXC = 1/2πfC
ESL (Equivalent Series Inductance)XL=2πfL
Effective Impedance
At Series resonance XL=XCZ = R
2)(2 XCXLRsZ
*Courtesy of Lee Ritchey
*
Capacitor Choices
0603 0612
*Courtesy of Lee Ritchey
*
Power Supply Bypassing
Bypassing is essential to high speed circuit performance
Capacitors right at power supply pinsCapacitors provide low
impedance AC return Provide local charge storage
for fast rising/falling edgesKeep trace lengths shortClose to load return
Helps minimize transient currents in the ground plane
ValuesIndividual circuit performance
Power Supply Bypassing
Bypassing is essential to high speed circuit performance
Capacitors right at power supply pinsCapacitors provide low
impedance AC return Provide local charge storage for
fast rising/falling edges Keep trace lengths short Close to load return
Helps minimize transient currents in the ground plane
ValuesIndividual circuit performanceMaintains low AC impedanceMultiple resonances
Multiple Parallel Capacitors
1 x 330µF T520, 1 x 1.0µF 0603, 2 x 0.1µF 0603, and 6 x 0.01µF 0603
*Courtesy of Lee Ritchey
*
2 x (1 x 330µF T520, 1 x 1.0µF 0603, 2 x 0.1µF 0603, and 6 x 0.01µF 0603)
1µF330µF
0.1µF
0.01µF
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Parasitics
46
Parasitics
PCB parasitcs take the form of hidden
capacitors, inductors and resistors in the PCB
Parasitics degrade and distort performance
47
Trace/Pad Capacitance
d
d
kAC
3.11
A
K = relative dielectric constantA = area in cm2
d = spacing between plates in cm
48
Trace/Pad Capacitance
d
d
kAC
3.11
A
K = relative dielectric constantA = area in cm2
d = spacing between plates in cm
Example: Pad of SOIC
L = 0.2cm W = 0.063cm
K= 4.7
A = 0.126cm2
d = 0.073cm
C = 0.072pF
49
Trace/Pad Capacitance
d
d
kAC
3.11
A
K = relative dielectric constantA = area in cm2
d = spacing between plates in cm
Reduce Capacitance1) Increase board thickness
2) Reduce trace/pad area 3) Remove ground plane
Example: Pad of SOIC
L = 0.2cm W = 0.063cm
K= 4.7
A = 0.126cm2
d = 0.073cm
C = 0.072pF
50
Approximate Trace Inductance
All dimensions are in mm
51
Approximate Trace Inductance
Example
L= 25.4mm
W = .25mm
H = .035mm (1oz copper)
Strip Inductance = 28.8nH
At 10MHz ZL = 1.86 a 3.6% error in a 50 system
All dimensions are in mm
52
Approximate Trace Inductance
Example
L= 2.54cm =25.4mm
W = .25mm
H = .035mm (1oz copper)
Strip Inductance = 28.8nH
At 10MHz ZL = 1.86 a 3.6% error in a 50 system
All dimensions are in mm
Minimize Inductance
1) Use Ground plane 2) Keep length short (halving
the length reduces inductance by 44%)
3) Doubling width only reduces inductance by
11%
53
Via Parasitics
14
ln2d
hhL
L = inductance of the via, nHH = length of via, cmD = diameter of via, cm
H= 0.157 cm thick board,D= 0.041 cm
Via Inductance Via Capacitance
1
041.0
)157.0(4ln)157.0(2L
L = 1.2nh
12
155.0
DD
TDC r
D2 = diameter of clearance hole in the ground plane, cm
D1 = diameter of pad surrounding via, cmT = thickness of printed circuit board, cm = relative electric permeability of circuit board materialC = parasitic via capacitance, pF
T = 0.157cm,
D1=0.071cm
D2 = 0.127
C = 0.51pf
r
nH
54
Via Placement*
0603 and 0402
*Courtesy of Lee Ritchey
55
Capacitor Parasitic Model
C = Capacitor RP = insulation resistance
RS = equivalent series resistance (ESR) L = series inductance of the leads and plates
RDA = dielectric absorption CDA = dielectric absorption
L
r
RP
C
RDA CDA
RS
56
Resistor Parasitic Model
R = Resistor CP = Parallel capacitance
L= equivalent series inductance (ESL)
CP
R
L
57
Low Frequency Op Amp Schematic
58
High Speed Op AmpSchematic
59
High Frequency Op AmpSchematic
Stray Capacitance
Stray Capacitance Simulation Schematic
Frequency Response with 1.5pF Stray Capacitance
1.5dB peaking
Stray Inductance
Stray Inductance
Parasitic Inductance Simulation Schematic
24.5mm x .25mm” =29nH
Pulse Response With and Without Ground Plane
0.6dB overshoot
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Ground and Power Planes
66
Ground and Power Planes Provide
A common reference pointShieldingLowers noiseReduces parasiticsHeat sinkPower distributionHigh value capacitance
67
Ground Plane Recommendations
There is no single grounding method which is guaranteed to work 100% of the time!
At least one layer on each PC board MUST be dedicated to ground plane!
Provide as much ground plane as possible especially under traces that operate at high frequency
Use thickest metal as feasible (reduces resistance and provides improved thermal transfer)
Use multiple vias to connect same ground planes togetherDo initial layout with dedicated plane for analog and digital
ground planes, split only if requiredFollow recommendations on mixed signal device data sheet.Keep bypass capacitors and load returns close to reduce
distortionProvide jumper options for joining analog and digital ground
planes together
68
Checking the layout
If possible have another set of eyes (or more) take a look at your layout.
69
Checking the layout
If possible have another set of eyes (or more) take a look at your layout.
Colored pencils
70
Checking the layout
If possible have another set of eyes (or more) take a look at your layout.
Colored pencilsSit with the designer when
board corrections are made
The World Leader in High Performance Signal Processing Solutions
Summary
72
Summary
High speed PCB design requires deliberate thought and attention to detail!
Load the schematic with as much information as possible Where you put components on the board is just as important as to
where you put entire circuits Take the lead when laying out your board, don’t leave anything to
chance Use multiple capacitors for power supply bypassing Parasitics must be considered and dealt with Ground and Power planes play a key role in reducing noise and
parasitics New packaging and pinouts allow for improved performance and
more compact layouts There are many options for signal distribution, make sure you
choose the right one for your application Check the layout very carefully
73
References Special Thanks and acknowledgement to Lee Ritchey for use of
plots and material for this presentation.
Lee Ritchey “Right the first time” ISBN 0-9741936-0-7 http://www.speedingedge.com/
Ardizzoni, John “A Practical Guide to High-Speed Printed-Circuit-Board Layout ”
Ardizzoni, John, “Keep High-Speed Circuit-Board Layout on Track,” EE Times, May 23, 2005.
Brokaw, Paul, “An IC Amplifier User’s Guide to Decoupling, Grounding, and Making Things Go Right for a Change,” Analog Devices Application Note AN-202.
Brokaw, Paul and Jeff Barrow, “Grounding for Low- and High-Frequency Circuits,” Analog Devices Application Note AN-345.
Buxton, Joe, “Careful Design Tames High-Speed Op Amps,” Analog Devices Application Note AN-257.
74
References DiSanto, Greg, “Proper PC-Board Layout Improves Dynamic Range
,” EDN, November 11, 2004. Grant, Doug and Scott Wurcer, “Avoiding Passive-Component
Pitfalls,” Analog Devices Application Note AN-348 Johnson, Howard W., and Martin Graham,
High-Speed Digital Design, a Handbook of Black Magic, Prentice Hall, 1993.
Jung, Walt, ed., Op Amp Applications Handbook, Elsevier-Newnes, 2005 available on Amazon.com
Kester, Walt, The Data Conversion Handbook, Elsevier-Newnes, 2005 available on Amazon.com
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