PCI Express* 4.0 Connector High Speed Electrical · connector and a Through-Reflect-Load (TRL)...

Document Number: 337145-002US

PCI Express* 4.0 Connector High Speed Electrical Test Procedure

March 2019

Revision 002

2 Document Number: 337145, Revision: 002

Intel technologies’ features and benefits depend on system configuration and may require enabled hardware, software, or service activation. Learn more at intel.com, or from the OEM or retailer. No computer system can be absolutely secure. Intel does not assume any liability for lost or stolen data or systems or any damages resulting from such losses. You may not use or facilitate the use of this document in connection with any infringement or other legal analysis concerning Intel products described herein. You agree to grant Intel a non-exclusive, royalty-free license to any patent claim thereafter drafted which includes subject matter disclosed herein. No license (express or implied, by estoppel or otherwise) to any intellectual property rights is granted by this document. The products described may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. This document contains information on products, services and/or processes in development. All information provided here is subject to change without notice. Contact your Intel representative to obtain the latest Intel product specifications and roadmaps. Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade. Warning: Altering PC clock or memory frequency and/or voltage may (i) reduce system stability and use life of the system, memory and processor; (ii) cause the processor and other system components to fail; (iii) cause reductions in system performance; (iv) cause additional heat or other damage; and (v) affect system data integrity. Intel assumes no responsibility that the memory, included if used with altered clock frequencies and/or voltages, will be fit for any particular purpose. Check with memory manufacturer for warranty and additional details. Tests document performance of components on a particular test, in specific systems. Differences in hardware, software, or configuration will affect actual performance. Consult other sources of information to evaluate performance as you consider your purchase. For more complete information about performance and benchmark results, visit http://www.intel.com/performance. Cost reduction scenarios described are intended as examples of how a given Intel- based product, in the specified circumstances and configurations, may affect future costs and provide cost savings. Circumstances will vary. Intel does not guarantee any costs or cost reduction. Results have been estimated or simulated using internal Intel analysis or architecture simulation or modeling, and provided to you for informational purposes. Any differences in your system hardware, software or configuration may affect your actual performance. Intel does not control or audit third-party benchmark data or the web sites referenced in this document. You should visit the referenced web site and confirm whether referenced data are accurate. Copies of documents which have an order number and are referenced in this document may be obtained by calling 1-800-548-4725 or by visiting www.intel.com/design/literature.htm. Intel, the Intel logo, and Xeon are trademarks of Intel Corporation in the U.S. and/or other countries. *Other names and brands may be claimed as the property of others.

Copyright © 2019, Intel Corporation. All Rights Reserved.

http://www.intel.com/design/literature.htm

Document Number: 337145, Revision: 002 3

Contents 1 Introduction ............................................................................. 7

1.1 Reference Documents .................................................................. 7 1.2 Definitions ................................................................................. 8 1.3 Tool List ..................................................................................... 8

2 Test Fixture Description ........................................................... 9 2.1 Test Board Design ....................................................................... 9 2.2 TRL Calibration Standards .......................................................... 10 2.3 Reference Plane Positions ........................................................... 11 2.4 Reference Plane Positions ........................................................... 12 2.5 Device Under Test (DUT) ........................................................... 13 2.6 Retention During Test ................................................................ 14

3 Equipment Setting, Calibration and Verification ..................... 16 3.1 Measurement Test Flow ............................................................. 16 3.2 Vector Network Analyzer Settings ............................................... 17 3.3 Allen Test................................................................................. 17 3.4 Reference Plane Definition.......................................................... 17 3.5 Flight Time ............................................................................... 18 3.6 TRL Four Port Calibration ........................................................... 19 3.7 Calibration Verification ............................................................... 20

3.7.1 Secondary Line Phase Margin ................................. 20 3.7.2 TRL Calibration Stability ......................................... 20 3.7.3 Dynamic Range .................................................... 20

4 Multi-Port Measurement ........................................................ 21 4.1 VNA Port Naming Convention ..................................................... 21 4.2 Connector Pair Descriptions ........................................................ 21 4.3 Differential Insertion Loss (DDIL) ................................................ 23 4.4 Differential Return Loss (DDRL) .................................................. 23 4.5 Crosstalk Victim-Aggressor Patterns ............................................ 23 4.6 Differential Near-End Crosstalk (DDNEXT) .................................... 25

5 Low Level Contact Resistance ................................................ 26

6 Contact Current Rating .......................................................... 27

A Connector Evaluation Board Bill-of-Materials ......................... 28

B TRL Calibration ...................................................................... 30 B.1 Initial TRL Calibration Steps 1 - 22 .............................................. 30 B.2 Final TRL Calibration Steps 23 to 46 and TRL Calibration Check ...... 31

C VNA Measurement Template .................................................. 33

D TDR Measurement Template (Not Required) .......................... 34

E Add-In Card and Base Board Support Bracket Drawing .......... 35


Figures Figure 2-1. PCIe Connector Evaluation Board Set ............................ 9 Figure 2-2. TRL Calibration Standards ......................................... 10 Figure 2-3. Base Board Design for SMT Connector Testing ............. 11 Figure 2-4. Base Board Design for Through-Hole/Press-Fit Connector

Testing .......................................................................... 12 Figure 2-5. AIC Design for SMT Connector Testing ........................ 12 Figure 2-6. Test Board Stack-Up (Baseboard and Add-In Card) ....... 13 Figure 2-7. SMT Connector Testing Setup for VNA Measurement ..... 13 Figure 2-8. Through-Hole/Press-Fit Connector Testing Setup for VNA

Measurement ................................................................. 14 Figure 2-9. PCIe Connector Evaluation Board and Support Bracket .. 15 Figure 3-1. PCI Express CEM Connector Measurement Flow ............ 16 Figure 3-2. TDT Instrument Temperature Compensation ................ 18 Figure 3-3. TDT Instrument Scaling and Acquisition Mode .............. 18 Figure 3-4. TDT Instrument Channel Setting ................................ 19 Figure 4-1. Port Naming Convention ............................................ 21 Figure 4-2. Port configuration for Connector Measurement ............. 22 Figure 4-3. Test Configuration for DDIL and DDRL11/DDRL22 ........ 22 Figure 4-4. Test Configuration for DDNEXT from a Victim on Base

Board Side ..................................................................... 24 Figure 4-5. Test Configuration for DDNEXT from a Victim on AIC .... 24 Figure 5-1. Daisy Chain Pattern for Connector LLCR Measurement . 26 Figure 6-1. Daisy Chain Pattern for Contact Current Rating ........... 27 Figure E-1. Support Bracket Assembly Drawing for PCIe Connector

Evaluation ...................................................................... 35 Figure E-2. Support Bracket Side Plate Drawing for PCIe Connector

Evaluation (1 of 2) .......................................................... 36 Figure E-3. Support Bracket Side Plate Drawing for PCIe Connector

Evaluation (2 of 2) .......................................................... 37 Figure E-4. Support Bracket Mid Beam Drawing for PCIe Connector

Evaluation (1 of 2) .......................................................... 38 Figure E-5. Support Bracket Mid Beam Drawing for PCIe Connector

Evaluation (2 of 2) .......................................................... 39

Tables Table 1-1.Terminology ................................................................. 8 Table 3-1. VNA Settings for Measuring PCIe Connectors................. 17 Table A-1. Bill of Materials for PCIe 4.0 Connector Evaluation Base

Board and Add-In Card for SMT Style Connector ................. 28 Table A-2. Bill of Materials for PCIe 4.0 Connector Evaluation Base

Board and Add-In Card for THM Style Connector ................. 28 Table B-1.TRL Calibration Kit Crossover Frequencies ..................... 30 Table B-2. E-Cal and Fixture Bandwidth Checks ............................ 30 Table B-3. Initial TRL Calibration Steps 1- 22 ............................... 30


Table B-4. Final TRL Calibration Steps 23 – 46, TRL Cal Check ........ 31 Table C-1. Data Collection Template for 4-Port VNA Measurements . 33 Table D-1. Data Collection Template for TDR Measurements ........... 34


Revision History Revision Revision History Date

001 • Initial release of the document. February 2018

002

• Updated measurement flow chart. • Updated SI formulas. • Added TRL calibration steps. • Updated test plan.

March 2019


1 Introduction This test procedure outlines the steps required to perform high speed signal integrity measurements on a PCI Express* connector at 16 GT/s. The high speed signal integrity requirements are described in the PCI Express* Card Electromechanical (CEM) Specification.

1.1 Reference Documents This document follows the procedures outlined in these documents:

• EIA 364-101 – Attenuation Test Procedure for Electrical Connectors, Sockets, Cable Assemblies or Interconnection Systems

• EIA 364-90 - Cross Ratio Test procedure for Electrical Connectors, Sockets, Cable Assemblies or Interconnection systems

• EIA 364-108 – Impedance, Reflection Coefficient, Return Loss and VSWR Measured in the Time and Frequency Domain Test Procedure for Electrical Connectors, Sockets, Cable Assemblies or Interconnection Systems

• EIA 364-23B – Low Level Contact Resistance Test Procedures for Electrical Connectors and Sockets

• EIA 364-70B – Temperature Rise Versus Current Test Procedure for Electrical Connectors and Sockets

• IEEE* P802.3ap*/Draft 3.3 – Draft Amendment of IEEE Standard for Information Technology

• Agilent* application note, “Stripline TRL Calibration Fixtures for 10-Gigabit Interconnect Analysis”, ©Agilent Technologies, Inc, 5989-4897EN, April 5, 2006

• K. Vaz, M. Caggiano “Measurement Technique for the Extraction of Differential S-Parameters from Single-Ended S-Parameters,” IEEE 27th Spring Seminar on Electronics Technology, 2004

• D. Bockelman, W. Eisenstadt “Combined Differential and Common-Mode Scattering Parameters: Theory and Simulation,” IEEE Transactions on Microwave Theory and Techniques, VOL 43, NO. 7, July 1995.

• PCI Express Card Electromechanical Specification, Revision 4


1.2 Definitions Table 1-1.Terminology

Term Description

Add-in-card A card that is plugged into a connector and mounted in a chassis slot

AIC Add-in card

Baseboard Mother board, system board, test board with TRL calibration standards

CEM Card Electromechanical

dB Decibel, given in dB Volt; i.e., 20log(V2/V1)

DUT Device Under Test

E-Cal Electronic Calibration

ESD Electrostatic Discharge

Fmax Maximum operating frequency

GT/s Giga-transfers per second

LLCR Low Level Contact Resistance

SMA Sub Miniature version A

VLC Vertical Launch Connector

VNA Vector Network Analyzer

VSWR Voltage Standing Wave Ratio

TEM Transverse Electromagnetic

TDR Time Domain Reflectometry

TDT Time Domain Through

TRL Through Reflect Line

1.3 Tool List The following list of equipment is adequate for measurement accuracy. The equipment has been verified to be compatible with this test procedure and the test fixture. Vector Network Analyzer: Keysight* N5230A

or Anritsu* MS4640A Series or Rhode* and Schwartz* ZVB or equivalent

Coaxial Terminators: 50 Ω, VSWR ≤ 1.2 at 20 GHz

50 Ω Coaxial cables: Gore* CAB062707-0250 Ω or Rosenberger* or equivalent

The coaxial terminations have a direct effect on the results of the measurements. The performance of the coaxial termination across the measurement frequency range must be verified before proceeding.


2 Test Fixture Description This test procedure is developed for use with the 16 GT/s PCI Express Connector Evaluation Board Set, shown in the following figures. The test fixture is designed and built to specific criteria to ensure good measurement accuracy and compatability with the interconnect specification. Test board requirementd can be found in Chapter 6 in the PCI Express Card Electromechanical (CEM) Specification, Rev. 4.

2.1 Test Board Design A test board set consists of two boards as shown in Figure 2-1, a baseboard and a mating add-in card. The base board includes a PCIe* connector and a Through-Reflect-Load (TRL) calibration kit.

Note: The mating add-in card should be fabricated from the same PCB panel as the baseboard.

Two types of test reference boards exist: one for SMT (surface mount) connector and the other for Through-Hole Mount (THM) or Press-Fit (PF) mount connector.

Reference designs including baseboard stack-up, DUT description, and add-in card stack-up information may be on the following website under “Tools” http://www.intel.com/content/www/us/en/io/pci-express/pci-express-architecture-devnet-resources.html.

Figure 2-1. PCIe Connector Evaluation Board Set

http://www.intel.com/content/www/us/en/io/pci-express/pci-express-architecture-devnet-resources.html

http://www.intel.com/content/www/us/en/io/pci-express/pci-express-architecture-devnet-resources.html


2.2 TRL Calibration Standards TRL calibration standards, one Primary Through, one Short (Reflect), three Lines (called Secondary 1, 2 and 3) and one Load are used as depicted in Figure 2-2. The frequency range for each secondary is written on the silkscreen.

Test board trace impedance is tightly controlled within 5 % of the nominal reference impedance of 50 Ω. 2.92mm vertical launch connectors and MEGTRON* 6 material are used.

Figure 2-2. TRL Calibration Standards


2.3 Reference Plane Positions Figure 2-3 shows the location of the reference plane on the base board designed for SMT connector testing. Figure 2-4 shows the location of the reference plane on the base board designed for THM/PF connector testing. The AIC design is the same for SMT and THM/PF connector test boards. Figure 2-5 shows the location of the reference plane on the add-in card used for SMT and THM/PF connector testing. Perform connector tests using add-in cards and baseboard boards from the same panel. AIC and baseboards should be marked by the fabricator to ensure AIC and baseboard traceability to the panel level. Use the AIC which is from the same panel as the base board, and maintain AIC and base board pairing during connector measurement.

Figure 2-3. Base Board Design for SMT Connector Testing


Figure 2-4. Base Board Design for Through-Hole/Press-Fit Connector Testing

Figure 2-5. AIC Design for SMT Connector Testing

2.4 Reference Plane Positions The VNA setup and test plan used in this procedure is designed to produce S-parameter measurements referenced to 50 ohm single ended impedance. Measurements must be renormalized to 42.5 ohms PCI-SIG* CEM reference impedance. All test traces are held to a


characteristic impedance of 50 ohms +/- 5%. The test board is a four layer stack-up. MEGTRON 6 is used for the laminate material on all layers and the stack-up details are shown in Figure 2-6.

Figure 2-6. Test Board Stack-Up (Baseboard and Add-In Card)

2.5 Device Under Test (DUT) Figure 2-7 and Figure 2-8 illustrate the test setup for the VNA measurement, location of the measurement reference planes, and DUT description.

Figure 2-7. SMT Connector Testing Setup for VNA Measurement


Figure 2-8. Through-Hole/Press-Fit Connector Testing Setup for VNA Measurement

2.6 Retention During Test A metal bracket must be used to properly hold the baseboard and AIC to ensure measurement accuracy and stability. Figure 2-9 shows the base board and add-in card mounted to the metal bracket. A mechanical drawing of the bracket is included in Appendix D.


Figure 2-9. PCIe Connector Evaluation Board and Support Bracket


3 Equipment Setting, Calibration and Verification

3.1 Measurement Test Flow The test flow in the Figure 3-1 describes the key steps and responses needed to complete accurate and repeatable time and frequency domain measurements. Key steps such as pre-TRL calibration checks and TRL calibration should be performed daily. Calibration quality checks should be performed before and after completing the measurement test plan to ensure stability of the test environment for the duration of the measurement activity.

Figure 3-1. PCI Express CEM Connector Measurement Flow

When attaching the VNA cables to the vertical launch connectors make sure to rotate the external bolt of the cable with respect to the VLC and avoid the damage of the central pin. Check the torque of the screws holding the VLC to the board and ensure they meet supplier recommendations.


3.2 Vector Network Analyzer Settings Measurement must be performed using a vector network analyzer (VNA) with a bandwidth of at least 20 GHz. VNA settings affect measurement and calibration performance. Use the baseline settings in Table 3-1 in combination with the calibration procedure to improve connector measurement accuracy and repeatability.

Table 3-1. VNA Settings for Measuring PCIe Connectors

VNA Setting Value

Start Frequency:Frequency Step: Stop Frequency 10 MHz : 10 MHz : 20 GHz

Number of Points 2000

Number of averages 3

IF Bandwidth ≤1 kHz

3.3 Allen Test The Allen Test is a useful test procedure to determine the maximum operating frequency (Fmax) of the test setup including the test fixture and VNA can support. Over the frequency range up to Fmax, the RF components and the VNA should not resonate. The Allen Test is performed using the primary through. There should be at least 5 db margin between Insertion Loss (IL) and Return Loss (RL) at the highest measurement frequency. The following step are recommended for the Allen Test.

1. Perform the SOLT calibration to set the reference plane at the VNA cable ends.

2. Measure the primary through on the baseboard.

3. Assess IL for significant high Q deviations.

4. Assess frequency of 5 dB difference between insertion loss and return loss.

Fmax is the lowest frequency resulting from IL and IL-RL assessments. Fmax for PCIe 4.0 CEM connector evaluation should be higher than 10 GHz.

3.4 Reference Plane Definition The VNA must be calibrated to a known standard to characterize the performance of the connector in the test fixture. The intent of the calibration is to eliminate systematic errors in the measurement and improve measurement accuracy.

The precise geometric location at which a vector network analyzer measurement is made is called the reference plane. There are


sometimes two different reference planes involved in a connector measurement. If a commercial coaxial calibration kit is used, it will typically establish a reference plane near the end of the test cables. In this case, a secondary calibration is needed to remove the influence of the test fixture and move the reference plane closer to the DUT.

One key property of the reference plane is it has to be far enough from geometric transitions such as vias that ephemeral modes die out before reaching the reference plane. The mounting vias are measured as part of the DUT. The recommended reference plane position is 50 mils from any geometric transition e.g., signal trace to connector/via/anti-pad, signal trace to baseboard pad/anti-pad or signal trace to edge finger/anti-pad.

3.5 Flight Time Measure flight time to obtain the actual flight time offset between the primary through and each secondary line for the TRL calibration. The time of flight is measured using a TDT measurement following the procedure shown below:

1. Make sure the TDR instrument is properly compensated at room temperature.

Figure 3-2. TDT Instrument Temperature Compensation

2. Set the screen scale to capture 50 ps/div and leave the acquisition mode to average.

Figure 3-3. TDT Instrument Scaling and Acquisition Mode

3. Set one channel as the driver and the other channel as the receiver.


Figure 3-4. TDT Instrument Channel Setting

4. Capture the primary through and save the waveform as a reference.

5. Connect the channels to Secondary 1 and capture the waveform and measure the flight time difference between the Primary Through and the Secondary 1 (reference to 20% of the maximum voltage).

6. Repeat Step 4 for Secondary 2 and 3.

7. Record the flight time offsets of the secondary lines for TRL calibration.

8. Use

3.6 TRL Four Port Calibration TRL calibration is intended to remove the effect of the fixture moving the reference plane to closest proximity to the connector. The TRL calibration standards are designed to remove the fixture effect and to support the measurement up to 20 GHz.

1. Reboot the VNA to remove previous data in memory.

2. Set the Start and Stop frequencies for the TRL calibration in the instrument.

Note: The maximum frequency is given by the Allen Test described previously if Fmax is smaller than 20 GHz.

Note: Use measured flight time offsets in the TRL calibration.

3. Set the Number of Points of the VNA and the IF Bandwidth.

4. Load the calibration file in the equipment for Keysight.


5. Open the calibration wizard in the calibration menu and select smart calibration, (when using a Keysight VNA) and select 4 port calibration.

6. Select the calibration file for the PCI Express connector.

7. Define the ports and run the calibration making the connections on the calibration fixture on the baseboard following the wizard instructions.

8. Take notes of the delays and save the calibration.

See Appendix B for more details.

3.7 Calibration Verification

3.7.1 Secondary Line Phase Margin Verify the secondary line phase margin on new boards. The phase plot should be linear over the secondary line frequency range. Secondary line phase margin should be greater than 20 degrees.

3.7.2 TRL Calibration Stability Verify the stability of the TRL calibration using insertion loss measurement of the primary through before and after completing the test plan.

Absolute value of primary through loss |S21| after TRL calibration should be ≤ 1% [approximately 0 ±0.086 dB] up to 10 GHz and ≤ 2% [approximately 0 ±0.170 dB] between 10 and 20 GHz.

3.7.3 Dynamic Range Verify the dynamic range is large enough to capture the crosstalk. The noise floor measurement is a crosstalk measurement between two distant traces. The crosstalk reading is the noise floor, which is the lower boundary of the dynamic range the VNA in use can support after the calibration. The noise floor should be less than -50 dB up to 8 GHz and less than -40 dB up to 20 GHz.


4 Multi-Port Measurement

4.1 VNA Port Naming Convention The multi-port measurement is described using the VNA port convention in the Figure 4-1. All differential pairs other than those being measured must be terminated with 50 ohm terminators.

The measured S parameter must be referenced to 50 ohm differential impedance. The S parameter must be renormalized to 42.5 ohm before any data processing for the comparison to the PCI specification.

Figure 4-1. Port Naming Convention

4.2 Connector Pair Descriptions The port configuration for connector measurment is shown in Figure 4-2. The cylinders represent the connector pins within the DUT. The five pairs are used for testing.


Figure 4-2. Port configuration for Connector Measurement

The test/pin configuration to carry out the differential measurements of insertion and return loss is shown in Figure 4-3.

Figure 4-3. Test Configuration for DDIL and DDRL11/DDRL22


4.3 Differential Insertion Loss (DDIL) Differential insertion loss is calculated using Equation 4-1 shown where S is formatted as a complex number.

Equation 4-1. Calculation of Differential Insertion Loss DDIL

4.4 Differential Return Loss (DDRL) Differential return loss is calculated using Equation 2 shown below where S is formatted as a complex number.

Equation 4-2. Calculation of Differential Return Loss DDRL

where DDRL11 is taken from port 1 and 3 while DDRL22 is from port 2 and 4.

4.5 Crosstalk Victim-Aggressor Patterns Two different multi-aggressor crosstalk summations are calculated to capture the worse case NEXT on a victim. The multi-aggressor sums are compared against the crosstalk limit in the PCI Express Card Electromechanical (CEM) Specification, Rev. 4.

DDNEXT_BB is the crosstalk on the base board side using the victim-aggressor patterns in Figure 4-4. DDNEXT_AIC is the crosstalk on the AIC side using the victim-aggressor patterns in Figure 4-5. Test port connections for each crosstalk measurement are listed in the VNA measurement template, see Appendix C.

DDIL= 20 log10 (|S21+S43-S23-S41|/2)

DDRL11= 20 log10 (|S11+S33-S13-S31|/2)

DDRL22= 20 log10 (|S22+S44-S24-S42|/2)


Figure 4-4. Test Configuration for DDNEXT from a Victim on Base Board Side

Figure 4-5. Test Configuration for DDNEXT from a Victim on AIC


4.6 Differential Near-End Crosstalk (DDNEXT) Differential Near End Crosstalk (DDNEXT) on the victim differential pair from a single aggressor is calculated by Equation 4-3.

Equation 4-3. Calculation of DDNEXT from a Single Aggressor in dB

where input ports (1,3) are connected to an aggressor pair while output ports (2,4) are connected to a victim pair.

The power sum of near-end crosstalk on a victim pair from multiple aggressors is calculated using Equation 4-4.

Equation 4-4. Power Sum of DDNEXT from Multiple Aggressors in dB

where 𝑁𝑁 is the number of aggressors.

The power sum of near-end crosstalk on the base board victim pair from multiple aggressors in the test plan is calculated using Equation 4-5.

Equation 4-5. Multi-Aggressor Near End Cross Talk on the Base Board Side (DDNEXT_BB)

The power sum of near-end crosstalk on the add in card victim pair from multiple aggressors in the test plan is calculated using Equation 4-6.

Equation 4-6. Multi-Aggressor Near End Cross Talk on the Add-in Card Side (DDNEXT_AIC)

DDNEXT_i= 20 log10 (|S21+S43-S23-S41|/2)

DDNEXT = 10 log10 (∑ 10𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝑇𝑇𝑖𝑖/10𝐷𝐷𝑖𝑖 )

DDNEXT_BB = 10 log10 (10𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝑇𝑇𝑡𝑡𝑡𝑡𝑡𝑡𝑡𝑡6/10 + 10𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝑇𝑇𝑡𝑡𝑡𝑡𝑡𝑡𝑡𝑡7/10 +10𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝑇𝑇𝑡𝑡𝑡𝑡𝑡𝑡𝑡𝑡8/10 + 10𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝑇𝑇𝑡𝑡𝑡𝑡𝑡𝑡𝑡𝑡9/10)

DDNEXT_AIC = 10 log10 (10𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝑇𝑇𝑡𝑡𝑡𝑡𝑡𝑡𝑡𝑡10/10 + 10𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝑇𝑇𝑡𝑡𝑡𝑡𝑡𝑡𝑡𝑡11/10 +10𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝑇𝑇𝑡𝑡𝑡𝑡𝑡𝑡𝑡𝑡12/10 + 10𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝑇𝑇𝑡𝑡𝑡𝑡𝑡𝑡𝑡𝑡13/10)


5 Low Level Contact Resistance

Low Level Contact Resistance (LLCR) measurements should be made using the four wire method detailed in EIA 364-23B. Use the daisy chain design illustrated in Figure 5-1.

Figure 5-1. Daisy Chain Pattern for Connector LLCR Measurement

The contact resistance measurement should include the solder tail, base board via and the contact mating interface.

Test voltage: 20 mV maximum open circuit

Test current: 100 mA maximum

Number of readings: 500 minimum


6 Contact Current Rating The contact current rating should be made using the four wire method detailed in EIA 364-23B. Use the daisy chain design illustrated in Figure 6-1.

Figure 6-1. Daisy Chain Pattern for Contact Current Rating


A Connector Evaluation Board Bill-of-Materials

Table A-1. Bill of Materials for PCIe 4.0 Connector Evaluation Base Board and Add-In Card for SMT Style Connector

Type Description Component ID

PRINTED CIRCUIT BOARD

SMT_BOARD_THERMAL_RELIEF_GND, 8.0

1 ea 8-layer, MEG-6, SMT PCIe connector test board

CONNECTOR SMT PCIe Connector 1 ea J66 Connector under test

RESISTOR RES_D,0201,43OHM,1.00%,1/16W

8 ea R56, R57, R58, R59, R60, R61, R64, R65

Base board termination resistors

RESISTOR RES_D,0201,100.0OHM,1.00%,1/16W

2 ea R66, R67 Calibration resistors

CONNECTOR_RF

Conn_RF,2.92,STD 22 ea J56, J60, J86, J87, J88, J89, J90, J91, J92, J93, J104, J105, J106, J107, J108, J109, J110, J112, J113, J114, J115

Base board launch connectors

CONNECTOR_RF

Conn_RF,2.92,STD 10 ea J94, J95, J96, J97, J98, J99, J100, J101, J102, J103

Add-in card launch connectors


12 ea R44, R45, R46, R47, R48, R49, R50, R51, R52, R53, R54, R55

Add -in card resistor

CAPACITOR CAP NP_SMC0201_1.0PF 6 ea C33, C34, C35, C36, C37, C38

Add -in card capacitor

Table A-2. Bill of Materials for PCIe 4.0 Connector Evaluation Base Board and Add-In Card for THM Style Connector


PRINTED CIRCUIT BOARD

THM_BOARD_THERMAL_RELIEF_GND, 8.0

1 ea 8-layer, MEG-6, THM PCIe connector test board

CONNECTOR THM PCIe Connector 1 ea J44 connector under test


8 ea R22, R23, R27, R28, R29, R30, R62, R63

base board termination resistors

RESISTOR RES_D,0201,100.0OHM,1.00%,1/16W

2 ea R68, 69 calibration resistors



CONNECTOR_RF

Conn_RF,2.92,STD 22 ea J20, J67, J68, J69, J70, J71, J72, J73, J74, J75, J116, J117, J118, J119, J120, J121, J122, J124, J125, J126, J127

base board launch connectors

CONNECTOR_RF

Conn_RF,2.92,STD 10 ea J76, J77, J78, J79, J80, J81, J82, J83, J84, J85

Add-in card launch connectors


12 ea R32, R33, R34, R35, R36, R37, R38, R39, R40, R41, R42, R43

add-in card resistor

CAPACITOR CAP NP_SMC0201_1.0PF 6 ea C27, C28, C29, C30, C31, C32

add-in card capacitor


B TRL Calibration The TRL calibration kit designed to remove the test fixture effect from the S-parameter measurement are included in the connector evaluation board design using the standards shown in Table B-1.

Table B-1.TRL Calibration Kit Crossover Frequencies

Frequency Ranges Description

DC to ≤ 0.3 GHz Load 1 and Load 2

> 0.3 to ≤ 1.24 GHz Secondary #3

> 1.24 to ≤ 5.15 GHz Secondary #2

> 5.15 to ≤ 20 GHz Secondary #1

TRL calibration requires preparation including e-cal, fixture bandwidth assessment and measured secondary delay times. Table B-2 shows the typical steps used to assess fixture bandwidth.

Table B-2. E-Cal and Fixture Bandwidth Checks

Step Description

1 Restart the VNA

2 Set the frequency sweep

3 Set the port power

4 Set Averaging and IF bandwidth

5 Set e-cal calibration (6 defined throughs)

6 Save the calibration

ECAL1 IL, RL measurement of Primary through

ECAL2 IL, RL measurement of Primary through

B.1 Initial TRL Calibration Steps 1 - 22 TRL calibration requires several steps. Table B-3 and Table B-4 show the typical steps used to achieve stable TRL calibration.

Table B-3. Initial TRL Calibration Steps 1- 22

Step Description

1 Restart the VNA

2 Recall the e-cal

3 Insert a new cal kit

4 Edit Cal Kit Information

5 TRL Cal Kit Setup: Open


Step Description

6 TRL Cal Kit Setup: Short

7 TRL Cal Kit Setup: Load

8 TRL Cal Kit Setup: Primary Through

9 TRL Cal Kit Setup: Secondary 1 (use measured delay time)



12 TRL class assignment: TRL Thru

13 TRL Class assignment: TRL Reflect

14 TRL Class assignment: TRL Line/Match

15 TRL Class assignment: Isolation

16 Set the frequency sweep

17 Set the port power

18 Set Averaging and IF bandwidth

19 TRL Guided Calibration (2 defined thrus + 4 undefined thrus)

20 SmartCal (GUIDED Calibration)

21 DUT Connector selection

22 Modify Cal (2 defined thrus + 4 undefined thrus)

B.2 Final TRL Calibration Steps 23 to 46 and TRL Calibration Check

Table B-4. Final TRL Calibration Steps 23 – 46, TRL Cal Check

Step Description

23 Guided Calibration

24 Guided Calibration Step 1 of 20: Connect Port 1 to Short


26 Guided Calibration Step 3 of 20: Connect Port 1 to Port 2

27 Guided Calibration Step 4 of 20: Connect Port 1 and Port 2 to Secondary 3



30 Guided Calibration Step 7 of 20: Connect Port 1 to Load





Step Description

34 Guided Calibration Step 11 of 20: Connect Port 3 to Port 4






40 Guided Calibration Step 17 of 20: Connect Port 1 | Adapter | Port 3

41 Guided Calibration Step 18 of 20: Connect Port 1| Adapter | Port 4

42 Guided Calibration Step 19 of 20: Connect Port 2| Adapter | Port 3 : Quality check, adapter offset of Port 2 and Port 3 = Sec 3 delay +- 6 ps

43 Guided Calibration Step 20 of 20: Connect Port 2| Adapter | Port 4 : Quality check, adapter offset of Port 2 and Port 4 = Sec 3 delay +- 6 ps

44 Save the Calibration

45 Check the Calibration

CAL5 IL measure primary through using port 1 and 2 (check 0 +-0.1 dB criteria)





C VNA Measurement Template

Table C-1. Data Collection Template for 4-Port VNA Measurements


D TDR Measurement Template (Not Required)

Table D-1. Data Collection Template for TDR Measurements


E Add-In Card and Base Board Support Bracket Drawing

Figure E-1. Support Bracket Assembly Drawing for PCIe Connector Evaluation


Figure E-2. Support Bracket Side Plate Drawing for PCIe Connector Evaluation (1 of 2)


Figure E-3. Support Bracket Side Plate Drawing for PCIe Connector Evaluation (2 of 2)


Figure E-4. Support Bracket Mid-Beam Drawing for PCIe Connector Evaluation (1 of 2)


Figure E-5. Support Bracket Mid-Beam Drawing for PCIe Connector Evaluation (2 of 2)

Date post:	28-Nov-2019
Category:	Documents
Upload:	others
View:	10 times
Download:	0 times