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SERVICE MANUAL 6204 Operation and Maintenance EVENTTRAK DIGITAL EVENT RECORDER SYSTEM INTERPRETER UNIT N451400-3301 (Compatible Only with Original Monitor Unit Version Using Controller PCB N451441-5101) December, 1983 (Revised November, 1986) B-11/86-75-2566-3 1001358 PRIN fED IN v SA UNION SWITCH & SIGNAL DIVISION AMERICAN STANDARD INC/PITTSBURGH, PA 15237 COPYRIGHT 1986. \JS&S DIVISION OF AMERICAN STANDARD tNC
Transcript
Page 1: PDF Viewing archiving 300 dpi - Hitachi Rail...SERVICE MANUAL 6204 Operation and Maintenance EVENTTRAK DIGITAL EVENT RECORDER SYSTEM INTERPRETER UNIT N451400-3301 (Compatible Only

SERVICE MANUAL 6204

Operation and Maintenance

EVENTTRAK

DIGITAL EVENT RECORDER SYSTEM

INTERPRETER UNIT N451400-3301

(Compatible Only with Original Monitor Unit Version Using Controller PCB N451441-5101)

December, 1983 (Revised November, 1986) B-11/86-75-2566-3 1001358

PRIN fED IN v SA

UNION SWITCH & SIGNAL DIVISION AMERICAN STANDARD INC/PITTSBURGH, PA 15237

COPYRIGHT 1986. \JS&S DIVISION OF AMERICAN STANDARD tNC

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...

Page 3: PDF Viewing archiving 300 dpi - Hitachi Rail...SERVICE MANUAL 6204 Operation and Maintenance EVENTTRAK DIGITAL EVENT RECORDER SYSTEM INTERPRETER UNIT N451400-3301 (Compatible Only

SERVICE MANUAL 6204

Operation and Maintenance

EVENTTRAK

DIGITAL EVENT RECORDER SYSTEM

INTERPRETER UNIT N451400-3301

(Compatible Only with Original Monitor Unit Version Using Controller PCB N451441-5101)

December, 1983 (Revised November. 1986) B-11/86-75-2566-3 1001358

PRINTED IN USA

/

UNION SWITCH & SIGNAL DIVISION AMERICAN STANDARD INC./PITTSBURGH, PA 15237

COPYRIGijT 1986, US&S DIVISION OF AMERICAN STANDARD INC.

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UNION SWITCH Ii SIGNAL

Revised pages of this manual are listed below by page number and date of revision:

Page Number oate of Revision Page Number Date of Revision

1-1 11/86

1-6 11/86

2-2 11/86

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CONTENTS

Section

I

II

GENERAL 1.1 1.2 1.2.1 1.2. 2 1. 2.3 1.2.4 1.2.5 1.3 1. 3.1 1.3. 2 1. 3. 3

INFORMATION GENERAL COMPONENTS Case, Card Enclosure and Motherboard Microprocessor Controller PCB N451208-0106 Front Panel PCB N451441-5201 RAM PCB N451441-4909 Power Supply PCB N451204-2901 SPECIFICATIONS Physical/Mechanical Electrical/Electronic Miscellaneous

OPERATION 2.1 CONTROLS AND INDICATORS

APPLICATION OF OPERATING POWER CRT OR PRINTER SET-UP

2.2 2.3 2.4 2.4 .1 2.4. 2 2.5 2.5.1 2.5.2 2.6 2.6.1 2.6.2

MONITOR UNIT DOWN-LOADING Set-Up of Direct or Remote Output Down Load Procedure PRINT-OUT FROM INTERPRETER UNIT Complete File Output or Abort Skip Procedure MNEMONICS PROGRAMMING Mnemonic Tables Set-Up EPROM Loading

III FUNCTIONAL DESCRIPTION 3.1 GENERAL 3.2 MICROPROCESSOR CONTROLLER PCB N451208-0106 3.2.1 Microprocessor Bus and Peripherals 3.2.2 I/0 Connnunications Circuits 3.3 RAM PCB N45144-490X

IV TROUBLESHOOTING AND MAINTENANCE 4.1 GENERAL 4.2 MICROPROCESSOR CONTROLLER PCB (N451208-0106) 4. 2.1 Required Test Equipment 4. 2. 2 Test Set-Up 4. 2. 3 Test Procedure Connnents 4. 2.4 Procedure 4.3 RAM PCB (N45144 l-4905) 4. 3.1 Required Test Equipment 4. 3. 2 Test Set-Up 4. 3. 3 Test Procedure Connnents 4. 3.4 Procedure 4 .4 FRONT PANEL PCB (N45144 l-5201) 4.4.1 Reconnnended Test Equipment 4 .4 .2 Test Set-Up 4 .4. 3 Procedure

i

UNION SWITCH & SIGNAL m

1-1 1-1 1-1 1-1 1-2 1-4 1-5 1-5 1-5 1-5 1-6 1-6

2-1 2-1 2-2 2-2 2-3 2-3 2-5 2-6 2-6 2-7 2-7 2-7 Z-9

3-1 3-1 3-1 3-1 3-5 3-6

4-1 4-1 4-1 4-1 4-2 4-3 4-6 4-18 4-18 4-18 4-19 4-20 4-22 4-22 4-22 4-23

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m UNION SWITCH & SIGNAL

Section

4.5 4.5.1 4.5.2 4.5.3

CONTENTS (cont'd)

POWER SUPPLY PCB (N451204-2901) Recommended Test Equipment Test Set-Up Procedure

v SUPPLEMENTAL DATA 5.1 RECOMMENDED REFERENCE LITERATURE 5. 2 DIAGRAMS

APPENDIX A A. l A.2 A.3 A.4 A.5 A.6

Figure

1-1 1-2 2-2

2-3 3-1 4-1 5-1 5-2 5-3 5-4 5-5 5-6 5-7 A-1 A-2 A-3 A-4 A-5 A-6

PARTS LIST CASE ASSEMBLY MICROPROCESSOR CONTROLLER PCB N451208-0106 RAM PCB N451441-4905 FRONT PANEL PCB N451441-5201 MOTHERBOARD PCB N451605-5501 POWER SUPPLY PCB N451204-2901

ILLUSTRATIONS

Eventtrak Interpreter Application Diagram Eventtrak Interpreter Unit Interpreter/Terminal Interfaces: EIA and 20 mA Current Loop Monitor/Interpreter Remote Output Set-Up Interpreter Unit Block Diagram Eventtrak Monitor Unit/Terminal Cable Microprocessor Controller PCB Schematic Diagram Microprocessor Controller PCB Schematic Diagram (Cont'd) Microprocessor Controller PCB Schematic Diagram (Cont'd) RAM PCB Schematic Diagram Front Panel PCB Schematic Diagram Motherboard PCB Schematic Diagram Power Supply Schematic Diagram Case Assembly · Microprocessor Controller PCB Component Layout RAM PCB Component Layout Front Panel PCB Component Layout Motherboard PCB Component Layout Power Supply PCB Component Layout

ii

4-24 4-24 4-25 4-25

5-1/2 5-1/2 5-1/2

A-2 A-6 A-8 A-10 A..-12 A-14

1-2 1-3 2-3

2-4 3-3/4 4-19 5-3/4 5-5/6 5-7/8 5-9/10 5-11/12 5-13/14 5-15/16 A-3/4 A-7 A-9 A-11 A-13 A-14

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l. 1 INTRODUCTION (Figure 1-1)

SECTION I GENERAL INFORMATION

UNION SWITCH & SIGNAL m

The Eventtrak Interpreter unit N451400-3301 is a portable microcomputer system which down-loads stored event data from the Eventtrak Monitor unit for subsequent output to a printer or CRT terminal away from the Monitor unit. It also allows the user to program customized mnemonics for the Monitor unit event print-out software.

Down-loading of event records is accomplished in two ways. The interpreter unit may be carried to a particular monitor unit location and connected directly to that unit for record transfer. A standard EIA RS-232C cable interface is used for this purpose. The interpreter unit may also be stationed at the central office to receive monitor unit records via the office/field code system. The latter method permits more rapid accessing of various field monitor units.

The monitor unit microprocessor PCB contains an erasable programmable read-only memory (EPROM) chip which is dedicated to the custom mnemonics programming. When this chip is not programmed (blank), the print-out from the event record will show the state of various inputs in a simple 1 (on), 0 (off) or F (flashing) format. The interpreter unit contains a socket which enables the monitor unit mnemonics EPROM to be programmed, through the interpreter unit. Program instructions are created on a terminal connected to the interpreter through an EIA interface separate from the down-loading interface.

The interpreter unit is cabable of down-loading the full memory of a 48K RAM monitor unit. Internal batteries retain the data for approximate~y 4.0 years under a power-down condition.

Refer to SM-6203 for monitor unit information.

1. 2 COMPONENTS

1.2.1 Case, Card Enclosure and Motherboard (See Figure 1-2)

All interpreter unit components are contained in a portable fiberglass case with a latching cover. The case contains a low-profile sheet steel enclosure which holds four plug-in printed circuit boards: Front Panel, Microprocessor Controller, RAM and Power Supply. All PCB's plug into a printed circuit "motherboard" (N451605-5501), which carries board-to-board couununications. Some Microprocessor Controller PCB signals are connected to the motherboard through a 50-line flat ribbon cable. The Motherboard contains discrete logic which enables either controller PCB or RAM PCB non-program memory.

All interpreter unit controls and indicators pertinent to down-loading and programming operations are displayed on a sheet metal control panel. The devices are electrically connected and mounted on the Front Panel PCB beneath the panel. Refer to sections 1.2.4 and 3.1 for descriptions of these devices. The four holes on the panel are used to ventilate component generated heat.

6204, P• 1-1

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m UNION SWITCH & SIGNAL

EPROM PROGRAMMING

TRANSFER TO MONITOR MPU PCB

!AFTER PROGRAMMING - - - - -

120 VAC (NOM)

r, - -)i I

L.J

EVENTTRAK MONITOR

DOWN-LOAD EVENT DATA

EVENTTRAK INTERPRETER

EVENT DATA OUTPUT (EIA) *

EPROM MNEMONICS

PROGRAMMING*

CRT OR PRINTER

(INTERACTIVE)

*OVER SAME EIA INTERFACE

Figure 1-1. Eventtrak Interpreter Application Diagram

1.2.2 Microprocessor Controller PCB N451208-0106

The Microprocessor Controller PCB is responsible for all Eventtrak Intepreter processing and decision making functions. It is mounted directly beneath the front panel PCB in the enclosure. The board contains both fixed program memory and short term "scratch pad" memory.

Microprocessor

The controller PCB uses a single 8-bit 6802 microprocessor as the prinicple controlling chip. It is an NMOS device having 128 bytes of on-chip random access memory (RAM).

PROM's

The controller PCB is equipped with four erasable programmable read-only memory (EPROM) IC's which contain the permanent control software for the unit. The board contains eight PROM sockets, however only four are used. Each PROM has a memory capacity of 16K bits (2K bytes).

6204, p. 1-2

J •

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UNION SWITCH & SIGNAL m

Figure 1-2. Eventtrak Interpreter Unit

620+, P• 1-3

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m UNION SWITCH& SIG ... AL

RAM's

There are 16 random-access memory (RAM) chips on the controller which are used to store variable data for miscellaneous processing purposes (not used for event record storage). The RAM IC's are divided into eight pairs which can hold 1024 bytes of 8-bit read/write memory for a total of 65,536 bits (8192 8-bit bytes).

PIA's

Two 6821 peripheral interface adapter (PIA) IC's provide 20 interface I/0 lines between the microprocessor-based components and other devices on the board.

ACIA

A single 6850 asychronous communications interface adapter (ACIA) IC provides serial communications (input and. output) for the microprocessor circuits. This component pertains to the EIA interfaces between the interpreter unit and external devices, including the monitor unit and terminal. ·

PTM

A 6840 programmable timer module (PTM) is used by the system software to control the timing of various on-board events.

Bit Rate Generator

The bit rates for the serial interfaces are established by an MC14411 bit rate generator. Six different bit rates (jumper selected), from 110 to 9600 baud, are available.

DIP Switch

A single dual in-line package (DIP) switch, with seven rockers, is provided on the controller board for miscellaneous programming purposes. The configuration of the rockers is read by the system software.

LED's

The controller PCB is equipped with five light-emitting diodes which are used for system monitoring during troubleshooting.

1.2.3 Front Panel PCB N451441-5201

The Front Panel PCB serves as the control/indicator mounting and external communications interface for the interpreter unit, and as the monitor unit EPROM progamming interface. Display components include three LED's which assist in EPROM programming, a single LED which indicates power on (+5 volts), two toggle switches which format the output to a terminal, one general mode select toggle switch and a power on/off toggle switch. Adjacent to the power toggle switch is an 1.5 amp fuse for circuit protection, and a 3-pin male plug for applying operating power (120 Vac nominal). Male and female 25-pin connectors are provided on the PCB for the terminal and monitor unit EIA interfaces, respectively.

6204, P• 1-4

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UNION SWITCH & SIGNAL m The blank Eventtrak Monitor Unit EPROM is plugged into a 24-pin, zero-insertion force (ZIF) connector on the interpreter unit front panel PCB. A lever on this connector closes the connector sockets on the EPROM pins. The majority of Front Panel PCB components are used to support progamming of the EPROM. Two PIA IC's are used as buffers to hold programming data, and for managing addresses and data controls from the controller PCB. Two power supply circuits, which include 21 and 25 volt converter-regulator IC's, provide these optional voltages for EPROM programming.

A +5 to +/-12 volt converter IC is used to power the EIA interfaces.

1.2.4 RAM PCB N451441-4909

The Random Access Memory (RAM) PCB is used exclusively for storage of wayside event data (down-loaded from the monitor unit), until output is made to a printer or CRT. It is equipped with 24 sockets designed to hold RAM IC's, each with a capacity of 2K bytes of data. Total capacity is 48K bytes. Four l-of-8 decoder IC's on this board are used by the CPU PCB to select groups of RAM IC's for data recording and retrieval. One 3.68 volt lithium battery is provided to protect RAM data when external power is disconnected. This board is identical to the 48K RAM board used in the monitor unit.

1.2.5 Power Supply PCB N451204-2901

This PCB provides the primary operating power for the interpreter unit. It contains two semiconductor modules which convert 120 volts (nom.) to +5 volts at 5 amps and +30 volts at 500 milliampheres. The +5 volt output is used for all electronic components on all other PCB's, except the programming power circuits on the Front Panel PCB. The +30 volts output is provided for these circuits.

1.3 SPECIFICATIONS

1.3.l Physical/Mechanical

Dimensions:

Weight:

Temperature Environment:

Access:

Connections:

L = 19.211 (48.7 cm), W = 15.2511 (38.7 cm), D = 811 (20.4 cm)

35 lbs. (15.875 kg.)

0 - 60o C@ 95% relative humidity

Hinged cover and PCB enclosure, plug-in PCB Is

One 25-pin "D" style female plug (RS-232C, monitor unit down-loading)

One 25-pin "D" style male plug (RS-232C, output to CRT or printer)

One 3-pin male plug (power input)

6204, p. 1-5

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UNION SWITCH & SIGNAL

1.3.2 Electrical/Electronic

Fuse (Qty= 1):

Power supply Input:

Power supply outputs:

1.3.3 Miscellaneous

Event Storage Capability:

Accurate data after power off:

Monitor/Interpreter communications:

Interpreter/Terminal communications:

standard output Mode (To Terminal):

output Bit Rate (From Monitor unit):

output Bit Rates (To Terminal):

Typical Bit Rate:

Recommended oata Terminals:

Logic Families:

Top Patt Numbers:

6204, p. 1-6

1.5 amp, 250 volt, 3 AG -type

105 to 125 vac, 120 Vac (nom.)@ 3 amps (max.), 50 or 60 Hz.

+5 Vdc@ 5.0 amps (max.)

+30 Vdc@ 500 milliamps (max.}

Up to 12,000 events

4.0 Years (max.)

EIA (RS-232C standard)

EIA (RS-232C standard) 20 mA current loop

8-bit ASCII, 1 stop bit, no parity

9600 bits pet sec. (BPS)

110, 300, 600, 1200, 2400, 4800, 9600 (BPS)

300 Baud

Teletype Model 43, TI Silent 700, most CRT's

NMOS, CMOS, TTL

Unit: N451400-3301 Microprocessor controller PCB: N451208-0106 RAM PCB: N451441-4909 Front Panel PCB: N451441-5201 Power supply PCB: N451204-2901 Monitor/Interpreter Cable: N451458-4601

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SECTION II OPERATION

UNION SWITCH & SIGNAL m

2.1 CONTROLS AND INDICATORS

Figure 2-1 shows the interpreter controls and indicators, which are accessible by opening the case cover. The following tabulation describes these devices:

Name Function

COLUMN SIZE (PRINTER) 2-position toggle switch; selects 80 or 132 character printer/CRT output.

SKIP (PRINTER)

START

2-position toggle switch; enables event data to be passed over to observe data of interest from a later time.

Pushbutton; initiates actual print-out or display of interpreter-stored data on printer or terminal, and down-load of event data from the monitor unit. Also permits abort of print-out.

MODE SELECT 3-position toggle switch; selects one of the following modes: Monitor unit down-loading, EPROM programming or output to terminal.

POWER LED; indicates power supply PCB is providing regulated +5 volt output. On steadily when power is applied.

MEMORY OVER RUN LED: Coordinated indications with PROM/MONITOR COMPLETE and PROM ERROR LED's for following functions:

a. Initial RAM examination (no prior data), RAM down-load "-eady" indication, and progress of the down-load.

b. EPROM pre-programming "ready" indication, and progress of EPROM programming.

c. Progress of event data print-out, print abort or temporary stop of print-out.

d. Skip procedure in progress.

PROM/MONITOR COMPLETE LED: Coordinated indications with MEMORY OVERRUN and PROM ERROR LED's (see above).

PROM ERROR LED: Coordinated indications with MEMORY OVERRUN and PROM/MONITOR COMPLETE LED's (see above), and indication of format error during writing of mnemonics on terminal.

ON/OFF 2-position toggle switch, turns on interpreter unit power.

6204, p. 2-1

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m UNION SWITCH & SIGNAL

Pl1 I • - -

....... - :)

PHii SOCKET

®': CILUIIII Sil(

PNTEI

@ IIGIIITOI Pflflll PIN. TERIIIIIAL

MOD( SEUCT

~ STAIT

dl:\ Oii

~ OFF

SKIP

$ $

• PIIWEI

• IIOIIIIY ffll 11U11

• PIIM/IIIIITN c•PUTE

• .... (llttl IB IB

MONITOR IS-232-C c TEIMNIAL IS-232-C \

Figure 2-1. Interpreter Unit control Panel Layout

2.2 APPLICATION OF OPERATING POWER

O FUS( . 1%A./2H I

@: )

)

connect the ac power cord, provided with the interpreter unit, to the 3-pin male plug on the control panel: make certain the power ON/OFF switch is off at this time. Plug the cord into a standard 120 Vac source and turn on interpreter unit. The POWER LED should light. Turn off the interpreter power before making any other connections.

2.3 CRT OR PRINTER SET-UP

The interpreter unit is internally preset to communicate with a terminal or printer having an 8-bit ASCII format with one stop bit and no parity. Either standard EIA or 20 mA current loop operation can be used. Figure 2-2 shows the cabling/pin-out configurations for both modes. Plug this connector/cable assembly into the TERMINAL RS-232C plug (male) on the control panel (power toggle switch to OFF).

The interpreter unit requires jumper settings on the CPU PCB to match the bit rate and communications mode with the terminal. To access this PCB, remove the PCB enclosure and remove the CPU PCB (power off). This PCB is directly beneath the Front Panel PCB. Disconnect the ribbon cable connector on the PCB before removal.

6204, p. 2-2

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UNION SWITCH & SIGNAL ffi r-----

oPEN >------.. ----------1 OV I

DATA IN

COMMON

COMMON COMPUTER

I I

EIA (RS-232C) MOOE DATA OUT

I =t~ --........ )·~

OPEN~-----·----------, OV

L- - ---'

I I 80CD I --t~i )~

·-, 17----~ 11 :

-4 12 I

_ii I ( 14

XMIT + (OUT)•

XMIT - (IN)

RE~+ (OUT)•

20 MA CURRENT LOOP ~ >1 ... ,s .... _....,l:.,a..+.-~RE:.;C:;..-...:.;;<IN~l-....,._

MODES: (·I I 1 COMMON I ' SHIELD

·cuRRENT LOOP POWER

INTERPRETER ACTIVE

JUMPERED WHEN NOT REQUIRED BY APPLICATION

,lJ,. DENOTES '</ TWIST PAIR

:..::.1-------""""~i--·...;.x_M_1T_·_!O~UTJ----.... ,

I __.

1,_1_3 ______ -t--+---xM_1_T_o_N_D_11N.>_· __ __.._

1

I 15 REC - OUT -+>,------t-+-----------· ~.,_1_a ______ .._....,. __ R_ec __ o_ND....,.<1N.D.r ____ ..,_,

I I, COMMON

~I I

: ~1 s.crs : 80CD I

20 DTR I

I I I -- , ____ .J

SHIELD

•EXTERNAL C. L. POWER

INTERPRETER PASSIVE

Figure 2-2. Interpreter/Terminal Interfaces: EIA and 20 mA Current Loop

To establish EIA RS-232C communications, install a jumper in JP5. Install a jumper in JP4 for 20 mA current loop operation. Next, install one jumper at JP6 to match the bit rate of the interpreter with the bit rate of the terminal. The bit rates marked 75, 150, and 1800 are not valid for the interpreter unit.

2.4 MONITOR UNIT DOWN-LOADING

2.4.1 Set-Up of Direct or Remote Output

US&S provides a finished connector/cable assembly, part no. N451458-4601, for the direct monitor/interpreter interface. Plug this cable into the 25-pin connector through the monitor unit trout cover and the MONITOR RS-232C female plug on th~ interpreter unit (power otf for both units).

6204, p. 2-3

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UNION SWITCH & SIGNAL

The 25-pin EIA connector on the monitor unit may be wired to the code system modem to enable remote transmission of the event data. Pin 25 of this connector on the monitor unit is wired in parallel with the unit's PRINT switch. By connecting this pin through a relay contact to common, the code system can be used to intiate a remote output command to the monitor unit. A control bit for this relay is required on the interpreter unit end of the system. This set-up is illustrated in Figure 2-3.

REMOTE PRINT RELAY

ov -~ ..... DED. /,1 i -CONTROL

FIELD CODE PRINT '" - BIT UNIT /'

DATA

'" -I , '

STANDARD CODE SYSTEM DATA t FRONT

MPU COVER PCB ''D'' MONITOR DATA/CODE SYSTEM

CONNECTOR ,, DATA SWITCHING UNIT

~ I

~ MONITOR UNIT .... , I FIELD MODEM -· . ' •, •,

INTERPRETER UNIT •• 'l

OFFICE MODEM

I I j. a.

MONITOR RS-232C DOWN LOAD DATA .... -

OFFICE CODE

Figure 2-3. Monitor/Interpreter Remote Output Set-Up

6204, p. 2-4

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2.4.2 Down-Load Procedure

Operation Verification

Turn on interpreter unit power.

1. POWER LED should 1.

2.

3.

4.

Set the interpreter 2. unit MODE SELECT switch in the MONITOR position and push the START button.

If making a direct 3. (local) output, move the PRINT switch on the monitor unit to either the A or B position. If making a remote output, send the bit to close the special monitor relay contact.

If the down-load has 4. to be aborted, set the monitor unit PRINT switch back to the cen­ter position (or close special remote contact).

light. MEMORY OVER­RUN, PROM/MONITOR COMPLETE and PROM ERROR LED I s may flash similtaneously 12 times, or remain dark.

The MEMORY OVERRUN, 2. PROM/MONITOR COMPLETE and PROM ERROR LED's may light steadily, or may flash once, then go dark.

Opto-Isolator PCB(s) 3. LED(s) on monitor stop flashing. The interpreter MEMORY OVERRUN and PROM ERROR LED's will flash si­miltaneously and the PROM/MONITOR COMPLETE LED lights steadily. The flashing LED's then halt (both on or off) and PROM/MONITOR COMPLETE begins to flash.

2 minutes after the 4. abort, the monitor unit Opto-Isolator PCB(s) LED(s) begin flashing.

UNION SWITCH & SIGNAL. m Comments

All of these LED's will will flash if there is no prior_ event data in interpreter memory. Each similtaneous flash indicates 2K of RAM is checked. If cycle stops and all three LED's re­main lit, not all RAM locations were verified. If RAM memory already contains event data at power-up, these LED's will remain dark.

All these LED's will light steadily when RAM memory is clear and the interpreter is in proper condition to receive data. The single flash shows RAM memory already contains event data.

Monitor unit taken out of event recording mode. The data transfer is preset to 9600 baud, consisting of 45.6~ bits of compressed event changes and 1.2K bits of ASCII mnemonic format data. The initial state of the participating LED's shows the down­load is proceeding nor­mally. The next change shows the down-load is complete or temporarily halted (i.e., to permit normal code line trans­missions).

A 2-minute timer is started in the monitor unit at down-load abort. The user can restart the down-load by moving the monitor unit PRINT switch back to the A or B positions.

6204, P• 2-5

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m UNION SWITCH & SIGNAL

A problem during the down-load is indicated by the MEMORY OVER RUN, PROM/MONITOR COMPLETE and PROM ERROR LED's. If the PROM ERROR LE~ lights, an error was generated during the data transfer. If only the MEMORY OVERRUN LED lights, the data was correctly received, but the memory capacity of the interpreter RAM PCB was exceeded. This could be caused by a monitor unit problem or more than one attempt to down-load the data without first resetting the system. To clear the MEMORY OVERRUN, PROM/MONITOR COMPLETE and PROM ERROR LED's, toggle the MODE SELECT switch in and out of the MONITOR position.

To verify that the data was properly recorded, conduct an immediate print out of the data, using the "skip" option. If the "END OF FILE" message appears on the print-out, the down-load most likely was successful. Refer to the following section for procedures.

2.5 PRINT-OUT FROM INTERPRETER UNIT

2.5.1 Complete File Output or Abort

1.

2.

3.

4.

Operation

Set the MODE SELECT switch to the TERMINAL position.

Set the COLUMN SIZE switch to either the 80 or 132 position and change cables.

Press the START button once.

1.

2.

3.

If the print-out has 4. to be aborted, press the START button once.

620!., P• 2-6

Verification Comments

1. This changes the inter­preter from the receiv­ing to the transmitting RS-232C interface.

2. Accomodate terminal print-out requirements.

CRT or printer is 3. operational. The PROM/MONITOR COMPLETE and PROM ERROR LED's are lit steadily, and MEMORY OVERRUN LED flashes very briefly. These LED's then go dark.

The terminal will 4. stop the file output and display "PRINT ABORTED". On the in­terpreter, the MEMORY OVERRUN and PROM ERROR LED's will flash alter­nately and the PROM MONITOR ·COMPLETE LED will be lit stead~ly.

The printer will com­mence with mile post, time, bit heading and event data. (Refer to SM-6203 for example and explanation of the print-out format.) The MEMORY OVERRUN LED flash occurs with output of each new RAM location.

A 2-minute timer is started in the interpre­ter when the print-out is aborted. The user can restart the print by pressing the START but­ton again. The printer will then pick up with next event file.

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UNION SWITCH & SIGNAL m 2.5.2 Skip Procedure

To go to specific data of interest, move the interpreter unit SKIP switch to the ON position (MEMORY OVERRUN and PROM ERROR LED's light steadily at this time). This will create a date and time promt "MM-DD-YY HR" on the terminal, which the operator completes to go to the requested point. For example, 1112-17-82 13" would yield all data starting from December 17, 1982, at 1:00 PM. The skip can only be specified to the nearest hour. ·

2.6 MNEMONICS PROGRAMMING

2.6.1 Mnemonic Tables Set-Up

With an interactive terminal connected to the interpreter unit, the customer can define mnemonic characters for all 128 input lines to the monitor units. These are programmed into an EPROM which is plugged into the interpreter front panel and, after completion of the programming (refer to section 2.6.2), removed to the MPU PCB of the selected monitor unit. To configure. the interpreter and terminal for mnemonics definition, keep the MODE SELECT switch in the TERMINAL position.

The interpreter will respond to a series of commands entered on the terminal. Following is a list of recognized commands:

Command Name

HELP

REVIEW

CLEAR

CRT

NOCRT

ONES

Purpose

This command prints the HELP file, which gives a summarized explanation of the instructions.

Review the current table contents. This command is used in conjunction with the ones, zeros, flashing or type commands. The data is printed out in eight groups of 16 lines each.

Clear the current table contents. This command is used in conjunction with the ones, zeros, flashing or format commands. Before the table is cleared, the message "ARE YOU SURE? Y/N" is printed. Responding with a "Y" (yes) causes the entire table contents to be cleared.

Set the input device to CRT.

Set the input device to hard copy.

Input the ones mnemonics. This mode will place a number specifying the input on the printer, followed by the previously defined character mnemonic. A prompt will be placed on the following line to call for the new mnemonic. To keep the previous mnemonic or skip this input, type a carriage return.

Each input must have three ASCII characters. The typical form consists of one or two characters, followed by one or two spaces, respectively. Since any valid ASCII character

6204, p. 2-7

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UNION SWITCH & SIGMAL

Mnemonics Connnand Terms (Cont'd)

Command Name Purpose

ZEROS

FLASHING

TYPE

is allowed, the user can chose special characters for certain conditions. Do not use "carriage return", "form feed" or any other character which may cause a confusing output. Note that the default character is a space or the character previously defined.

Input the zeros mnemonic. The same format recommendations (for the ones mnemonic) also apply for this mnemonic.

Input the flashing mnemonic. When entering the mnemonics for the non-flashing type input, a special error character (typically a "1fa'') may be used to flag the occurence of an error condition. The same format recommendations (for the ones mnemonic) also apply for this mnemonic.

Input the bit type information (only one character allowed). This command will place a number on the printer specifiying which input type is currently being entered. Two types of inputs are allowed, including flashing ("F") or non-flashing ("N"). When entering the mnemonic for a flashing type input, the typical form should be an "F", followed by the remainder of the required characters. The same format recommendations (for the ones mnemonic) also apply for this mnemonic.

The interpreter unit will allow several of the standard control characters, typically found on computer systems. These are as follows:

CNTR-C

CNTR-U

C~R-R

62CX., p. 2-8

Abort the current command at the present point. All commands can be terminated with this control. This allows review or modification of only a portion of the mnemonic input, then continuation to another command. Abort the current line. This permits correction of mistakes on input.

Repeat the current line. This helps clarify an input if that input was garbled for some reason.

NOTE

If there are any input, format etc. errors during mnemonics writing, the PROM ERROR LED on the inter­preter will light. The programmer must be observant for this indication since it will go dark with the next correct entry (interpreter cannot inhibit faulty inputs to the te rmina 1).

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UNION SWITCH & SIGNAL m 2.6.2 EPROM Loading

The interpreter unit is capable of programming a type 2716 (2K, 8-bit) erasable progammable read-only memory (EPROM) IC. Mnemonic data is entered under program control by the user. Two types of 2716 EPROMS are available, including 21 and 25 volt inputs. The interpreter is assembled by US&S for progamming of the 25 volt type of EPROM.

The Front Panel PCB has two voltage supply circuits working in compliment (25 volt source active when 21 volt source is inactive, and vice-versa). A jumper selects the 25 volt supply. To enable use of a 21 volt EPROM, use the following procedure:

1. Turn off interpreter unit power (POWER LED goes dark).

2. Remove the nuts and screws which secure the various toggle switches, the two 25-pin connectors and the 3-pin power plug. Remove the fuse holder also.

3. Remove the six screws (left and right) on the panel and carefully lift panel. Lift the EPROM socket lever up so that the panel clears this device without damage.

4. Remove jumper Jl (near the edge connector having copper contacts). This converts the board to the 21 volt supply circuit.

5. Carefully reassemble the panel and components.

The EPROM loading procedure is as follows:

Operation Verification Comments

1. Plug the blank EPROM 1. 1. into PROM SOCKET with the lever up and the chip indentation toward the lever side of the socket. Then push down the lever to make proper electrical contact with the EPROM pins. Power should be off.

2. Turn interpreter 2. POWER LED lights. 2. unit power on.

3. Place the MODE SELECT 3. 3. Interpreter removed from switch in the PROM either the down-load or PROG posit ion. print-out configuration.

6204, P• 2-9

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ffi UNION SWITCH & SIGNAL

Operation

4. Press the START button once.

4.

Verification

The PROM/MONITOR 4. COMPLETE LED should first light steadily, followed by a cycle operating as follows:

-PROM/MONITOR COM­PLETE LED on steady.

-MEMORY OVERRUN AND PROM ERROR LED's al­ternating.

-PROM/MONITOR COMPLETE on steadily again.

Above cycle repeats until programming is complete (approx 1 min.)

Comments

The initial PROM/MONITOR COMPLETE indication must appear before EPROM pro­gramming can be success­fully executed (EPROM verified to be blank).

If the PROM ERROR LED lights immediately after the START button is pressed, the EPROM is not blank. If this LED lights after one minute, the programming procedure has not been successful. In either case, repeat the procedure with a new EPROM.

6204, P• 2-10

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SECTION III FUNCTIONAL UESCRIPTION

3.1 GENEKAL lSee Figures 3-1 and 5-5)

UNION SWITCH & SIGNAL

all interpreter unit PCB's contain microprocessor peripheral devices which are controlled directly by tne microprocessor on the controller PCB, including EPKUM programming PIA's on the Front Panel PCB, and RAM IC's/decode logic on the RAM. PCB. IC2 on tne motherboard is an octal flip-flop which the microprocessor (controller PC.B) uses to develop addresses for RAM IC's (RAM PCB) when event data is being initially recorded. ICl (also controlled by the microprocessor) is a 3-input NANU gate used in conJunction with IC2 to create an address validation signal for data entering RAM memory on the RAM PCB. The power-up reset for the interpreter unit is generated through transistor Ql on tt1e motne rboa rd.

PIA IC4 on the Front Panel PCB is selects either the 21 or 25 volt power circuit for EPJIDM programming, in addition to supplying program data for the EPKUM. Jumper Jl installed (tactory) causes IC4 to switch on optical coupler IG6, which enables the adjacent 25 volt output circuit (voltage regulator lCl). Coupler IG7 (21 volt circuit) is switched on when Jl is removed.

3.2 MICROPROCESSOR CONTROLLER PCB N451208-0106 (See Figures 5-1 through 5-3)

3.2.1 Microprocessor Bus and Peripherals

NOTE

The terms 11M.SG11, "ACK", "STROBE", 11 BREQ11

, "G-IN", "G-OUT" "GK.ANT" and "RDY", and "SYSTEM DATA", which appear on the Microprocessor Controller schematic (Figure 5-1), are carried over from a previous application of this board and are irrelevant to operation of the interpreter unit.

The controller PCrl consists basically of the microprocessor IC36, its immediate peripherals (EPlillf'l 1 s, l{Afl's, PIA's, PTM and ACIA) and support chips. The 6802 microprocessor is the exlusive controlling chip on the boara. Its check signal is generated by 4.0 MHz crystal XTAL l; the microprocessor divides this base trequency by four. The resulting 1.0 MHz signal is used to sequence various internal operations. The 128-byte byte on-cnip RAJ.vi is usea for miscellaneous "scratch-pad" memory during various operatiops.

The microprocessor uses a lb-line address bus (AO to Al5), an 8-line data bus (UO to D7) and a multi-purpose control bus (IK~, VMA, HALT, NMI, BA, R/W, E and 1<.ESET) to communicate with the major peripl:).erals on both tile controller PCB and other interpreter unit PCB's. Data lines are buffered for the controller and RAM. PCB RAM.'s, the controller PCB EPROM's and Front Panel PCB Pl.A's by bi-directional bufters IC9 and IC20. These buffers are necessary, in part, because of the large number of RAM' s which must be driven by the microprocessor. The microprocessor drives the data lines for the controller PCB PIA's, PTM. and ACIA directly (unbuffered data). The IC21 and IC34 gates aaJacent 1C9 ;.md IC20 ai;e used to enable the "output" buffers when data is

i:>204, P• 3-1

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m UNION SWITCH & SIGNAL

being delivered to peripherals (DRIVER EN), or the "input" buffers'when data is being received from peripherals (REC EN). All address lines are buffered by IC's 31 to 33. Separate l-of-8 decoder/demultiplexers, each with address and control gates, enable the microprocessor to select specific chips on and off the controller PCB for addressing. The address decode bus (included in Figure 3-1 under CONTROL bus) includes the PSEL (EPROM select), RSEL (RAM select) and MSEL (misc. chip select) lines. The RSEL lines only select the RAM IC's on the controller PCB itself. The MSEL lines select all other controller PCB peripherals except EPROMS (PSEL), plus IC2 on the motherboard and the PIA's on the Front Panel PCB. MSEL 8 is used in conjunction with IC2 to address the RAM IC's on the RAM PCB, as a group.

The IRQ (interrupt request) control line is used by the on and off-board peripherals to flag the microprocessor on change a change of operation. E (enable) is the basic clocked output from the microprocessor used to sequence operations of the peripherals. The microprocessor uses the R/W (read/write) line to inform the peripherals when it is in a condition to receive data (read) or deliver data (write). The valid memory address (VMA) line is used to inform perihperals of a correct address on the address bus. Differentiation of the RAM PCB and controller PCB VMA control is achieved by creating a RAM PCB valid address signal (VMAl) via ICl on the motherboard. Bus available (BA) is brought up when the microprocessor is not performing an operation on a bus (i.e., using internal RAM). On the controller board, BA participates in the control of data buffers IC9 and IC20. The HALT line is used by the RAM PCB to inform the microprocessor it can no longer exchange data (RAM event memory protection; refer to section 3.3). Non-maskable interrupt (NMI) is connected only to PIA IC39. This line is used as a second interrupt (in addition to IRQ) for changes of inputs from the front panel switches. The RESET line is used to place the microprocessor, PTM and PIA's (both controller and Front Panel PCB's) in a reset condition. A reset is generated at power-up (+5 volts on) on the motherboard and input to the controller PCB.

The EPROM's store the interpreter's pennanent software and tables of constant data. Although the controller PCB contains sockets for eight 16K EPROMS, only four are used in the intepreter unit application. Each 16K EPROM holds 2048 bytes of 8-bit data (2K x 8 bits). At least one EPROM, installed at IC8, is required to set the reset vector address for the microprocessor. Additional EPROM's are installed in reverse numerical order (IC7, IC6 etc.) to enable proper addressing. The RAM IC's contain variable or "scratchpad" data (not pertaining to recorded event data). The eight pairs of RAM's can each hold 1024 bytes of 8-bit data.

The programmable timer module at IC37 consists of three independent timers. The normal clock rate into the timer is fixed at 9600 Hz from the bit rate generator/oscillator. Gate controls from the timers are connected to PIA 1 (IC38), which allows the timers to be started at any time.

PIA 1 also inputs to the microprocessor the state of the seven rocker switches on the DIP switch. PIA 1 is used as the driver for the four system housekeeping monitor LED's (1 through 4).

6204, p. 3-2

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MSEL8

t --

CONTROLLER PCB/RAM PCB RAM SELECT

r I TWO RAM IC'S

1024 BYTES TWO RAM IC'S

1024 BYTES

------, -I _TW_O_R-AM-1c-·s-l I TWO RAM 1c·s I I II

1024 BYTES 1024 BYTES

' I TYPICAL FOR

,... ALL RAMS I (TOTAL) I I (TOTAL) I I (TOTAL) I I (TOTAL) I I ; I I I I I I I I \ I I I I I I I

ACD ACD ACD ACD IC2 IC1 I .

I I I ~

~ I i I ·~ .. ·~ ' ~ j TWO RAM IC'S TWO RAM IC'S TWO RAM IC'S TWO RAM IC'S

I I c 1024 BYTES 1024 BYTES 1024 BYTES 1024 BYTES I • c;::_DATA 0-4 r--VMA (IN) I (TOTAL) (TOTAL) (TOTAL) (TOTAL) "') ADDRESS 14, 15 - :) VMA1 (OUT)

I I 'A CD I I I I I I I I I

ADDRESS I ACD ACD ACD I : BUFFERED DATA I : I I I

I CONTROL I

I I I I r XTAL --- ---- - .. . -1 I RAM PCB I ......... I -B I I CONTROLLER

EPROM I POWER A ~

PCB ~

.... ~ RAM 16K : I ,

BACK-UP T

1· I SELECT T ... MICRO- . ADDRESS . - I I I -~

.. PROCESSOR . BUFFERS ..

en

I I en 0 w i I a: <( I ~ FLAT RIBBON I I 0 0 I-....

I I w 0 <( . CABLE, ALL I ..

16K ~ a: <( en 0 ~ RAM w

UNBUFFERED DATA en OTHER BO TOi RAM u. w -rt I

_ _____. ~ SELECT I I

u. a: BO LINES ON I I IC'S ::, CONTROLLER 0 DECODE co PCB 0 EPROM MOTHERBOAR ~ (3) ~ ~ ~

... ~I

EPROM <( 16K

I PCB. I ..

I I <( SELECT . ~ - .. x

I I 0 DATA

I I .. T r+

I I 0 .. BUFFERS A

w L BIT a: - RATE

I I I e:: I I w GENERATOR u. ... - u.

~ i.. 16K , ::,

I l I r

RAM co MISC. RAM

i SELECT I I z r-+ PERIPHERALS EPROM ~ I I ~ ::, 16K IC's DECODE f4-- DIP SELECT

I~ ,.

I . (8) I+- I

.. SWITCH ,. .. I , .. en

..J PIA 0 ........ (NOT USED) a: I I I I I-

en ~

~, z en 0 EIA I I w ,..... LED'S (.)

DRIVERS i I a: - . ,

I I I JUMPERS ~ & REC. 0 t G.C. , ..

~ 0 <(

I+-- I .. -I I

r ,

I I I ACIA 16K RAM RAM IC'S SELECT

~ ...

CL I ~

~ ,-,-- - ... .... , I (8) DECODE I I .... .. DEVICES , I ~ .

~ .... ~ PTM .. en ·- 600 BPS I I I

..J

I 0 ~ I a: ,

I SDO I-z

I I 0 MICROPROCESSOR - I

,.. I 1 I (.) IC'S 45-49

CONTROLLER PCB ~ I 2 • ~

(NOT USED) : 3 I I I ...

E ..... ......... ~ I~ 4 I .. ~

BUFFERS , I 16K RAM RAM

I "STROBE" 5 I I .. SELECT I -~ PIA - 6 I .. IC'S ,

(5) DECODE SYSTEM DATA 7 i ,_ . ... +-- I+- I I ~ , . .

I

L __________ _J L ______ - -- _______ _J L

I JUMPER~

. r

PIA .. (DATA . PROGRAM) .. .

i

PROM SOCKET

. ... ..

PIA

UNION SWITCH & SIGNAL m

POWER CIRCUIT PROGRAM SELECT POWER

CIRCUIT POWER CIRCUIT 21 VOLT

SELECT

""" - 21 OR 25 VOLT --,

~~

I

PROGRAM

- POWER

-, I I I I

CIRCUIT ~ (ADDRESS 25 VOLT

I I I I

PROGRAM) . .

MONITOR TERMINAL RS-232C

... RS-232C .

(D-CONNECT) (D-CONNECT.) -

i a

FRONT PANEL PC

START SWITCH

SKIP SWITCH

COL. SIZE

SWITCH

MODE SW

MONITOR PROM PROS.

PRINTER

OVER-- RUN .

LED

COM-

LED r PLETE

. ERROR . LED

I I I I

B I I I

I I I I I I I I

_J

Figure 3-1. Interpreter Unit Block Diagram

6204, p. 3-3/4

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UNION SWITCH & SIGNAL m PIA 2 (IC39) is used to interface the controller board with controls and indicators on the Front' Panel PCB. The eight lines are bi-directionally buffered by the tri-state buffers at IC42 and IC43, however data on a given line, consisting of Front Panel PCB LED outputs and switch inputs, is transmitted in only one direction. IC's 45 through 49 are not used in this .application of the controller PCB, except the IC45 11RDY11 gate, which enables IC42 and 43.

The controller PCB is equipped with various plug-in and soldered jumpers. JPl is a solder-in jumper which connects the shield wire of the external interface cable to the case chassis (ground). Jumper JP2 is not used. Jumper JP3 is permanemtly installed to enable operation of the EPROM'S. Jumper JP4 selects the EIA communications mode for the interface with the external terminal. JPS selects current loop operation. One jumper is installed among the 10 JP6 sockets to fix the communications bit rate.

3.2.2 I/0 Communications Circuits

The controller PCB may communicate with an external terminal using a standard Electronic Industries Association (EIA) RS-232C serial data line. The ACIA IC40 provides the serial 1/0 for this option between the board and the external devices, via connector Jl. The line driver at IC41 converts board internal signal outputs to EIA, while the line receiver at IC44 converts EIA level data inputs back to the board internal signal level. These operate on 12 Vdc. Installing a jumper at JP4 sets up the board to EIA operation. EIA signals used by the controller board include:

RTS (Request to Send) - This is an output from the controller PCB to the terminal, requesting clearance to send data.

CTS (Clear to Send) - This is an input from the terminal informing the controller PCB that data may be transmitted.

D-OUT (Output Serial Data) - This is the data transmitted from the controller P~B to the terminal, after reception of the CTS.

DCD (Data Carrier Detect) - This is an input from the terminal indicating that the carrier has come on.

D-IN (Input Serial Data) - This is the data transmitted from the terminal to the controller PCB.

COM (Logic Common) - This is the zero volts reference for all other signals.

Snield - All EIA lines may be shielded from electromagnetic interference through this line. When solder-in jumper JPl is installed, the shield pin-out is grounded to the card file chassis. The cable shield can then be connected to this line.

6204, P• 3-5

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UNION SWITCH & SIGNAL

•I

The controller PCB may also communicate with a terminal using a 20 mA current loop; either passive or active current loop operation can be applied. If the terminal provides the power source for loop (controller PCB is passive), optical isolators are provided which separate the board electrically from the terminal. If the controller PCB must provide loop power, separate lines are available with the 12 Vdc supply on them. The controller PCB is wired at Jl for either passive or active operation. IC40 controls the data I/0 for the current loop option. Installing a jumper at JPS switches the board to this option. (DCD and CTS of the EIA option must be disabled when going to current loop operation. This is accomplished by connecting these lines to the normally-high DTR line.)

The 20 mA current loop lines include:

TX+ (Transmit +)

Active Mode - This line provides the 20 mA to power the loop for the outgoing data(+ Data Out).

Passive Mode - Not connected since the external device is powering the loop.

TX- (Transmit -)

Active Mode - This line is the 20 mA return for the outgoing data (- Data Out).

Passive Mode - With the external device powering the loop, this line is the 20 mA input for outgoing data(+ Data Out).

TXG (Transmit Ground)

Active :t,tode - This line is the ground return for the outgoing data lines (COM).

Passive Mode - This line becomes the 20 mA return for the outgoing data (­Data Out).

RC+, RC-, RCG (Receive+, Receive - and Receive Ground)

These lines are configured and operated in the same manner as the transmit lines, except that incoming current loop data from the external device is being handled. Optical couplers work in both active and passive modes.

Refer to section 2.3 for wiring of the current loop interface.

3.3 RAM PCB N45144-490X (8ee also Figure 5-2)

IG's 26 through 29 are l-of-8 decoders which select groups of RAM's for event recording and reading. Two of these decoders (IC27 and 28) control less than eight RAM's. The A, Band C inputs on each decoder are the tri-state addressing inputs from the microprocessor on the controller PCB. STR (Start RAM) enables the decoders at the actual start of data. In addition to address, data and the R/W control line, each RAM is provided a chip-enable from an adjacent NAND gate. A RAM IC will be enabled by this gate when its respective decode line is high and the HALT line is high. The HALT line

t,l204, p. 3-6

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UNION SWITCH & SIGNAL m provides a clearly defined RAM disable when external power to the board is disconnected or falls below specification. The circuits accessible on TP2 through TP5 make up a two-stage power contingency circuit to protect memory in the RAM chips. If the power provided by the power supply converter PCB falls below 4.7 volts, IC25 (prograunnable voltage reference) pulls the HALT line high via Ql. IC25 is intended to insure that all RAM's are properly disabled. IC25 is calibrated by potentiometer Rl3, an includes a turn-on hysteresis transition to 4.9 volts when power comes back up towards normal.

Between 4.7 and 3.3 volts, all components will continue to be powered by externally supplied voltage, although no data flow occurs since the RAM's are disabled. If input voltage falls below the 3.3 volt limit of Zener diode D2, Q2 and Q3 no longer switch power into the board. This, in turn, allows DJ to conduct the 3.68 volt power from the lithium battery. In this manner, data already present in the RAM's is preserved during the power-down period.

Table 3-1 contains the hexadecimal and decimal RAM addresses for all locations on the RAM PCB.

Table 3-1. RAM PCB, RAM IC Hexadecimal and Decimal Addresses

Decode IC RAM. IC Hexadecimal Address Decimal Address

IG28 24 DOOO to D7FF 53248/57343 II 23 C800 to CFFF 51200/53247 II 22 cooo to C7FF 49152/51199 II 21 B800 to BFFF 47104/49151

IC26 20 BOOO to B7FF 45056/ 4 7103 II 19 A800 to AFFF 43008/45055 II 18 AOOO to AFFF 40960/43007 II 17 9800 to 9FFF 38912/40959 II 16 9000 to 97FF 36864/ 38911 II 15 8800 to 8FFF 34816/36863 II 14 8000 to 87FF 32768/34815

IC29 13 7800 to 7FFF 30720/32767 I 12 7000 to 77FF 286 72/ 30719

11 6800 to 6FFF 26624/28671 . 10 6000 to 67FF 24576/26623

9 5800 to 5FFF 22528/24575 8 5000 to 57FF 20480/22527 7 4800 to 4FFF 18432/20479

I 6 4000 to 47FF 16384/18431 IC27 5 3800 to 3FFF 14336/16383

II 4 3000 to 37FF 12288/14335 II 3 2800 to 2FFF 10240/12287 II 2 2000 to 27FF 8192/10239 II 1 1800 to lFFF 6144/ 8191

6203, P• 3-7/8

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U".'ION SWITCH & SIGNAL

SECTION IV TROUBLESHOOTING AND MAINTENANCE

4.1 GENERAL

Routine corrective maintenance on the Eventtrak Interpreter consists of repairing and/or securing various internal wiring and PCB component connections, and replacing faulty PCB's with spares. Faulty PCB's should be returned to US&S for repair or replacement. To obtain the proper Returned Material Report (RMR) form, contact the US&S district sales representative.

Different test equipment set-ups are used for each of the interpreter unit PCB's. The Microprocessor controller PCB requires the US&S TS-301 test set, which performs software-controlled diagnostics on the principle components and circuits of the board. The test software is carried in a diagnostic PROM, which is substituted for one of the service EPROMS on the board (other EPROMS removed). The RAM PCB test procedure requires a functional Eventtrak Monitor unit, diagnostic PROM's for the monitor unit microprocessor PCB and a CRT computer terminal which displays procedural steps and results. General purpose test equipment is used for troubleshooting of the Front Panel, motherboard and power supply PCB's.

Possibly faulty components and lines are listed for all PCB tests. The maintainer is responsible for following up the written test procedures with standard component performance and circuit continuity tests.

4.2 MICROPROCESSOR CONTROLLER PCB (N451208-0106'

4.2.1 Required Test Equipment

Device

US&S TS-301 Test set (with one test PROM).

US&S MICR0-700 controller PCB Test PROM (Qty.=l)

Multimeter (Qty.=l), suggested models: Simpson 260, Fluke 8000A)

Specifications

N451400-2401

N451575-0314

Voltmeter: DC voltage range: 0 to 50 Input resistance: 20K ohm/vdc Accuracy: +/- 2% tolerance

for 5 and 12 vdc ohmmeter resistance range:

O to 20 M Ohmmeter accuracy: +/- 5%

reading at center scale

6204, p. 4-1

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m UNION SWITCH & SIGNAL

Frequency Counter (Qty.=l, suggested models: Hewlett-Packard 5300, 5302)

Connecting Leads (Qty.=l, suggested brand: Pomona 3738-C-18

4.2.2 Test Set-Up

1. Disconnect interpreter unit 110 Vac power.

Frequency range: 100 Hz to 5.0 MHz. Five digit resolution@ 5.0 MHz Input impedance: 1 megaohm

(30 pf max. cap.)

Hooked end/BNC male

2. Remove the two (of six) front panel machine screws closest the case hinge, and the two lock pins closest the case handle.

3. Remove the card enclosure from the case.

4. Pull the Microprocessor Controller PCB part way out of its case slot (middle), disconnect the flat ribbon cable on the PCB, then remove PCB from the case.

CAUTION

DO NOT REMOVE OR INSTALL THE MICROPROCESSOR CONTROLLER PCB WITH INTERPRETER UNIT POWER ON, OTHERWISE COMPONENT DAMAGE MAY RESULT.

5. With multimeter adjusted to the R X l scale, connect "+" lead to Z of connector edge J2 and the"-" lead to pin A of the connector. Tbe meter should show a resistance not less than 2 ohms. If this test fails (shorted track in power bus or shorted component indicated) do not proceed any further with test procedure. The board should be replaced.

6. Remove all service EPROM's from the board; check that each is tagged with its IC number to insure proper relocation after the test procedure.

7. With TS-301 power turned off, remove the test EPROM in storage on the set and install it in IC8 on the controller board.

CAUTION

DO NOT REMOVE OR INSTALL THE TEST PROM ON THE TS-301 TEST SET WITH POWER ON, OTHERWISE COMPONENT DAMAGE MAY RESULT.

8. If not already installed, place four jumpers in socket JP2.

9. Push in the actuator knob on the test set and insert the board in the edge connectors. Jl/J2 of the board and the test set should correspond; the component side of the board faces the test set control panel.

b204, p. 4-2

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UNION SWITCH & SIGNAL El:)

10. Connect the J3 ribbon cable on the test set to the J3 plug (microprocessor bus) on the board. The cable should not have any twists once installed.

11. Place the TS-301 test mode switch to the PCB position.

4.2.3 Test Procedure Comments

The Microprocessor Controller PCB test procedure is arranged to call upon a larger portion of the board with each test; the latter tests cannot be confirmed unless key components and circuits, checked in the earlier tests, are working properly. US&S recommends that the procedure be followed in its entirety, unless it is definitely known before hand which logic areas of the board are responsible for the problem.

Following is a breakdown of the procedure and the reasoning behind the specific steps. If the maintainer elects to troubleshoot only one area of the board he should review the following descriptions to determine which intermediate step to begin with:

1,2

3-5

6-8

NOTE

St~ps 47 through 63 cover some components which are not used in interpreter unit operations. (Inactive components include sections of IC's 45 through 49 on the output of PIA 2 (except the IC45 RDY gate and IC46 STROBE buffer), and the two sections of IC46 on the output of PIA 1.) These steps should be carried out in full. The terms G-IN, G-OUT, RDY, BREQ, STROBE, ACK and MSG are retained in the test procedure description to facilitate use of the TS-301 and the controller PCB schematic; they are not relevant to interpreter unit operation.

Description

Before running any components through functional tests, the central power bus is checked to verify continuity of current to the board.

The condition of the 4 MHz clock into the microprocessor and the 1 MHz from its oscillator is critical to the operation of the chip and other components checks. Steps 3 and 4 check both frequencies off the microprocessor. Because the frequency counter is already set up, the ACIA baud rate reference frequencies are also checked in Step 5, however, these tests are not crucial to subsequent tests until Step 39.

This is a check of the general controller PCB reset function; the TS-301 supplies the reset signal in the same manner as the reset line from the motherboard. This test must be passed since the board is reset frequently in subsequent tests. To facilitate location of the faulty component(s) some components which do not participate in the reset are temporarily pulled off the board.

6204, p. 4-3

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m UNION SWITCH & SIGNAL

9-11

12, 13

14, 15

16-21

22-27

28-31

32-38

6204, p. 4-4

This is a similtaneous check of the address decode logic for the main microprocessor bus, and of the test set's ability to input different test codes and read responses from the controller PCB.

This is the specific test of the microprocessor chip (4 MHz clock into the chip operating properly). The rotating LED pattern on the test set indicates a comprehensive internal test routine which is being run by the test PROM. The test repeats itself until a reset is called.

These steps check the operation of the controller PCB read/write memory in the RAM's. The four high switches on the test box are put through a "walking ones" test which check out the RAM pairs. An incorrect data bit or bits will show with the corresponding test box lamp going off periodically out of sequence with the other lamps.

The controller PCB EPROM locations are checked in these steps. Since the main test PROM must be kept in IC8, a second test PROM is used to checkout the remaining locations (including those not used in interpreter unit operation). The four high switches on the test set specify the EPROM location. A checksum is displayed on the test box LED's which matches the checksum taken when the test PROM itself is checked on the test box.

These steps check the operation of the three parts of the programmable timer module. The accuracy of the timers is checked against the microprocessor 1 MHz clock. Two of the four high switches on the test set select which of the three timers is to be tested. The test set LED's display the difference, in binary, between the actual and calculated values. A display of zero (all LED's off) indicates perfect accuracy while a display with all LED's on indicates the greatest deviation. The displayed value should be a binary 3 (LED's 1 and 2 on only) or less to qualify the timer.

PIA-1 is checked via its "A" register in this procedure. This is the first test which makes use of DIP switch SWl on the board. Since there are only seven rocker switches available on SWl and PA7 of PIA-1 (ACK line) must also be checked, the first part of the procedure sets up certain LED's on the test set to flash (flash rate provided by the test software) indicating proper functioning of that line. The DIP switch rockers then check the states of the PAO through PA6 with rocker position corresponding to test set LED display.

The "B" register of PIA-1 part1.c1.pates in this test, which also involves the controller PCB LED's and the PTM timers. With test set Switch 7 thrown on, the timers are gated by the PIA outputs and a rotating pattern is generated on both the test set LED's and the first four of the board LED's. When Switch 7 is thrown off, the gates to the timers are turned off, as indicated by stopping of the rotating LED patterns. The test is repeated through the other timers, resulting in increased rotation flash rate.

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39-46

47-50

51-61

62, 63

UNION SWITCH & SIGNAL m This procedure checks the ACIA transmit and receive buffering. First, a bit rate and serial data mode option are selected. Then the SWl rockers are set to create a bit value. The received bit value indicated on the test LED's should match the DIP switch. Both the serial data mode and bit values are changed for reruns of the tests.

The IC48 and 49 flip-flops, and adjacent IC45, 47 and 47 gates/buffers are checked in these steps. The bit switches on the test box are cleared so that the board is idle as far as external communications are concerned. Throwing the G-IN switch on the set simulates a high input on the G-IN line. Since no communications are occuring, the board should place a high output on G-OUT, which the test set shows as an illuminated LED.

These steps checkout PIA-2, which interfaces Front Panel PCB data. DIP switch SWl is used here to simulate switch inputs from the Front Panel PCB. The first time G-IN is set low (after the board is reset), the board should place BREQ high. Alternate rockers on SWl are closed; when G-IN is then set high, PIA-2 now has a message to transmit which shows up as an alternating LED display and a G-OUT indication. When G-IN is set low again, the test set will continue to show the message, but the board will only output a BREQ again. The procedure is repeated with the SWl rockers reversed.

The last steps in the procedure checkout the MSG and STROBE lines which complement the data output. The test software checks the individual control lines in a manner resulting in alternating flashing of the MSG and STROBE LED's on the test set. In actual operation, MSG goes low first, holds low through the start and stop of the STROBE pulse, then goes back high.

In the tests of specific components, the 0-3 switches on the test set provide the code which directs the test PROM to a specific part of the board. The remaining switches are periodically used to refine the checks within that part. Any toggle set to the up position (towards "TS-301" label) sets the corresponding line to a high or logic 11111 state and vice-versa when set to the down position. When the letter "X" appears in a switch listing, the toggle can be in either position since it does not participate in the test. When a rocker on DIP switch SWl is set to the OPEN side, the circuit is off and a logic "1" is generated and vice-versa for the closed position. Throughout the procedure, the PCB/PROM switch is set to the PCB side. PROM is pnly used when checking the test PROM itself in the test set (SM-6219).

6204, P• 4-5

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ONION SWltCH & SIGNAL

4.2.4 Procedure

Operation

1. Place toggle 1. switches O through 7 and the G-IN toggle in the logic "O" (down) position.

2. Place the POWER 2. toggle switch on the set on.

3. Connect ground 3. lead of frequency counter to TPl and apply probe lead to pin 37 of IC36.

4. Move probe lead 4. of counter to pin 38 of IC36.

5. Move probe lead 5. of counter to the following socket pins of jumper JP6 on the Controller PCB:

11 12 13 14 15 16 17 18 19 20

6. Turn off test set 6. and carefully remove the following IC's from the Controller PCB.

IC 1 - 7 IC12 - 19 IC23 - 30 IC37 - 40

6204, p. 4-6

Verification

POWER LED should light.

Counter should show 4.0 MHz,+/- .05%.

1.0 MHz,+/- .05%.

Counter should show the following fre­quencies (KHz), +/- .05%:

1.2 1. 7588 2.4 4.8 9.6

19.2 28.8 38.4 76.8

153.6

Possible Problem Area

1.

2.

3.

4.

5.

6.

Check for blown fuse on test set (caused by a short in the power bus of the Controller PCB).

Check XTAL 1 and capacitors C52, C53, and IC36.

Check IC36.

Check XTAL 2, IC50 and R27 where any frequency is out of spec. Check also Rl4 and/or C56.

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Operation

7. Turn test set power 7. back on and press the test set RESET pushbutton for several seconds, then release it.

8. Turn off test set and reinstall the IC' s which were removed in Step 6.

9. Turn test power back on and check that 0-7 toggle switches are down; press the RESET switch.

8.

9.

UNION SWITCH & SIGNAL El)

Verification Possib.le Problem Area

All LED's on the Con- 7. troller PCB and the test set should go out (except for test set POWER) when RESET is released.

8.

9.

If any LED remains on after RESET is released, check the following:

(a) IC8 for shorts or opens on the address, data, select and power lines.

(b) IC36 pins 2, 3, 4, 6, 8, 35, 36 for a logic "l" (3.9 vdc + I - 1. 2 vdc ) •

(c) IC36 pins 1, 7 and 21 fdor a logic "O" (.25 vdc, +/- .25 vdc).

(d) IC's 9, 20, 31, 32 and 33: buffer output should follow input when enabled.

(e) IClO: address decode output PSEL8 should go to logic "O" for every MPU "read" from the test set PROM IC8.

(£) IC's 28, 34, 35, 46, 47, 48, and 53.

6204, P• 4-7

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m UNION SWITCH & SIGNAL

Operation

10. Starting with toggle switch 7, place each of the 0-7 switches in the up {logic 11111

) position, in sequence, until all switches are up.

Verification Possible Problem Area

10. LED adjacent to each 10. Check IC22. switch should come on as each switch is thrown.

11. Starting with 11. LED adjacent to each switch should go off as each switch is thrown.

11. Same as Step 10. toggle O, place each of the 0-7 switches back in the down (logic "O") position, in sequence, until all switches are down.

12. Set test boK switches O - 7 as follows:

Switch Logic

0 1 1 0 2 0 3 0 4 x 5 x 6 x 7 x

13. Press, then release the RESET release button.

6204, p. 4-8

12.

13. 0-7 LED's will appear to sequence from the ends of the string (0 and 7) towards the middle (3 and 4) in a rapid, repeating pattern. The exact rotation is:

Pattern LED's No. ON

1 0,7 2 1,6 3 2,5

4 3,4 5

LED's Off

1-6 0,2-5,7 0,1,3,4

6, 7 0-2,5-7 0-7

12.

13. If rotation stops and two LED's remain lit steadily, check IC36.

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UNION SWITCH & BIGNAb m Operation Verification Possible Problem Area

14. Set the test box 14. When last toggle is 14.

15.

16.

switches as follows: thrown all test LED's should light simil­taneously for about two seconds, go off briefly, then light again for two seconds, pattern repeats.

Switch Logic

0 0 1 1 2 0 3 0 4 0 5 0 6 0 7 0

Keeping switches O, 15. When the last toggle 1, 2 and 3 in the in each series is above positions, thrown, all LED's reset switches 4, 5, should stay dark for 6 and 7 as follows: about two seconds,

flash on briefly, then Switches go off again for two

7 6 5 4 seconds; pattern repeats.

(a) 0 0 0 1 (b) 0 0 l 0 (c) 0 0 1 1 (d) 0 1 0 0 (e) 0 1 0 1 (f) 0 1 1 0 (g) 0 1 1 1 (h) 1 0 0 0

Set the test box 16. When the last toggle switches as is thrown, LED's 1,3, follows: 5 and 7 should light

steadily. All other Switch Logic LED's should be off,

except test set POWER. 0 1 1 1 2 0 3 0 4 0 5 0 6 0 7 1

15. An LED which stays on during the two-second "dark" interval indi-cates a faulty RAM chip or a bad data line on the PCB. Check RAM pairs:

(a) IC' s 19 and 30 (b) re's 18 and 29 (c) re's 17 and 28 (d) IC's 16 and 27 (e) IC' s 15 and 26 (f) IC's 14 and 25 (g) re's 13 and 24 (h) IC's 12 and 23

16. If any variance from this pattern occurs, check:

(a) Test PROM (b) Connections to test

PROM (IC8) (c) IC's 10,35 and 53

6204, p. 4-9

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m UNION SWITCH & SIGNAL

Operation

17. Turn test set POWER off.

18. Insert a second test PROM (N451575-0314) in socket IC7 of the controller PCB.

19. Keeping switches 0,1,2 and 3 set per Step 16, re­set switches 4,5, 6, and 7 as follows:

Switch Logic 4 1 5 1 6 1 7 0

20. Turn test set POWER on.

21. Repeat Steps 17 through 20, in each case re­locating the second test PROM in the different PROM sockets. Reset test box switches as follows for each new PROM location:

2nd Test PROM Switches

In 7 6 5 4

IC6 0 1 1 0 res 0 1 0 1 IC4 0 1 0 0 IC3 0 0 1 1 IC2 0 0 1 0 ICl 0 0 0 1

6204, p. 4-10

Verification

17.

18.

19.

20. Same results as in Step 16.

21. Same results as in Step 16.

Possible Problem Area

17.

18.

19.

20. Check same components as in Step 16, however check IC7 socket connections.

21. Check same components as in Step 16, however check the corresponding socket connections for each new IC socket taking the second test PROM.

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Operation

Make certain test box power is turned OFF betore repeating the second test Pk.OM. Leave POWER off at end of tests.

22. Set test box switches as .tollows:

Switch Logic 0 0 1 0 2 1 J 0 4 1 5 0 6 x 7 x

23. Turn test set POWER switch on.

24. Keeping switches 0,1,2, and 3 set per Step 22, reset switches 4 and 5 as .toilows:

Switcn Logic 4 0 ) 1

2:>. Press, then re-lease the llli~EI pushbutton.

20. Reset switches 4 and s as .tollows:

switch .Logic ---4 1 5 1

27. Place switches 1-7 ot DIP switch 1:.iW 1 on the Con­troller PCB to the closeo position.

23.

24.

l5.

26.

27.

UNION SWITCH & SIGNAL m Verification Possible Problem Area

22. 22.

LED's 1 and 2 should 23. Check IC37. both be on steadily, only one on steadily, or both off. All other lliU Is (except POWER) should be off.

Same results as in 24. Same checks as Step 23. Step 23.

25.

Same results as in 26. Same checks as Step 23. Step 23 •

'/.7.

6204, P• 4-11

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m UNION SWITCH & SIGNAL

Operation

28. Set test box 4 switches as follows:

Switch Logic 0 1 1 0 2 1 3 0 4 x 5 x 6 x 7 x

29. Press, then release the RESET pushbutton.

30. Set rockers 1, 3 5 and 7 of DIP switch SWl on the Controller PCB

31.

32.

to the OPEN position.

Reset DIP switch rockers 1, 3, 5 anq 7 to the closed position and 2, 4 and 6 to the OPEN position.

Set the test box switches

Switch 0 1 2 3 4 5 6 7

as follows:

Logic 0 1 1 0 1 0 x 1

6204, P• 4-12

Verification

28.

29. The ACK and #7 LED's should flash on and and off similtaneously at about one second. intervals. All other LED's (except POWER) should be off.

Possible Problem Area

28.

29. Check IC's 38 and 53, SWl and RNl.

30. LED's 0,2,4 and 6 on 30. Check SWl, RNl and IC8. the test set should

31.

32.

be lit steadily. LED's ACK and 7 should con­tinue to flash at one second intervals while all other LED's remain off.

LED's 1,3,5 and 7 on the test set should be lit steadily. LED's ACK and 7 should con-tinue to flash at one second intervals.

31. Same check as in Step 30.

32.

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Operation

33. Press then release the RESET push­button.

34.

35.

36.

Set switch t/:7 on the test to the down (logic "O") position.

Set switch t/:7 back to the up position.

Keeping switches 0,1,2 and 3 set per Step 32, re-set switches 4 and 5 as follows:

Switch 4 5

Logic 0 1

37. Repeat Steps 34 and 35 per the Step 36 switch settings.

UNION SWITCH & SIGNAL m Verification Possible Problem Area

33. Test set LED #7 lights first, followed se­quentially by LED's 6,5,4,3,2,1 and O until all LED's are lit. Then LED #7 goes off, followed sequen­tially by LED's 6,5,4 3,2,1 and O until all LED's are off. LED #7 lights again and the sequence is repeated.

33. Check IC's 37,38,53 and LED's 1 through 4 on the board.

When LED #7 first lights, LED #1 on the Control-ler PCB also lights, fol­lowed by LED's 2,3 and 4 in the same kind of pattern as the LED's on test set. The PCB LED's also go out in these­quential pattern and then repeat. The two rotations are not synchronized. All other LED's (except POWER) should stay off.

34. Rotating patterns 34. Check IC38. on the test set and board LED's are halted.

35. Rotating patterns on 35. the test set and board are restored.

36. Same rotating pat­terns obtained as in Step 33, except at a faster rate.

36. Check IC's 37 apd 38.

37. Same patterns as in Steps 34 and 35 at faster rate.

37. Same check as in Step 34.

6204, P• 4-13

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m UNION SWltCH & SIGNAL

Operation

38. Keeping switches 0,1,2 and 3 set per Step 36, re­set switch /fa4 to the up (logic 11 111

)

position.

39. Set the test box switches as follows:

Switch 0 1 2 3 4 5 6

Logic 1 1 1 0 x x x

40. Install a jumper at the JP6 2400 location on the Controller PCB.

41. Install another jumper at JP4.

Verification

38. Same rotation pat­tern obtained as in Step 33, but at a rate faster than that obtained in Step 36.

39.

40.

41.

42. Place rockers 42. 1,3,5 and 7 of DIP switch SWl (on board) to the closed position and 2,4 and 6 to the OPEN position.

43. Press, the release the RESET push­button.

6204, p. 4-14

43. LED's 1,3 and 5 on the test set will be lit steadily, LED's 7 and ACK should flash on and off similtan­taneoµsly at about one second intervals. All other LED's (except

POWER) should be off.

Possible Problem Area

38. Same checks as in Step 36.

39.

40.

41.

42.

43.Check IC's 40,41 44 and 47.

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Operation

44. Reset rockers 2,4 and 6 of DIP switch SWl to the closed position and 1,3,5 and 7 to the OPEN position.

45. Remove the jumper at JP4 and place it in JPS on the board.

46. Repeat Steps 42 through 44.

47. Set 0-7 switches on the test set to the down ( logic "O") position.

48. Press then re­lease the RESET pushbutton.

49. Place the G-IN switch on the test set in the up ( logic "l")

50. Reset the G-IN switch to the down ( logic "O") position.

51. Reset the G-IN switch back to the up (logic 11111

)

position.

44.

45.

Verification

LED's O, 2, 4 and 6 on the test set will be lit steadily. LED's 7 and ACK should flash on and off at about one second intervals. All other LED's (except POWER) should be off.

46. Same results obtained as in Steps 42 through 44.

47.

48.

49. The G-OUT LED on the test set and the grant LED (#5) on the Con­troller PCB should both light steadily. All other LED's (except POWER) should be off.

50. All LED's (board and test set) should be off, except the POWER LED.

51.

UNION SWITCH & SIGNAL ffi Possible Problem Area

44. Same checks as in Step 43.

45.

46. Check IC's 40,46,47,51 and 52.

47.

48.

49. Check !C's 39,45,46,47 48 and 49.

50. Same checks as in Step 49.

51.

6204, P• 4-15

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m UNION SWITCH & SIGNAL

Operation Verification Possible Problem Area

52. Set the 0-7 switches on the test set as follows:

Switch 0 1 2 3 4 5 6 7

Logic 1 0 0 1 x x x x

53. Press, then re­lease the RESET pushbutton.

54. Reset the G-IN switch to the down ( logic 11011

)

position.

52.

53.

54. The BREQ LED on the test set should light steadily. All other LED's (except POWER) should be off.

55. Check that DIP 55.

56.

switch SWl rockers are set per Step 44.

Set the G-IN switch to the up ( logic 11111

)

position.

57. Reset switch G-IN to the down ( logic 11011

)

position.

56. LED's 0,2,4,6 and G-OUT on the test set, and the grant LED on the board (LED #5) should come

57.

on steadily. All other LED's (except POWER) should be off.

58. Reset DIP switch 58. LED's 0,2,4,6 and BREQ on the test SWl rockers 1,3,5

and 7 to the closed position and 2,4, and 6 to the OPEN position.

6204, p. 4-16

set should come on. All other LED's (except POWER) should be off.

52.

53.

54. Same check as in Step 49.

55.

56. Check IC's 39,42 and 43.

57.

58. Same checks as in Step 49.

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Operation

59. Reset G-IN to the up (logic 11 111

)

position.

60. Repeat Step 59.

61. Reset G-IN to the down ( logic 11011

)

position.

62. Set the 0-7 switches on the test set as follows:

Switch 0 1 2 3 4 5 6 7

Logic 0 1 0 1 x x x x

63. Press, then re­lease the RESET pushbutton.

Verification

59.

60. LED's 1,3,5 and G-OUT on the test set and the grant LED on the board (#5) should come on steadily. All other LED's (except POWER) should be off.

61. LED's 1,3,5 and BREQ on the test set should come on. All other LED's (except POWER) should be off.

62.

63. MSG and STROBE LED's on the test set should flash on and off alter­nately. All other LED's (except POWER) should be off.

UNION SWITCH & SIGNAL m Possible Problem Area

59.

60. Ch~ck IC's 39,42 and 43.

61. Same checks as in Step 49.

62.

63. Check IC's 39 and 46.

6204 , p. 4-1 7

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ffi UNION SWITCH & SIGNAL

4.3 RAM PCB (N451441-4905)

4.3.1 Required Test Equipment

Device Specifications

Eventtrak. Monitor Unit Must be equipped with a microprocessor PCB and power supply converter PCB (min.)

Computer Terminal (Qty= 1, RS-232C input, capable of 9600 baud Recommended model: Digital Equipment Corp. VTlOO)

Eventtrak. Monitor Unit Test PROM Set US&S N451575-0702, N451575-1004, N451575-1005

Volt-Ohmmeter (Qty= 1, Recommended models: Simpson 260, Fluke 800A)

Voltmeter: de

Voltage range: 0 to 50 volts

Input resistance: 20K ohm/volt

Voltmeter accuracy: +/- 2%

Ohmmeter resistance range: 0 to 20M

Ohmmeter accuracy: +/- 5% reading at center scale

4.3.2 Test Set-Up

1. Disconnect interpreter unit 110 Vac power.

2. Remove the two (of six) front panel machine screws closest the case hinge; and the two lock pins closest the case handle.

3. Remove the card enclosure from the case.

4. Pull the RAM PCB from its case slot.

t>204, P• 4-18

Note

Once the RAM PCB is out of the case, it should be stood in the same position in norlJ)ally has in the card file, especially if it is to left out of the file for an extended period of time. If the board is laid in a different position, the life expectancy of the lithium battery will be reduced. This recommendation also applies to the RAM which is temporarily removed from the monitor unit (refer to step 10).

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UNl<lfll SWITCH l SiCNALo m CAUflON

DO NOT REMOVE OR INSTALL THE RAM PCB PCB WITH INTERPRETER UNIT POWER ON, OTHERWISE COMPONENT DAMAGE MAY RESULT.

5. Construct monitor unit/terminal connector/cable assembly according to Figure 4-1.

6. Remove monitor unit card file front cover and attach computer terminal to the D connector. Terminal should be set to 9600 baud and turned off.

7. Remove monitor unit microprocessor PCB (power off), place a jumper in socket J3 (sets monitor unit bit rate at 9600 baud) and jwnpers in JlO and Jl2 (EIA mode to terminal).

8. Replace service EPROM's IC23, IC24 and IC25 with test PROM's (the test PROM's are tagged with the designated IC socket nwnber).

9. Reinstall microprocessor PCB in its card file slot.

10. Remove existing RAM PCB from the monitor unit card file (power off) •

....,I .. -----LENGTH AS REQUIRED-----t ...... l MONITOR UNIT TERMINAL

r--, r--, EIA DATA OUT )l'll-.....;2;;.._---11---------------+l---3 --11~)

EIA DATA IN ~ 3 I I 2 I>

COMMON )I 7 I I 7 I)

EIACTs@8

I I EIA DCD REQUIRED FOR MPU, RAM AND I I

o OPTO-ISOLATOR PCB TESTS I I EIA DIR (+12V) I

L--~ L __ ~ Figure 4-1. Eventtrak Monitor Unit/Terminal Cable

4.3.3 Test Procedure Comments

The RAM PCB test procedure is divided into two parts. The first part verifies the basic operating condition of the board in preparation for tests of the RAM IC's themselves.

In step 1, a basic continuity check is performed on PCB circuits. This test is performed with the board outside of the monitor unit card file to prevent false continuity readings from the card file motherboard.

In step 3, the power-up reset of the monitor unit causes the EPROMS to conduct a rapid check of lines and peripherals. The primary PCB test selection menu also appears on the terminal at this time.

6204, p. 4-19

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UNION SWITCH & SIGNAL

The second part of the RAM. PCB test consists of the terminal-supervised test. The terminal displays a menu showing the different RAM storage capacities, according to PCB part number. The user must be careful to select the maximum RAM. capacity test (48K). The test program cannot determine the memory capacity. If a too-small capacity is selected, not all melll?ry will be checked.

The test program expects single-character answers to its prompts. If two or more characters are entered, pressing the RETURN key on the terminal has no effect. If this happens, press RETURN a second time and the terminal will request a response again.

Two modes of operation are provided: CRT and hard-copy. The CRT mode is for video terminals and hard-copy is for printer terminals. CRT mode is the default, and following a reset, the unit comes up in this mode. To switch between modes, enter CTRL-P (hold down the terminal's CTRL key and press P.) This echos as Panda message is displayed indicating which mode is active.

Note

Do not attempt any tests on the power contingency circuit on the RAM. board. This circuit is care­fully calibrated at the factory to protect RAM memory should external power fall below specifica­tion. If the power contingency circuit is thrown out of calibration, some or all data in RAM memory may be garbled or erased when power is lost.

4.3.4 Procedure

Operation

1. With V.O.M adjusted 1. to the RX 1 scale, connect "+" lead to TP2, 11

-11 lead to TPl

and measure continuity.

2. Install interpreter 2.

3.

RAM PCB in the mon­itor unit RAM. PCB slot (make certain power is off) •

Turn on mou~tor unit 3. and computer terminal power.

6204, p. 4-20

Verification

Resistance should be 1. equal to or greater than 2 ohms.

2.

Hexadecimal display on 3. MPU stand-off PCB should show "FF" briefly, then "OO" steadily. The test menu should appear on the computer terminal, as shown below:

Possible Problem Area

Shorted track in power bus or shorted component (IC, capacitor etc.)

See section 6.2.1.4, step 10.

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Operatiott

l!:VENTTRAK TEST PROGRAM.

1. PRO<.:ESSOR OOAiID

l. INPUT OOA&J

3. RAM. BOARIJ

TEST UESIRED1

4. Select Lest No. 3 4. by entering 11311

,

1.

2.

J.

4.

then pressing the RETURN or ENTER key.

EVENTTRAK RAM. BOARD

12K (UN451441-4902)

24K (UN -4903)

36K (UN -4904)

48K (UN -4905)

TEST DESll{ED?

TEST

Verification

Terminal should provide the following display:

::>. Select the 48K RAl.•1 test.

5. The program will list 5. each RAM chip number as it is tes teci., and whether it passed or failed.

uN,oh SWITCH. SIGNAL ~ Possible Pr~blem Al'aa

Indicated RAM chip, associated tracks or support circuitry.

6204, P• 4-21

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m UNIO,,. l\v1TtH & slCNAL

4.4 FNONT PANEL PCB (N451441-5201)

4.4.l Recommended Test Equipment

llevice

Volt-Ohmmeter (Qty= 1, Recommended models: Simpson 260, Fluke 800A)

Power Supply (4ty = 1, recommended models: HP6200B, HP6227B)

Power Supply (Qty= 1, recommended models: HP6200B, HP6227B)

4.4.2 Test Set-Up

Specifications

Voltmeter: de

Voltage range: 0 to 50 volts

Input resistance: 20K ohm/volt

Voltmeter accuracy: +/- 2%

Ohmmeter resistance range: 0 to 20M

Ohmmeter accuracy: +/- 5% reading at center scale

5 Vdc @ 1. 5 amps

30 Vdc@ 1.5 amps

1. Disconnect interpreter unit 110 Vac power.

2. Kemove the two (of six) front panel machine screws closest the case hinge, and the two lock pins closest the case handle.

3. Kemove the card enclosesure from the case.

4. Kemove the nuts and screws which secure the various toggle switches, the two 25-pin connectors and the 3-pin power plug. Remove the fuse holder also.

5. Kemove the four remaining machine screws (left and right) on the panel and carefully lift panel. Lift the EPR.OM sockec lever up so that the panel clears this device without damage.

b. Pull the PCrl from its motherboard connectors.

CAUTION

!JU NOT lIBMOVE UK INSTALL THE FRUNT PANEL PCB WITH 11-IT~KPRETEK UNIT POWER ON, OTHERWISE COMPONENT vAMAl.;E MAY lIBSULT.

7. t:arefully reassemble the switch and plug components.

ol04, P• 4-22

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4.4. 3 Procedure

Operation

1. Adjust VOM to the K X 1 scale.

1.

2.

J.

4.

s.

6.

7.

8.

<.;onnect VOM "+" lead 2. to TP4 and "-" lead to TPS and measure continuity

Move VOM "+" lead to 3. TP6 and measure continuity.

H.emove IC3 and IC4 4. from their sockets.

Connect 5 Vdc supply 5. +5V to TP4 and OV to TPS (make certain power is off before making connections).

Adjust VOM to 50 Vdc 6. range.

Connect VOM. "+" lead 7. to 11+11 terminal of Cl,

.. _ .. lead to "-"

terminal of Cl.

Move VOM "+" lead to 8. "-" terminal ot <.;2 and"-" lead to"+" terminal of C2.

Y. Turn off +5 Vdc 9. supply.

10. Connect 30V lead of 10. JO Vdc supply to 11+11

terminal of Cl2 and OV lead to "-" terminal of Cl2.

li. Turn on 5 Vdc supply 11. tnen 30 Vdc supply.

UNION SWITCH It SIGNAL. m Verification Possible Problem Area

1.

Resistance should be 2. equal to or greater than 2 ohms.

Resistance should be 3. equal to or greater than 2 ohms.

4.

5.

6.

Meter should snow 12 Vdc 7. +/- 0.5 Vdc.

Meter should show 12 Vdc 8. +/- 0.5 Vdc.

9.

10.

11.

Shorted track or component on 5 volt power bus (IC, capacitor etc.)

Shorted track; reg­ulators ICl, IC2 and related components.

IC8, Cl

IC8, C2

12. Connect VOM 11+11 lead 12. Meter should show O Vdc. 12. IC6, IC7 to 'f Pll and "-" lead to "-" terminal of Gl2.

6204, P• 4-23

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m UNIOrf SWITCi-1 & liGIIIAL

Opet"i:Jtion

13. Contlect a JUlllper wire betweeh TP16 and the 11

-11 terminal

of ClO.

Verificatio11 Possible Problem Area

13. Meter should snow 25 vdc. 13. If meter sho~s less than 20 or greater than 30: IC6, !Cl or related circuits.

14. If meter is in 20 to 14. Meter should show 25 Vdc. 14. ICl or related 30 Vdc range, but circuitry. not 25 Vdc, adjust K20 to obtain proper reading.

15. Remove jumper wire from TP16.

15. Meter s11ould show O Vdc. 15.

lb. Reconnect the jumper 16. Meter should show 21 Vdc. 16. wire between TP17

If meter shows less than 20 or greater than 30 :· IC 7, IC2 or related 'circuits.

and the 11-

11 terminal of ClO.

17. If meter is in 20 to 17. Meter should show 21 Vdc. 17. IC2 or related 30 Vdc range, but circuitry. not 21 Vdc, adjust R29 to obtain proper reading.

18. Remove jumper wire 18. Meter should show O Vdc. 18. fromt TP17.

19. Turn off 5 Vdc and 19. 19. 30 Vdc supplies and r~move all connecting wires.

20. Reinstall IC3 and IC4.

4.5 POWER SUPPLY PCli N451204-2901

4.5.1 Recommended Test Equipment

Device

Volt-Ohmmeter (Qty= 1, Recommended models: Simpson 260, Fluke 800A)

6204, P• 4-24

Specifications

Voltmeter: de

Voltage range: 0 to 50 volts

Input resistance: 20K ohm/volt

Voltmeter accuracy: +/- 2%

Ohmmeter resistance range: 0 to 20M

Ohmmeter accuracy: +/- 5% reading at center scale

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UNION SWITCH & SIGNAL m 4.5.2 Test Set-Up

1. Disconnect interpreter unit 110 Vac power.

2. Remove the two (of six) front panel machine screws closest the case hinge, and the two lock pins closest the case handle.

3. Remove the cara enclosesure from the case.

4. Pull the power supply PCB from its case slot; be careful not to damage the flat ribbon cables under the front panel.

CAUTION

l.)() NOT KEM.OVE OR INSTALL THE POWER SUPPLY PCB WITH INTERPRETh:R UNIT POWER ON, OTHERWISE COMPONENT uAMAGE MAY RE8ULT.

4. 5.3 Procedure

Operation

1. Adjust VOM to the RX. 1 scale.

Verification

1.

'l.. Connect VOM., "+" iead to 'f P7 and "-" to TPS and measure continuity.

2. Resistance should be 2.

3. M.ove VOM "+" lead to 3. TP6 and measure continuity.

4. Connect VOJ.v1, 11+11 4. lead to TPl and "-" to LP2 and measure continuicy.

s. Move VOt'i "+" lead to 5. '.i'P3 and measure continuity.

6. Uisconnect the VOM.. 6.

7. Connect J.15 Vac to 1. the power supply PCB on TPl and TP3 (ground on '.rP2) •

8. Turn on 115 Vac 8. power.

equal to or greater than 2 ohms.

l<.esistance should be 3. equal to or greater than 2 ohms.

Resistance should be 4. equal to or greater than 2 ohms.

Resistance should be s. equal to or greater than 2 ohms.

6.

1.

8.

Possible Problem Ar~a

Shorted track, de­fective SV supply module.

Shorted track, de­fective+/- 15V supply module.

Shorted track, one or both supply modules defective.

Shorted track, one or both supply modules defective.

6204, p. 4-25

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m UNION SWITCH & SIGNAL

O:eeration

9. Set voltmeter to lu Vdc scale and connect "+" lead to TP5, .. _ .. lead to TP7.

10. Set voltmeter to the 50 Vdc scale and move voltmeter "-" lead to TP6.

11. Turn oft power and disconnect ac and meter leads.

6204, P• 4-26

Verification

9. t'1eter should show Vdc, +/-0.l Vdc.

10. Meter should show Vdc, +/-0.5 Vdc.

11.

5.0

30.0

Possible Problem Area

9. Defective 5V supply module.

10. Defective +/-15V supply module.

11.

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SECTION V SUPPLEMENTAL DATA

UNION &WITCH & SIGNAL m

The tollowing publications provide additional data on the electronic components used on the interpreter unit PBC's:

M6~00 Prograuuning Reference Manual, Motorola Semiconductor Products, Inc., First Edition, Copyright November, 1976

Microprocessor Applications Manual, Motorola Semiconductor Products, Inc., First Edition, Second Printing, Copyright November, 1976

Motorola CMOS Data, Motorola Semiconductor Products, Inc., Copyright, 1978

Signetics Bipolar & MOS Memory Data Manual, Signetics Corporation, June 1977.

The TTL Data Book, Texas Instruments Inc.

5. :L DIAGRAMS

This section provides the complete schematic diagrams for all Eventtrak Interpreter PCB's, including the motherboard, and wiring diagrams for the various ribbon cables. Note that the Microprocessor Controller PCB schematic covers three sheets. Refer to section III for operating descriptions of the ~CB's and Appendix A for component specifications and part numbers.

0204, P• 5-1/2

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8

s: (K +5 MICROPROCESSOR R6

5 +5

I Rii I yl 4r 6802

!RO Vccl 8 ' +5 RI 3K

DATA BUFFERS MC6889/8T28 r------------,

I IC9 /"'] I Jill 101

I I I I

MC6889 /8T28 r------------, I 1c20 /"'] I

R3 +5

NM! 3K

R1

R4 3K

3K

"'O STANDBY .06Sµr

I C36 .J.'.:35

VMA 5 -

z HALT

E U7_____f_-=E_ 6 NM!

40 RESET

3 MR

36 RE

VMA_A

1

!!A

r--~~B5/8T95 I !C32 ___ _

P-AIO IOI f'..._ , I I

p = A.L___§_ I

I p~I

P-A7

Pc A.§.

15 I A.§.

,13

~~ IA5

+5---,-litVcc V ~ ·:,r ['~ i.1--' r-l!Ji\',-J ,068M ~

,.i

I I

I I

ADDRESS A 6 DECODERS

74LSl38

25 I I I i ... .J,J

~GZA .,-:; 7 RSEL 8 I JCI I

,¥ rs 9 RSEL 7

Ys 10 RSEL 6

! l ......... ., v----4 A15 _6_j~, i

Y3µ_l

Yzi J 3 H!>t.L

I Yil ' 4 RSEL uj

I ::: I: I: Yol 15 RSEL I

JPZ I 6K

H

VMA 11

Al

A 1_5_

_A_I 4

Ali_

IQ

~

II

11_

!CZI

74LSIO

74LSl38

74~

GZA .,-:; 7

!C22 rs 9

Ys 10

r:; J l

~12

Y zLLl_

q.L.1

PSEL 8

PSEL 1

Pill_!,

MSEL I

"1SEL 2

MSEL 31 !,!SEL 4

I I

M5E~

MSEL & ,

I M5EL 7

i

I I

I I

I

3 C y O I 5 MSEL 8 '1

1

M 2 B A4 I A t

I I

045127 5-0701, Rev. 0 - I

!C7! .1

-

BCFFE.REO !JAiA B~S l :?! ! CONTROL a~s . _ 9 ~ l ADDRES5 aus '~ :i

ADORE$ S JECODE BUS r 8 v,

I UNBUFFERED DATA BUS I z 0 ,

IC4

M AJ. ~

I I I 1C3 -

I PROM z

2716/2732

AX 211 l'CC - .

PSEL 6 18 I IF+>! I I,. AX

lcr1PGM ! ...1:.osa,

211 Vee

A6 "J

3 AS "14 4 A4

A3 5 A3 A2 6 AZ

-4.i 1 Al

B AO

QI Q.§.

~

Figure 5-1. Microprocessor Controller Schernat ic Diagram

m

PCB

62.04, P• 5-3/4

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~{ ATA BUS I 00. l

~~. 82.

0 a: . ...

1,,,U1111f\U .,.,.._,

ADDRFSS RUS AODRl'SS n,:-cno,:- RIIS UNRIIFfl'Rl'O DA TA RIIS

_ RESISTOR NETWORK I

1" PIA I +

8 5 3 3 6821 3.3K < < +12~

+51:ii CSI I

PIN I I 5.IK JI-M

cso IC38 PAO z MCCO I ?3- PAI 3

-~

COM )

~ m PA2 4 - SW I

_1_ JI-J ACIA i

PA3 S < 7 JSPST SW! TCHES 6850

Al 35 RSI DIP PACKAGE 75150

AO 36 RSO PA4 6 •s_--r£ TX DATA

6 4 IC41 II o-ouT

7. CSI

PAS cso JI-C

Rti ?I PA6 e 7 . !C40 RIW

MSEL 4 9r

" ?5 PA7 9 '-- CS2

RE Sq '4 E AO 75154 I RESET CB2 19 +5 +5 11 RS JP4

IRQ '7 !ROB 18 OUT©; ouTt!x

Rtii RX DATA L i:---. II !C44 6 n-TN ,

CBI 13 RtW 7

39 B RIB ~04

JPS I T CA2

E 14 E ----- JI -0

40 9 IC53 5 IC53 ~ 6 Rl9 LED3 CAI

!RO 7 IRQ P-D7 26 360 MV5054- 360 MV5054-3

•5

07 17 -P-D6 '7 PB7 74LS05 74LS05 P-07 15 07 75150

?R 06 16 RTS S I p-ns PB6

P-06 16 06 3 IC41 - I' RTS

05 15 P~04 ?Q PBS +5 P-05 17 05 JI-E

04 PB4 14 +5

P-03 30 P-04 18 04

03 OUTI ~ OUT2 ~ P-D2 31 I? GAT" '

P-03 19 03 02 PB2

2 Rl6 P-0' P-Dl 3? 11 GAT" ? 4 RI 7 LED2 ?Q 75154

DI PBI I IC53 LEDi 3 IC53

02

p-no 33 V._._PBO JO GATE I 360- MV5054-3 360 MV5054-3 P-01 21 01 CTS

24 f? !C44 5 CTS

00 v,..,.. 74LS05 74LS05 P-DO 22 /

DO 2 JI -F

I 20H:tt

BIT RATE GENERATOR +5

,068 I, 8432MHZ 14411 r--:- 75154

+5"' =

1,C:~STAL l 21

I 95nn JP6 RXCLK

XINICSO Fl oco 23 1n- !C44 7 nco

PROGRAMMABLE Tl MER 12 4800 TXCLK 7

6840 XTAL RI 4 F3 . - Yoo Vss JI -K 14

+5--1.§ 2 ISM FS

13 ?400 ---CSI IC37 = ?n 124:~ XOUT F6

15 1 •nn - +5

+5 24 voo F7 4 1 ,on ............,__ -068

"""' ? 1•- Gi ?C "ATF I cs,l ~ 5 cnn +5 pl' -=-~ cso RSB F8 -? """? 7 ,nn

-12

G2 -068P'T I RESET F9 - JI-N

.A? 12 RS2 o; ,; "AT" '

,, V5s Fl I

8 1 sn --Al I I RSI 23 13 11n -- •12

A" ID RSO + RSA F13 7

9 75 - JI -R Fl 4

R/W I' Rlii Rl2 +5~ 510 JI-P

" 17 R-,.'"°T 8

ENABLE RESET

iRn 9

TX+

j'RQ +5 /

JI -S I ICSI 01

P-07 I 15 TX-

18 07 ?A "

7 '

P-06 JQ cl l' ~ "'""' JI -T

P-D5 20 06 C2 t=t 4 2N3904

p-n4 ?I 05 B 04

2 6 4N36

p-n, ?? 03

5 IC46 6 R9 RS rxr. ?3 3 IC46 4 M51\ '

p-n, 02

/ 300 IOOK 7

P-DI '4 J2-M 74LSD5

JI -W

DI 74LS05 JPI

P-DO 25 ---- FRAME )

00 Vr.r. V,;,; [ • JI -A

14kli 9 8 ACK ,

SHIELD) IC46

.068 ,,

+5 JI-B J2-T

+5 "'= 74LS05 •12~

PIA 2 tRIO 6821 7414 \2K

51 0 JI -U

+Slii 39 R<n IC52

CSl IC39 CAZ I -2 STROsc' 2 IC47 I I RC-

40 RDY IC46 J~ t cso CAI 19

JZ-N JI f 02

Ji -v

M'-~' 3 02-74LS05

~cs2 CB2

18 2 RCG

CBI J_ I I N4003

Al 35 PAO? PAn RI I 6 4N36 JI -X

A" 36 RSI RSO PAI 3 PAI t0A L. 4,1,

- IOOK

PAZ 4 PAZ I R/W ?I ---11. 0 PR O j_ O PR O 5 13 IC46

-I? BRED MC6889 l8 T28

Rtii PA3 5 PA3 ,---------- .. " ?5 PA4 6 PA4 IC48 !C48 4LS05

J2-P I [:>42 I I E R<SET 34 RESET PAS 7 PAS 74LS74 74LS74 r-

PAO soo )

TRQ 38 9 ': <]]:' I

!ROA PA6 8 PA6 JZ-C I

NMI u. CP CLR if c....-1 CP CLR if&. !C45 8 ROY PBO

37 !ROB PAT g PA7 IO 74LS08 .:, ~L p-n1 26 10 PBO

13Y 1Y PAI SOI . ,7

07 PBO I

<j-J t P-D6 06 PBI I l PBI J2-0

P-0~ 28 PBI 141

PB2 12 PB2 p-n4 ?9

05 I I

PB3 13 PB3 4,1, P-"3 30

04 PA2 71 SO• I P84 14 PB4 12

P-"' 03 ...-Lo PR as 12 I I

31 PBS J2-E

i

16]. 4

Al5

Al 4

Al 3

Al 2

Al I

AIO

A9

AB

A7

A6

AS

A4

A3

A2

Al

AO

M''' •

MS"' 6

MSFI 1

M'' 8

PA4

PB4

J3 -45

J3 -47

~ ~ -so J3-!

J3 -48

J3 -46

J3 3-3

J3 3-1

.;3- II

J3~ -13

' J3 -9

' J3 -5

' , J3 -2

' 7 J3 -4

J3 -6

' J3 -8

' J3: 10

J3~ 31

' J3: 35

' J3: 41

7 J3-43

IQ

R/W

BA

E

VMA

TXSTB

RESET

NMI

HALT

!RO

-1 aJ

J3-32 ~ 07 )

J3-i 2

) 0 06 ) J3-34 J3-l 4

05 ) J3-30 J3-l 6

) 04 ) J3-28 J3-18

) 03 ) J3-36 J3-20

) 02 ) J3-38 J3-22

01 ) J3-40 J3-24

) 00 ) J3-42 J3-26

) --? J3-44 J3-I

"7 J3-l 5

--? J3-23

-) J3-29

--? J3-31

--? J3-39

--? J3-49

J2-S

TP2 JZ-21, Y

•5~ ..... ~~..-~~~~~~ J2-22, Z

+.LC54

TPl r l t <l,A - J2-2,B

+12

-12

svsATE8M~~s DAT

~5

~4 n~

n~

4

C6889 /~~ - - ..

~--- I 04 ) 1-- !C43 p S J2-H

t-{> J: _?_ /

PAS I?

PBS 14

I ~ I sos ) P84

2

1 [> 113 J2-J , I 4 <]]' I 1--- I I

: ~ :, "' ,L PA6 1

P86 ~

m

<j-J lo PBS 15 P-01 3'

02 ff 414 ~I G~OUT, PB2 s I PB6 16 PB6 IC49

p-nn DI

PR7 IC47 2~ 4 I I I 33 00- Vr.c VccPB7 17

74LS74 - +SJ I 9 I

GRANTW PA3 503 . PA7 9

~-{> 1 ! I V ,.,/1_ j I 1. --""7

I~ J2-L I V.,/1 I! 13

3 CP CLR if .§_ ZOP.:ld ~ ''" ""' ·- O.-v· MV5054-3 P83

.068 1Y 4

360

+5 "'= L~~~M/~~:0101 R<'°s•T G-!N •

7

E J2-R SYSTEM DATA OUT 8

D4 51275-0702, Rev. 0 SYSTEM DATA IN 8

I <}}I J2-F

111 I P87

I 16 I I 01£ R/E GND ~·5

'"-1--1--1- C43 I 15 I ~-068Pf i---I

- I I i Figure

ROY

II ----.~~· I ' 11s_ •s .- ~44

R/E .!:.~£._I r .0Ge•1

I OIE---,---18 •

5-

'--;-sT 1L-~

- J 2. Microprocessor Controller PCB

Schematic Diagram (Cont'd)

b:L04, p. 5-5/o

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{

8UFF!;:qEO DATA BUS

c~~i~o T ~~:::~~ :~! __ : _______________ - ---- ---~L---------- ---- -- -- --- ----- --- ------ --i SH.o

7ot i ! ADDRESS DECODE BUS -----------------{-- --------- -------> CONT'D

I ! UNBUFFERED DATA BUS - 1-------- --------- ----------------1 SY.

0

0~03

I 11 -------,0~ I ~ 8 10 I 2 8} 10,+- l-f-Z S IQ 1 2 st P:WEP WIR!NG )

2114

+5 ASEL B~cs

Riw 10 WE !Cl2

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6204, p. 5-9/10

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P, C, CONNECTOR "A"

A GND / ) (SDOJ Sl<.IP (4j

~:B~ GND 4- Hc.R <so, 1 coLuM>I sizE (6

1 C SDO ,IMFD 15021 MONITOR (B'

D SDI C:4 (503 I PROM PROG (19 502 +SY (5041 PRINTER (12

503 B (SDSI OVER RUN (1~

20 10

504 <S06l COMPLETE (1~

505 l <SD7l ERROR (1t so6 , m (3: 507 r < '- .5 t ) +12VOC, :::TPJ) rTP4 (~ +Sz

) -12VOC, ) ~ GNO. ? ~ ~ +SVDC, /' I' ) ( GNO. B

+SVOC, ' +12VDC, (U STARL __ (' -12VDC, (W

z N

R p R3 IOK ( +30VDC. S

DO C'

r DI DI 02 E

03 F, 04

05

06

l 07 "M11 SELECT 5 11M11 SELECT 6

3 11M11 SELECT 7

30 ~" 2 32 ) READ Iii READ /W z

"E" I

ID AO ri AO 1J Al Al l

B lltm P,C, CONNECTOR "B" 16P, DIP, CONNECTOR J2 16P, DIP, CONNECTOR J3 -=--------<I~ 38 ) ) I FRAME / / FRAME ·-·· ___ SIAl!I 40) llM[ NC A) _,I (I (I

44 T1ffi' NC B) SHIELOIGNO, * ) ..---------<' O< INTERPRETER ENABLE l VMA ?J C) DATA OUT ,/_ ( 3 / DATA OUT (Z !: ) RITT l O) DATA IN ./'_ (Z ./'_ DATA IN ( 3

6 AZ E) RTS ./'_ (5 I' RTS (4 A3 F ) CTS ./'_ ( 4 ./'_ CTS ( 5

/

)-M ~ ~

13 )-fl II )-.M. 7 ~ 3 ),-1.!.Q 46 All

48 Al2

so )--fil 47 )--hl1 45) AIS

I > 15)

23)

29)

31)

39)

49)

NC

TO MJCR0700

J ) COM .I'_ (7 /_ COM ( 7 K ) DCO ./'_ ( 9 I' OCD ( 8 M OTR / ( 8 / OTR ( 9 N -12VOC NC, ~, /~

p +SVDC NC. '------------------'

R +I ZVDC 10 S TX(+) TX(+) II

T TXI-) TXI-) IZ

U RCt+J RC<•> 14 V RC< - l RC< - I 15 W TXG TXG 13 X RXG RXG 16

TO ALL +5VOC,

L2

+ Cl

IOMF~ 35voc: f

P,C. CONNECTOR 5

@' I +SVOC. (U,Al

r"tn GNO, <3.C)

i I I SENSE ((5,E l

I I •30VOC, (<7.GJ

~2,__ __ -10150. TANT.

35VOC.

TLIO (<22,Zl

TL20 (<20,Xl

TO ALL "GNOU ~---------- TL30 (< 18, VJ

43 ) "M" SELECT 8 .,71

2

10

TO FRONT PANEL PCB

UNION SWITCH & SIGNAL

P.C. CONNECTOR "B"

DO (1,2

(3,4

(5,6

01

02

03 (7 ,B

(9,10

(11. 12

04

05

06 (13, 14

(15, 16

(17, 18

07

AO

Al (19,20

(21,22

(23,24

AZ

A3

(25,26

(27 ,28 >- TO RAM (29, 30 PCB

(31,32

A4

AS

AG

A7

AB (33, 34 A9

(35,36 AIO

(37 ,38 MAI I (39, 40 MAl2

(41,42 MAl3 ( 43, 44 MAl4 45,4fi

MAIS 47,48

"\ \.: VMAI (49,50

HALT 53,54

"E" 51,52 REAO/W 55,56

+SV( )JP~ (63,64,65,66

GNO( )'.i-P2 (69, 70, 71, 72

12 VMAI

m

Fi~ure 5-o. Motherboar,i J:>L:J:$ Schematic Diagram

b204, p. 5-13/14

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CA&L£ COUAJ.

(r,A)(2,s)+.svoe--<-------------------,

(3,C)("l,O)COMNI. --<-----------------

TP.6

TP.4 (1,.w)(20,x)CAS[ GA/0. --<---T-P,_S __ _

(21, Y)(22,Z)IISVAC --<---4-11!-. 3----'--l

(17,U)(l&,V) 115 VAC --<----+---1-...f

AI.C. ©

TP. 2

PS I r.... -1-SV@SA. \.V

® ® @)

('1,H)(6,J)+30VDC--<4---4-------------------..J

Figure 5-7. Power Supply Schematic Diagram

ONION SWITCH & Slt3NAL m

PS2 ±1!:>V® .SA

6204, p. 5-15/16

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Page 66: PDF Viewing archiving 300 dpi - Hitachi Rail...SERVICE MANUAL 6204 Operation and Maintenance EVENTTRAK DIGITAL EVENT RECORDER SYSTEM INTERPRETER UNIT N451400-3301 (Compatible Only

PARTS LIST

EVENTTRAK

SERVICE MANUAL 6204 APPENDIX A

DIGITAL EVENT RECORDER SYSTEM

INTERPRETER UNIT N451400-3301

December. 1983 (Revised November. 1986) B-11/86-75-2566-3

UNION SWITCH & SIGNAL DIVISION AMERICAN STANDARD INC./PITISBURGH, PA 15237

ID0135B

COPYRIGHT 1986, US&S DIVISION OF AMERICAN STANDARD INC. PRINTED IN USA

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m UNION SWITCH & SIGNAL

A. l CASE ASSEMBLY (See Figure A-1)

Item

1 2 3 4 5 b 7 8 9

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 2b 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41

6204, p. A-2

Description

Case, fiberglass End, right hand End, left hand Guide, Card Box, power supply Brace, center Top, card file Panel, front Support Guard Spacer, card guide left hand Spacer, hinge Spacer Filter, plexiglass Hinge Guide, Card Guide, PCB nylon Receptacle, side mount Fastener, stud Stud, 1/4 in. oval hd. Ho~der,fuse Switch, 'toggle single pole Filter, RFI line Cable, SO-conductor Cord, line SVT type Name plate Spacer, card guide right hand Pane 1, bot tom Fuse, 1.5 amp, 250 volt Rubber extd. channel Label Plug, vent black 1 in. Cable Cable Cable Clamp, cable RAM PCB Microprocessor Controller PCB Power Supply PCB Front Pane 1 PCB Motherboard PCB

US&S Part No.

M451612-2601 M451612-3301 M451612-3201 M451612-3104 M451612-3001 M451612-2901 M451612-3401 M451612-3701 M451612-2701 M451612-3101 M451612-3102 M451612-2802 M451612-2803 M451612-3601 M451612-2001 J712087 J712093 J726101 J791635 J792797 J713333 J725707-0175 J792920 N451458-2603 J045794 M451108-5202 M451612-3103 M451612-3801 J071042 A075114 M451523-2001 J792972 N451458-4502 N451458-4501 N451458-4601 J709556 N451441-4905 N451208-0106 N451204-2901 N451441-5201 N451605-5501

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17

3

F451400-33, Rev. 0

..

~ I - . - • \IJ I'.:_\ \'J ,t, \.'I \:, 1 I ~ - - - - -- - - - - -· - -· --':;;::;;±-r==-r--=- =- - ..::=----r::-\.~- =- = "=- - ==r~- --'E- -. - - .-,

I I I I Ill Interpreter ~ ,J I E.ventTra.1<. tt) I ~A I I UN451400 • 3301 ·q:7 . j I (b r-..,, . : : \

. l __ 1J

l,;I I,} I I I I 1.'°'~

11~1 I 1- I Ir, I ;,1 !, -J I I .Q/ r--r, . ,--------- 11-___ ...,..,....,...

J I I DPIN I :;;!i<f> .' ER. II.:-) © F~;E-

: I I iER.MINALi . ~llll~~I I . '. 1'zA. I . HOD£ &l!LEC. 'T

I I /';;;:\ I I~ ~t".'~ I, t11- JJ_-c ~ lt!J1 ,..,..v,-, 11 · 11 ""'O'F'F 1n I I PROM SOC:t<ET s1~T !o "'90

""" ~.

I I

~: ~ . PRINTER. u

13'2. Ot.J 80 OFF

MONrTOIL I ~ ==7a._ , ~-2:u.-c. I l:..!-----.J~

"Tll&MIN"-L 1 ~'''°r---T< LJ

COLUMN SKIP Sl'Z.E

R.'5-1.11.· C. I 11_

m 1 14

37 18 2 6 24 38 40 27 2 5

I~ \. I

0

32

23

-22

8

34

33

31 30 9

+

18 16

4

UNION SWITCH & SIGNAL m

,· \ I I I

12

15

- -------, I

=========·±.-1:

m-tn::.----13

41

26

Figure A-1. Case Assembly

b204, p. A-3/4

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UNION SWITCH & SIGNAL m

TH IJi , P:AGK' IiNliENT'rONALLY LEFT BLANK

6204, P• A-5

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m UNION SWITCH & SIGNAL

A.2 MICRUPROCESSOk CONTROLLER PCB N451208-0106 (See Figure A-2)

Item

IC 9, 20, 42 , 43 IClO, 11, 22 IC12-19, 23-30 1C21 1C31-33 ll;34 IC35 IC3b IC37 IC38, 39 IC40 IC41 IL:44 Il;45 1l:4t>, 53 IC.:47 IL:4~, 49 IL:50 ICSl,52 IC IC IC IC Ql XTAL 1 XTAL l Cl-50,55 L:52, 53 L:54 lU-5, 7 K6,15,20 li8, 11 1.<.10 K12, 13 1:(9 Kl4 K

K

KNl t<.16-19, 21 Ul ,D2 IC12-19, 23-30 JP6 ICl-8,40,50 IC9, 20 IC36, 38, 39 1C37 IC SWl

J3 llilJl-5 TPl-4

0204, P• A-6

Description

IC, Quad Bidirectional Tri-State Buffer IC, TTL Decoder/Demultiplexer IC,NMOS (1Kx4) Random Access Memory IC, TTL 3-Input NAND Gate IC, Hex, Tri-State Buffer IC, TTL Quad 2-Input NOR Gate re, TTL Quaa 2-Input NAND Gate IC, NMOS Microprocessor iC, Programmable Timer Module IC, Peripheral Interface Adapter IC, Asynchronous Communications Interface IC, Single End Line Driver IC, Single End Line Receiver IC, TTL Quad 2-Input AND Gate IC, TfL Hex Inverter IC, TTL Hex Schmitt Trigger Inverter IC, TTL ~dge Trigger Flip-Flop IC; ilaud Rate Generator IC, Optical Isolator Erasable Programmable Read-Only Erasable Programmable Read-Only Erasable Programmable Read-Only Erasable Programmable Read-Only Transistor, 60 Vdc, 200 mA Crystal, 4 MHz

IC Memory Memory Memory Memory IC

IC· IC

Crystal, 1.8432 MHz Capacitor, .068 mFd, 50 Vdc Capactitor, 27 pFD Capacitor, 22 mFd, 15 Vdc Resistor, 3K Ohm, 1/4 W Resistor, 5.lK Ohm, 1/4 W Resistor, lOOK Ohm, 1/4 W Resistor, 2.2K Ohm, 1/4 W Kesistor, 510 Ohm, 1/4 W Kesistor, 300 Ohm, 1/4 W Resistor, 15 Megohm, 1/4 W Resistor, 2.7K Ohm, 1/4 W Kesistor, 47K Ohm, 1/4 W Resistor Network, 3.3K Ohm, 2.7 W Resistor, 360 Ohm 1/4 W Diode, 1N4003 200 Vdc IC Socket, 18-Pin Jumper Socket 20-Pin Socket, 24-pin IC Socket, 16-Pin IC Socket, 40-Pin iC Socket, 28-Pin IC ~ocket, 8-Pin Duai In-Line Package Switch, 7-Rocker Jumper Plug Connector, 50-Pin Light Emitting Diode Test tiJrret lugs

Adapter

US&S Part No.

J715029-0248 J715029-0291 J715029-0289 J715029-0277 J715029-0249 J715029-0255 J715029-0238 J715029-0247 J715029-0244 J715029-0246 J751029-0250 J715029-0293 J715029-0295 J715029-0254 J715029-0290 J715029-0292 J715029-0280 J715029-0243 J715029-0236 N451575-1001 N451575-1002 N451575-1003 N451575-1008 J731281 J709242-0009 J709242-0008 J709145-0395 J706936 J709145-0396 J735052 J73.5301 J735137 J735237 J735159 J735519-0073 J7J5519-0225 J735238 J735035 J735519-0338 J735367 J723555 J725840-0007 J725840-0009 J725840-0003 J725840-0004 J725840-0001 J725840-0002 J725840-0006 J725707-0156 J713795 J709146-0121 J726150-0121 J703175

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UNION 8Wift:H Ii SIGNAL m lJ451208-000l, kev. l r, ::nnnnn:=_:= l » 0 .. .. !WWUL.11 .. r - • -

~~ E 3 J ~D:: MICROPROCESSOR CONTROLLER 119 ~

RIB RI& IC53 0 13 UN451208-0901 REY. lt31 • m.

I~[ I~[ Jnn ... ~ • • Inn [ inn • TPI

IC33 lt32 • ;o,.,,.,,.,,.,,.,,.,,.,[ Jnn u:.: u•

2( f: .. u:: lt20 ltl n., • • • u-

i[ IC34

J '= ':: '::':: ':: ':: ':: i o:i l Inn TPI '""' .. UI ... W N - U• • ·I

==c( Jnn u:.: IC21 IC10

:( ICJ5 • • )"" .. " n ITU! U"' . ~ ~ I OE [ I"" w ..

u= SWI • ,en ICl1 •

El l~ I • • :[ l"" loid I"!? uw

UN RN1

IC23 ICl2

i[ L .. • • • HJ= l i"" =[

u;:; )"" u= IC24 ICII u•

• •

i[ • w- )De [ i"" • .... )n" ~l L .. ,.w u.: u::

:[ ... IC25 IC14 )"" .... • • • nffl uu ~;;;

We l I"" ; [ I <I u= u ..

IC21 ICII • "" ""

.... • • g[ .::u u~ ~- •

TP4 [

• ::n We [ i"" )"" I"" U• u• u: t: [ Jes •u

t,J IC21 IC11 -12 ·11 IC44 • •

ICO IC42 Joe [ • I"!? ~[ £[ I"" u~

u:: • • l"" ICU ICll u~ 18£ ( Jn:: • • __ ...,..,_ U•

ID= l --w•""•"""•• I"!? .... -1,1111·•••••0 CIICIIOOCDCICIGCtO IC41 IC45 U• • ... ICZI IC11

:[ ..

)OE [ • • I"" l"" u:: ID= [ I"!? u•

~[ fg IC49 IC41 u• IC30 IC11

E[ r _, ro~ ;;l o,~n, RIO -( J- -c J- .. .. ..., u· 111 ,( J- -c J- ..

-c I), -oo, J-02

9· XTAL2 l13J- ,( J- -c J-112 115 JPI

~ JI-Z JI-A 12-z r 1

Figure A-2. Microprocessor Controller PCR Component Layout

6204, P• A-7

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m UNION SWltCH & SIGNAL

A.3 KAM PCB N451441-4905 (See Figure A-3)

Item Description US&S Part No. --ICl-24 Random Access Memory IC, TC5516 J715029-0335 H.:25 Progammable Voltage Ref. IC, ICL8212 J 715029-0334 IC:l.6-29 l-of-8 Decoder IC, 54LS138 J715029-0334 IC30-35 Quad, 2-Input N.AND Gate IC, 74COO J715029-0355 IC36-39 Hex. Buffer IC, 54LS04 J715029-0358 IC40 Quad, Z-Input N.AND Gate IC, 54LSOO J715029-0356 IC41 Quad, 2-Input NOK Gate IC, 54LS02 J715029-0357 Kl Resistor, 47K Ohms, 1/4 W J735035 K2 Resistor, SlOK Ohms, 1/4 W J735405 RJ Res is tor, 150K Ohms, 1/4 W J735040 K4, 9, 11 Kesistor, lOK Ohms, 1/4 W J735053 K5 Res is tor, 5.lK Ohms, 1/4 W J735301 K6 Resistor, lK Ohms, 1/4 W J735031 R7 Resistor, 75 Ohms, 1/4 W J735519-0043 K8,10 Resistor, lOOK Ohms, 1/4 W J735137 RlZ Resistor, 510 Ohms, 1/4 W J7351.'59 KU Potentiometer, 20K Ohms, 1/2 w J620850-0089 1<.14 Resistor, ZK Ohms 1/4 W J735049 Ul Diode, 1N4148 J726149 lJ2 Zener Diode J726081 03 Diode, MBR115 J726150-0168 Cl Capacitor, 4.7 m.Fd, 35 Vdc J706422 C2-34 Capacitor, .1 m.Fd, 50 Vdc J709145-0330 .IH Battery, Lithium J705151 Ql Trans1.stor, 2N3906 J731280 Q2 Transistor, 2N3904 J731281 Q3 Transistor, 2N4919 J731398-0037 TPl-11 Test Point P1.n J731396 1<.a-24 IC Socket, 24-Pin J725840-0003 IC2o-2~ IC 8ocKet, lo-Pin J725840-0004 1C30-41 IC.: Socket, 14-Pin J725840-0005 Jl Jumper Socket J792545 Jl Jumper J792546

o:L04, P• A-8

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tlNION Ml1'0H & SfGIWAL EB F4 51441-49, B.ev. 0

e L - OM <OM ,oM N

ICB UI...J IC16 UL.J JC24 uu

"f ] ] 1

. --,,_;--

"' ,.., u

> J u.J • M• ,-.M• .nM ..... .... a::: "' N

IC7 Uu ICIS UL.J IC23 UL.J

~~ ] ] 1 . --,,_;--

... ,.., u

vi J . • I

Cl-. M• ,oM• vM ......... a:::v ..,

N CCV IC6 '-'u !Cl 4 UL.J IC22 UL.J ~"' I ] ] 1 . --,,_;--

<CV a:::z ..,

® ,..,

J u

ffi· M• .nM" ,..,M .... N '- .... !CS Uu IC13 uu IC21 UL.J

I ] ] 1 . --,,_;--

N r ,.., J u

M" ..-M• NM .., N

IC4 Uu IC12 uu IC20 uu '- .... Q .. I

:f ] 1 a.. . --,,_;--....

i "' "' .... J

,.., u

M• ,..,M. -M "' N

IC3 '-'u ICI I UL.J IC19 uu '- ....

I ] ] 1 . --,,_;--

0

L J ,.., u

M" NM 0 OM 0.. ... N .... IC2 Uu ICIO uu IC18 uu

I ] ] 1 '- ....

J

"' r-,• -r-i• a>M

!Cl Uu IC9 UL.J IC17 UL.J ..,

I ] } 1 0.. ....

J

.... o..,.., Rl4

IC36 ..,

IC37 IC38 JC39 n~ 'ii -2: le RI ,..,

? B ~? I:? 1 \.. ,I -[{ }} R2 ~

J .., JI R3 u . ;:; . aj .,..«~ ?7 () - + .... u a.. .... IC26 IC27 IC28 IC29 {]} -Jl,

? :2 :? :? 1 03 .., • u

"' ,..,Rr-,,..FN J a.. .... "' ~

,.&M roM• a,r-,• or-i• ,.., ""yyyi.,., .::J LJ -N N N ..., 0.. UL.I UL.I uu UL.I 0 ,..., ...

RI I - 0..

g: J ~;1,JLJ N(

0 ....

lJ 1 ,.., -{ ]- { ]} "'( .... "' -{ ]- { } N

I ~N J y« RIO .., 0\ N Q ....

v, a,.,.,. IC41 IC40 f:: N « 0.. ."'e >- UL.I

,.., . « ...

uu

Figure A-3. RAM PCB Component Layout

a..ao4. ,.i. A-9

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m UNION SWITCH & SIGNAL

A.4 Fl:<ONT PANEL PCB N451441-5201 (See Figure A-4)

Item

Rl-5,10,11,17,21, L.8, 30, 33, 35-38 Rb-9 Rl2,23 Kl3, :t.4 J.<.14,25 I.U5, 32 Rlb,21:> Kl8, 34 J.<.19, 27 K20,29 l<.22,Jl Cl,2,5,6,12 l.;3,4 C7, lJ C8,10,14 C9,11,15 SWl, 2 ::iWJ SW4 ~1,2 Ql,L Ql,2 Ul, 2 LEDl-4 lliDl-4 Ll,2 TPl-'fP17 lCl ,2 11.,J,4 ::iKTl ::iKTl ::iKTl lCb, 7 IC8 Jl Jl

0204, P• A-10

Description

Resistor, lK Ohm, 1/4 W

Resistor, 360 Ohm, 1/4 W Resistor, l.lK Ohm, 1/4 W Resistor, 390 Ohm, 1/4 W Resistor, 2.2K Ohm, 1/4 W Resistor, lOOK Ohm, 1/4 W Resistor, 39 Ohm, 1/4 W Resistor, lOK Ohm, 1/4 W Resistor, 3.6K Ohm, 1/4 W Pot-Trimpot, lK Ohm Resistor, 5.lK Ohm, 1/4 W Capacitor, 10 mFd, 35 Vdc Capacitor, 68 MFd, 20 Vdc Capacitor, .22 mFa, 100 Vdc Capacitor, 1 mFd, 35 Vdc Capacitor, .1 mFd, 50 Vdc Switch, UPDT toggle Switch, DPDT toggle Switch, SPDT pushbutton Transistor, 2N2270 Transistor Mtg. Pad Heat Sink, aluminum Diode, MBR140P Light Emitting Diode, MV5054-l Spacer G'hoke, VK200 10/3d Test point pins Voltage Regulator IC, UA723 Peripheral Interface ~dapater IC, MC6821 Connector, wire-wrap, 24-pin Socket Spacer uptical-Isolator IC, 4N36 de/de converter IC, 12 Vdc Jumper plug Jumper socket

US&S Part No.

J735031

J735367 J735036 J735236 J735237 J735137 J735519-0462 J735053 J735033 J620850-0033 J735301 J706625 J706160 J709144-0048 J706387 J706436 J725707-0178 J725707-0256 J725 707-0162 J731186 J792072 J792496 J726150-0169 J726150-0069 M451529-0106 J709161 J703175 J715029-0070 J715029-0246 J709146-0156 J725869 M451612-0103 J715029-0236 J709557-0003 J792545 J792546

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..

t451441-52, Rev. 0

m~o rmO ,mo

.... •

> ... ... ... _ ...... e ..... tzl .... '? C".LJ

131 C ::I 137 C ::I

HI C::I IH C ::I Ill C ::I

,mo rmO ,mo TPl10

"' -....... ....... -...... ..... >• ..,:::,

SWJ

r ., L ..J

IZ n u

.... cJ n r,

ICI ~ •

moO mO m.O mp mO mO mO mO mO mO

Ill c :I

c :J 121 Cl

[ 121

c :I

c :::J Ill

~ ... ...

L

II n u

r , L ..J

IWI

n : : : 1:fll

,c,,....... nnn R" UUU u.,011

111nnn111 ...,.._, i' "\ uuu

n n 11• 11

\.. 4 uu

Ill

........... ICI

nLJ CJ u

IIJ

•••

II U U

n n n u u u

r, L .J

IWI

c11uvm +

1c•

,u....., nnn • CIJ + UUU ::

[ :!:i

nu nu nu nu u u u u

Ill

12,nnn """' i" "\ U U U Ill

n nm '- .!, U U II

....... n """' .

ICJ

UNION SWITCH a SIGNAL m

Cl '"'~' n )r w J C5v . + ..

n U111

n + i~ 1u'"'m CII W

IU c ::I

II [] " LI

Cl

+{ Jc Cl

Ji+ +C J +c[ ]Cl

ct

. [] "

Figure A-4. Front Panel PCB Component Layout

6204, P• A-11

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m UNION 8W1fCH & SIG~AL

A.5 M.OtHERBOARD PCB N451605-5501 (See Figure {A-5)

Item Description US6S Part No. --I<.;1 Triple 3-input NA~U gate 74LSlO J715029-0277 I<.:2 Octal D Flip-Flop 74LS374 J715029-0381 41 Transistor, 2Nl270 J731186 Cl,2 Capacitor, 10 mFd, 35 Vdc J706625 C3,5 Capacitor, .1 mFd, 50 Vdc J709145-0330 l.A, b Capacitor, 1 mFd, 35 Vdc J706387 1{1 Resistor, 5.lK Ohm, 1/4 W J735301 .lt2 Res is tor, lK Ohm, 1/4 W J735031 1.{3 Resistor, lOK Ohm, 1/4 W J735053 \" H.4 Resistor, 15K Ohm, 1/4 W J735061 Ll,2 Choke, VK 200 10h8 J709161 TLl,L,3 Terminal, solder J731396 TPl-) Test Point Pin J703175 RAM. Connector, 36-pos. J709146-0251 p. :::i. > FR. PNL., Connector, 22-pos. J70?146-0125 M.ICJ.<.0-700 Jl Connector, 50-way J709146-0121 J2,3 Socket, 16-pin J725840-0004

6204, P· A-12

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L

...

E451605-55, Rev O

[:::::t CJ•• ! . " (), c.,J 141> ~~--.::.•·.::.•---------------'•;..;·Z;.._­c:, :I! ffiiL--.-.. --------------,,,..,_,,,.,---'

i~ ~ ~t c::CO ICJ( ~(

~~ CJ C5 • !:z

] TP3 TP4

fl. PNL. PIC.

•1cao-100,c1

IAM PCI.

r _J

UNION SWITCH a SIGNAL m

1 H

.. , " 8-1

11

12 . D

TEST PAO

"

.. , 1·22

ll •

12

11

CJn, Tl2

:: t J Cl [ ) + JP5 lllz

'....=-...:;..._-----=---,

I R2 ]

RI [ ] ] ,,, ... 22

TPl

TP2

-,

Figure A-5. Motherboard PCB Component Layout

6204, P• A-13

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m UNION SWITCH & SIGNAL

A.6 POWER SUPPLY PCB N451204-2901 (See Figure A-6)

Item Description US&S Part No. --PSl Power supply module, +5 Vdc, 5 amp J725709-0079 PS2 Power supply module, +/-15 Vdc, 5 amp J725709-0080 TPl-7 Test point pin J703175

0

~o PS2

~o PS1

I ----...... --------~o ...... ----EO ------EO ------------_J !,..., SUPPLY BO. N451204·2901 REV.

_jl? m.~

Figure A-6. Power Supply PCB Component Layout

61.04, P• A-14


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