PDF VLSI DSP Embedded System Design

Copyright © 2005 Altera Corporation

Embedded System Design Using FPGAsEmbedded System Design Using FPGAs

2 Copyright © 2005 Altera Corporation

AgendaAgenda

Traditional Embedded System DesignEmbedded Processor in FPGAsDesign Flow with FPGAsConclusion


Embedded SystemsEmbedded SystemsComputing Systems inside a specific device applicationEmbedded System = Embedded Processor + Peripherals + SoftwareMust Work in Real Time !Usually Responds to External Stimulus− Incoming Call on a Cell Phone


Design FlowDesign FlowSystem System

SpecificationSpecification

AlgorithmAlgorithmModelingModeling

HW/SWHW/SWPartitioningPartitioning

HW/SWHW/SWIntegrationIntegration

System System ValidationValidation

RTOSRTOSSelectionSelection

Data Flow & Data Flow & Control FlowControl FlowDevelopmentDevelopment

Driver Driver DevelopmentDevelopment

Verify usingVerify usingEmulation/SimulationEmulation/Simulation

ModelModel

System System SpecificationSpecification

AlgorithmAlgorithmModelingModeling

HW/SWHW/SWPartitioningPartitioning

HW/SWHW/SWIntegrationIntegration

System System ValidationValidation

ProcessorProcessorSelectionSelection

Peripheral Peripheral DesignDesign

Custom IPCustom IPDesignDesign

HWHWIntegrationIntegration

HW HW ValidationValidation

SWSWIntegrationIntegration


Nios II EmbeddedProcessorNios II EmbeddedProcessor


What is Nios II?What is Nios II?Altera’s Second Generation Soft-Core 32 Bit RISC Microprocessor− Developed Internally By Altera− Harvard Architecture− Royalty-Free

FPGA

- Nios II Plus All Peripherals Written In HDL- Can Be Targeted For All Altera FPGAs- Synthesis Using Quartus II Integrated Synthesis

Ava

lon

Switc

h Fa

bric UART

GPIO

Timer

SPI

SDRAMController

On-ChipROM

On-ChipRAM

Nios IICPUDebug C

ache


Nios II Block DiagramNios II Block Diagram

ProgramController

&Address

Generation Instruction

Cache

clock

reset

irq[31..0]Control

Registersctl0 to ctl4

ArithmeticLogic Unit

Hardware-Assisted

Debug Module

InterruptController

JTAG interfaceto Software

Debugger

Custom Instruction

Logic

ExceptionController

InstructionMasterPort

DataCache

DataMasterPort

GeneralPurpose

Registersr0 to r31

CustomI/O Signals

Nios II Processor Core


0

50

100

150

200

250

0 500 1000 1500 2000CPU Core Size

(Logic Elements)

Perf

orm

ance

(DM

IPS)

Nios II: Faster & SmallerNios II: Faster & Smaller

Results Based on Stratix II FPGA

Economy

Fast

Standard

50% Smaller

Over 2X Faster10% Smaller

4X Faster


Binary Compatibility / Flexible PerformanceBinary Compatibility / Flexible PerformanceNios II /f

FastNios II /sStandard

Nios II /eEconomy

Pipeline

H/W Multiplier & Barrel Shifter

Branch Prediction

Instruction Cache

Data Cache Configurable None None

Logic Usage (Logic Elements) 1400 - 1800 1200 – 1400 600 – 700

CustomInstructions

5 Stage None6 Stage

1 Cycle

Dynamic

Configurable Configurable None

3 Cycle EmulatedIn Software

Static None

Up to 256


Hardware Multiplier AccelerationHardware Multiplier AccelerationNios II Economy version - No Multiply Hardware− Uses GNUPro Math Library to Implement Multiplier

Nios II Standard - Full Hardware Multiplier− 32 x 32 32 in 3 Clock Cycles if DSP block present, else uses software

only multiplier

Nios II Fast - Full Hardware Multiplier− 32 x 32 32 in 1 Clock Cycles if DSP block present, else uses software

only multiplier

AccelerationHardware

Clock Cycles(32 x 32 32)

None 250

StandardMUL in Stratix

3

FastMUL in Stratix

1


Nios II: Hard NumbersNios II: Hard NumbersNios II/f Nios II/s Nios II/e

Stratix II 200 DMIPS @ 175MHz1180 LEs1 of 8 DSP4K Icache, 2K DcacheStratix 2S10-C5

90 DMIPS @ 175MHz800 LEs

4K Icache, No DcacheStratix 2S10-C5


No Icache, No DcacheStratix 2S10-C5

Stratix 150 DMIPS @ 135MHz1800 LEs1 of 8 DSP4K Icache, 2K DcacheStratix 1S10-C5


4K Icache, No DcacheStratix 1S10-C5


No Icache, No DcacheStratix 1S10-C5

Cyclone 100 DMIPS @ 125MHz1800 LEs

4K Icache, 1K DcacheCyclone 1C4-C6


2K Icache, No DcacheCyclone 1C4-C6


No Icache, No DcacheCyclone 1C4-C6

* FMax Numbers Based Reference Design Running From On-Chip Memory (Nios II/f ≅1.15 DMIPS / MHz)


Peripherals for Nios II Peripherals for Nios II Memory Interfaces− EPCS Flash Controller− On-Chip

RAM, ROM− Off-Chip

SRAMCFI Flash

SDRAM ControllerDMAUARTTimers

Serial Peripheral Interface− SPI

Parallel l/OJTAG UARTLCD DisplayEthernet PortSystem ID PeripheralInterface to User LogicInterface to Altera IP


User-DefinedInterface

MemoryInterface

On-ChipDebug Core

Off-ChipSoftware Trace

Memory

UART n

Timer n

SPI n

GPIO n

DMA n

Avalon Switch Fabric

Instr.

Data

AddressDecoder

InterruptController

Wait StateGeneration

Data inMultiplexer

DynamicBus Sizing

AvalonMaster/SlavePort

Interfaces

MasterArbitration

Nios II System ArchitectureNios II System ArchitectureUART 0

Timer 0

SPI 0

GPIO 0

DMA 0

MemoryInterface

User-DefinedInterface

Nios IICPU


Avalon Switch FabricAvalon Switch FabricProprietary interconnect specification used with Nios II

Principal design goals− Low resource utilization for

bus logic− Simplicity− Synchronous operation

Transfer Types− Slave Transfers− Master Transfers− Streaming Transfers− Latency-Aware Transfers− Burst Transfers

32-BitNios II

Processor

Switch PIO

LED PIO

7-SegmentLED PIO

PIO-32

User-Defined Interface

ROM(with Monitor) UART Timer

Address (32)

Read

Write

Data In (32)

Data Out (32)

IRQ

IRQ #(6)

Avalon Sw

itch Fabric

Nios II Processor


Custom-Generated for Peripherals− Contingencies are on a Per-Peripheral Basis− System is Not Burdened by Bus Complexity

SOPC Builder Automatically Generates− Arbitration− Address Decoding− Data Path Multiplexing− Bus Sizing− Wait-State Generation− Interrupts

Avalon Switch FabricAvalon Switch Fabric


Avalon Master PortsAvalon Master Ports

Initiate Transfers with Avalon Switch FabricTransfer Types− Fundamental Read − Fundamental Write

All Avalon Masters Must Honor a waitrequestsignalTransfer Properties− Latency− Streaming− Burst


User-Defined Custom PeripheralsUser-Defined Custom Peripherals

What if I need to add a peripheral not included with the Nios II system?− user wants to add own peripheral to

perform some kind of proprietary −Expand or accelerate system capabilitiesAvalon switch fabric allows easy interface to custom peripherals


Custom InstructionsCustom Instructions

Augment Nios II Instruction Set− Mux User Logic Into ALU Path of Processor Pipeline


Synthesis- Translate Design into Device Specific Primitives- Optimization to Meet Required Area & Performance Constraints- Spectrum, Synplify, Quartus II

Design Specification

Place & Route- Map Primitives to Specific Locations Inside

Target Technology with Reference to Area &Performance Constraints

- Specify Routing Resources to Be Used

Design Entry/RTL Coding- Behavioral or Structural Description of Design

RTL Simulation- Functional Simulation (Modelsim,

Quartus II)- Verify Logic Model & Data Flow

(No Timing Delays)

LE M512

M4K I/O

FPGA Hardware Design FlowFPGA Hardware Design Flow

SOPC BuilderSOPC BuilderFunctional Simulation (Modelsim, Quartus II)Verify Logic Model & Data Flow (No Timing Delays)


Timing Analysis- Verify Performance Specifications Were Met- Static Timing Analysis

Gate Level Simulation- Timing Simulation- Verify Design Will Work in Target Technology

tclk

FPGA Hardware Design FlowFPGA Hardware Design Flow

Test FPGA on PC Board- Program & Test Device on Board- Use SignalTap II for Debugging


SOPC BuilderSOPC Builder

Altera, Partner & User Cores− Processors− Memory Interfaces− Peripherals− Bridges− Hardware Accelerators− Import User Logic

(ie. custom peripherals)Web-Based IP Deployment

Over 60 Cores Available

Today

– System Contents Page


Hardware designer selects which Nios II version to use when creating system

Nios II CPU Configured in SOPC BuilderNios II CPU Configured in SOPC Builder


Selecting JTAG Debug CoreSelecting JTAG Debug CoreConfiguration is chosen when hardware designer selects appropriate Nios II processor core


SOPC BuilderSOPC Builder – More “cpu” Settings Page


SOPC Builder – System Generation PageSOPC Builder – System Generation Page


SOPC Builder Produces a .PTF FileSOPC Builder Produces a .PTF File

Text file that records SOPC Builder editsDescribes Nios II SystemUsed by software development tools


Integrate SOPC Builder O/P in Quartus IIIntegrate SOPC Builder O/P in Quartus IIIntegrate SOPC Builder block symbol to Quartus II schematic (as shown below) and compile designOr, instantiate top module into your HDL design and compile


Project DirectoriesProject DirectoriesHardware− HDL Source & Netlist− db - Quartus project

database

Software− Application source code− Library files

Simulation− Testbench− Automatically generated

test memory and vectors


RTL SimulationRTL Simulation

Nios II SOPC Builder Automatically Creates Simulation Models Plus:− ModelSim Project− Testbench− Simulation Scripts

Set Simulation Option


SDRAMDev boardSRAM

Dev board FLASH

32-BitNios II

ProcessorOn Chip

ROM)

Clock Reset

Address (32)

Read

Write

Data In (32)

Data Out (32)

IRQ

IRQ #(6)

Avalon Sw

itch Fabric

Nios II Processor

Simulation TestBenchSimulation TestBench

Tri-StateBridge

Use

r Dev

ice

Compact FLASH

SDRAMController

Ethernet MAC/PHY

Tri-StateBridge

Compact Flash PIOs

User Defined Interface

User Defined

Peripheral

On Chip RAM

Custom Instruction

UART

User Device User Peripheral

Included

Not Included


User Additions to Nios II TestBenchUser Additions to Nios II TestBench

SOPC Builder creates testbench embedded in top level file eg NiosII.v

Sections within this file are reserved to add user files and code

These sections are preserved if the SOPC builder is used to re-generate the Nios II system


Running an RTL SimulationRunning an RTL SimulationLaunch ModelSim from Nios II IDE:− Highlight Software Project In C/C++ Projects panel− Right click− Run As Nios II ModelSim


Running an RTL SimulationRunning an RTL Simulation


Capture the state of internal nodesIn-system, at full system speeds

Up to 200 MHzMulti-Analyzer Support1,024 Channels128K Samples10 Trigger LevelsNo Probes!Can be used simultaneously with the Nios II IDE debugger and the FS2 console!

SignalTap™ II Logic AnalyzerSignalTap™ II Logic Analyzer


SignalTap™ II Logic AnalyzerSignalTap™ II Logic Analyzer


Nios II Software DevelopmentNios II Software Development


SOPC Builder FlowSOPC Builder FlowSOPC Builder GUI

Connect Blocks

Processor Library Custom Instructions

Peripheral Library Select & Configure Peripherals, IP

IP Modules

Configure Processor

C Header files

Custom Library

Peripheral Drivers

Compiler, Linker, Debugger

Software Development

User Code

Libraries

RTOS

GNU Tools

Generate

HDL Source Files

Testbench

Synthesis &Fitter

User Design

Other IP Blocks

Hardware Development

Quartus II

On-ChipDebug

Software TraceHard Breakpoints

SignalTap® II

AlteraPLD

JTAG,Serial, orEthernet

ExecutableCode

HardwareConfiguration

File Verification& Debug

NiosNios II IDEII IDE


Nios II IDE (Integrated Development Environment)*Nios II IDE (Integrated Development Environment)*

Leading Edge Software Development ToolTarget Connections− Hardware (JTAG)− Instruction Set Simulator− ModelSim®-Altera Software

Advanced Hardware Debug Features− Software and Hardware

Break Points, Data Triggers, Trace

Flash Memory Programming Support

* Based on Eclipse Project


Opening the Nios II IDEOpening the Nios II IDELaunch the Launch the NiosNios II IDE from II IDE from the SOPC Builder or from the SOPC Builder or from the Windows Start menuthe Windows Start menu


Nios II IDENios II IDE

List of Open Projects

Terminal window

File Viewer Window

(for C code, C++, and assembly*)

•Note: C++ files must have extension .cppIn-line assembly code offset by asm();


Nios II IDE C/C++ Projects/NavigatorNios II IDE C/C++ Projects/Navigator

Lists all open projects

Displays source files associated with project

List all open and closed projects

Allows you to drag and drop new files into existing projects


Creating a C/C++ ApplicationCreating a C/C++ ApplicationFile > New > Project


Creating a C/C++ ApplicationCreating a C/C++ Application

Link to a System Library- Select a pre-existing library- Or create a new library


This Creates Two Software Projects- Application and System Library ProjectThis Creates Two Software Projects- Application and System Library Project

System Library Project- contains system

header file, etc.

Application Project- contains application source code

Drivers Directory- contains all device drivers – DO NOT DELETE !


Application and System Library ProjectsApplication and System Library Projects

Application Projects build executablesSystem Library Projects contain interface to the hardware− Nios II device drivers (Hardware Abstraction

Layer)− Optional RTOS (MicroC/OS-II)− Optional software components (Lightweight

TCP/IP stack, Read Only Zip File System)


Other New Project OptionsOther New Project OptionsSystem Library− Only creates system library project− Build C applications upon this later

Advanced C/C++ Project− Disable automatic tool features like

makefile and linker script generation− User defines own instead

Managed Library Project− Facilitates software library

development− Enables you to associate pre-

compiled code into an Application Project

− Tool writes makefile for included files


Project Properties Project Properties Both Application and System Library have Properties pages


System Library OptionsSystem Library OptionsSelect RTOSSpecify stdio devicesPartition the memory map


Software CompilationSoftware Compilation

To compile a software application, highlight your project and select Build Project from the Projects menu


Directory Structure After CompilationDirectory Structure After Compilation

Application Project System Library Project


Hardware Abstraction LayerHardware Abstraction LayerA lightweight runtime environment for Nios II software− Provides a level of abstraction between application code and

low level hardware

HAL libraries are generated by Nios II IDEA HAL contains:− device drivers− initialization software− file system− stdio, stderr


Hardware Abstraction LayerHardware Abstraction LayerProvides generic device models for classes of peripherals common in embedded systems− eg. timers, I/O peripherals, etc.

Gives a consistent POSIX-like API, regardless of underlying hardwareMake programming as familiar as possible to software engineers who may not be familiar with the specific peripheral architectures

ANSI C (through the Newlib library)UNIX style interface (i.e. POSIX like)Altera extensions where standards don’t exist or were inappropriate (watch for the alt_* extension)


Hardware Abstraction LayerHardware Abstraction LayerKey features of the HAL− Uses standard interfaces where appropriate− Close integration with the Newlib ANSI C library

http://sources.redhat.com/newlib/− Device drivers automatically configured to match the PTF− Drivers initialised before main()− Scalable (i.e. packs down small)− Clear distinction between system and application software


Nios II Processor System Hardware

DeviceDriver

DeviceDriver

DeviceDriver…

Nios II HAL: Runtime LibraryNios II HAL: Runtime Library

_exit()close()closedir()fstat()getpid()gettimeofday()ioctl()isatty()kill()lseek()

open()opendirread()readdir()rewinddir()sbrk()settimeofday()stat()usleep()wait()write()

HAL API

HAL API

C Standard LibraryC Standard Library

User Program

The HAL ‘UNIX Style’ Functions are the glue between the C library and the device drivers


HAL File SystemHAL File System

/

/dev /mnt

/dev/jtag_uart0 /dev/lcd0 /mnt/rozipfs

/mnt/rozipfs/myfile1

/mnt/rozips/myfile21• Device names match those set in SOPC builder.• Can only access nodes, not directories.• All paths must be absolute (no current directory)


Familiar File/Device AccessFamiliar File/Device Access

ANSI C:fp = fopen (“/dev/lcd0”, “w”); fprintf (fp, “%s”, msg);

UNIX Style:fd = open (“/dev/lcd0”, O_WRONLY); write (fd, msg, strlen(msg));

Newlib also supports C++ streams:ofstream ofp(“/dev/lcd0”, ios::out); ofp << msg;

Existing code (outside the Nios world) uses these interfaces. Porting is now much easier.Use of existing standards means there’s nothing new to learn.


HAL System Header FileHAL System Header File

system.hsystem.h

SOPCSOPC Builder System ContentsBuilder System Contents

System Library SettingsSystem Library Settings


system.hsystem.hContains macro definitions for system parameters, including peripheral configuration, for instance: − Hardware configuration of the peripheral− Base address− IRQ priority (if any)− Symbolic name for peripheral

Does not include: static information, function prototypes, or device structures (unlike the old excalibur.h)Located in the syslib project directoryRarely necessary to include it explicitly in your application code, which improves rebuild time


system.h - examplesystem.h - example

.

.

./** button_pio configuration**/

#define BUTTON_PIO_NAME "/dev/button_pio"#define BUTTON_PIO_TYPE "altera_avalon_pio"#define BUTTON_PIO_BASE 0x00920830#define BUTTON_PIO_IRQ 2#define BUTTON_PIO_HAS_TRI 0#define BUTTON_PIO_HAS_OUT 0#define BUTTON_PIO_HAS_IN 1#define BUTTON_PIO_CAPTURE 1#define BUTTON_PIO_EDGE_TYPE "ANY"#define BUTTON_PIO_IRQ_TYPE "EDGE"#define BUTTON_PIO_FREQ 50000000

/** system configuration**/

#define ALT_SYSTEM_NAME "std_1s10ES"#define ALT_CPU_NAME "cpu"#define ALT_CPU_ARCHITECTURE "altera_nios2"#define ALT_DEVICE_FAMILY "STRATIX"#define ALTERA_NIOS_DEV_BOARD_STRATIX_1S10_ES#define ALT_STDIN "/dev/jtag_uart"#define ALT_STDOUT "/dev/jtag_uart"#define ALT_STDERR "/dev/jtag_uart"#define ALT_CPU_FREQ 50000000#define ALT_CPP_CONSTRUCTORS#define ALT_IRQ_BASE NULL

.

.

.

Defines system settings and peripheral configurations:− Replaces excalibur.h (from Nios)


HAL ReferencesHAL ReferencesEach HAL project references library routines and drivers for thecomponents included in your Nios II system


Reading/Writing Hardware in NiosReading/Writing Hardware in Nios

Nios Classic used volatile pointers to access hardware e.g.− volatile *my_led_pointer = (int *) LED_BASE;

Volatiles will no longer provide access to hardware registers in Nios II− They are still used to tell the compiler not to

optimize code− No longer disable cache access


Reading/Writing Hardware in Nios IIReading/Writing Hardware in Nios II

− IORD(BASE, REGNUM)Reads value at register REGNUM offset from base address BASE

− IOWR(BASE,REGNUM,DATA)Writes DATA to register REGNUM offset from base address BASE

Instead use I/O macros to access hardware− I/O macros bypass the cache for hardware accesses− They set bit 31 of address bus high (ie. control bit)

REGNUM = 0REGNUM = 0REGNUM = 1REGNUM = 1REGNUM = 2REGNUM = 2REGNUM = 3REGNUM = 3REGNUM = 4REGNUM = 4

BASE+2BASE+2

BASEBASE

BASE+4BASE+4


Header Files for Nios II PeripheralsHeader Files for Nios II Peripherals

Each Nios II peripheral has specific read/write macros for each register− Example: UART (altera_avalon_uart_regs.h)

#define IORD_ALTERA_AVALON_UART_RXDATA(base) IORD(base, 0)

#define IOWR_ALTERA_AVALON_UART_RXDATA(base, data) IOWR(base, 0, data)

#define IORD_ALTERA_AVALON_UART_TXDATA(base) IORD(base, 1)

#define IOWR_ALTERA_AVALON_UART_TXDATA(base, data) IOWR(base, 1, data)

#define IORD_ALTERA_AVALON_UART_STATUS(base) IORD(base, 2)

#define IOWR_ALTERA_AVALON_UART_STATUS(base, data) IOWR(base, 2, data)


InterruptsInterrupts

HAL API for ISRs - Functions− alt_irq_register()

Associates interrupt with your ISR function.

− alt_irq_disable_all()Disables all IRQs

− alt_irq_enable_all()Enables all IRQs

− alt_irq_interruptible()Used in ISR function body. Allows ISR to be interrupted by higher priority IRQs.

− alt_irq_non_interruptible()Used to make ISRs uninterruptible (default behavior).


Write your ISR(Follow prototype)

Register your ISRUsing alt_irq_register()

alt_irq_register ( alt_u32 id, void* context,

void (*irq_handler) (void*, alt_u32));

Sample Usage:alt_irq_register ( 3, &some_data, sample_isr);

sample_isr ( void* context, alt_u32 id);

id == irq number (0 to 31)context == void pointer to data produced by or consumed by ISR.

HAL API for ISRs - Useful InfoHAL API for ISRs - Useful Info


HAL API for ISRs - Useful InfoHAL API for ISRs - Useful InfoCreating interruptible code blocks in ISR− Use alt_irq_interruptible() & alt_irq_non_interruptible()

Do not use standard C library or RTOS software functions inside ISR that may pend for any reason− Eg. printf()

Keep it simple….− Use ISR to trigger execution of slow processing tasks outside of

interrupt context− Do NOT perform these tasks within ISR

References:− Exception Handling Chapter in “Nios II Software Developer’s

Handbook”


Software Run & DebugSoftware Run & Debug


Software Run and DebugSoftware Run and Debug

Nios II RunNios II IDE JTAG DebuggerNios II ISSNios II ConsoleThird Party tools


Running Code On A TargetRunning Code On A TargetNios II IDE can be used to download code to target board


Running Code On A TargetRunning Code On A TargetDownload messages, stdout and stdin appear in console window


Nios II IDE Run OptionsNios II IDE Run Options

Nios II IDE > Run > Run…


System ID Peripheral RevisitedSystem ID Peripheral RevisitedWhen downloading code to a target, Nios II IDE computes expected System ID peripheral values from PTF file− If computed ID values do not match System ID variables stored on

the target board then an error is flagged− Generally, to fix this you should recompile your hardware


Nios II IDE JTAG DebuggerNios II IDE JTAG Debugger

Requirements− Must have JTAG

Debug Core enabled in CPU


Nios II IDE Debug PerspectiveNios II IDE Debug Perspective

DoubleDouble--click to click to add breakpointsadd breakpoints

Basic Debug• Run Controls

• Stack View

• Active Debug Sessions

• Variables

• Registers

• Signals

Memory View


Nios II IDE DebuggerNios II IDE Debugger

Step ReturnStep ReturnStep OverStep OverStep IntoStep IntoStep with FiltersStep with Filters

DisconnectDisconnectTerminateTerminateSuspendSuspend

ResumeResume

Run last ConfigurationRun last ConfigurationDebug last ConfigurationDebug last Configuration


Nios II IDE DebuggerNios II IDE Debugger

Standard debug windows− memory− registers− Variables− breakpoints− expressions− signals


Nios II Instruction Set SimulatorNios II Instruction Set Simulator

Instruction Set Simulators are software models of an Instruction Set Architecture− Generally used to debug code if a target board

is unavailable.− Provides limited models of a few hardware

peripherals.TimerUARTMemory (flash, SDRAM, on-chip, etc…)


Nios II Instruction Set SimulatorNios II Instruction Set Simulator

Launch an ISS Debug session from the Run Menu


Nios II Instruction Set SimulatorNios II Instruction Set SimulatorTargets .elf file to ISS and opens debugger− Application can then be debugged as normal


Customizing Views in the IDE GUICustomizing Views in the IDE GUI

You can turn windows on or off in either the Run or Debug Perspective


Nios II SDK ShellNios II SDK Shell

SDK shell is still provided with Nios IIUsed to support legacy SDK flow (eg.. n2b, n2c) as well as other general commandsCan launch terminal to interface to JTAG UART’s− nios2-terminal

And compile code− nios2-elf-gcc


Nios II / FS2 ConsoleNios II / FS2 Console

Command line debugger


Nios II Console LaunchNios II Console Launch

FS2 Console Launches then minimizes


Nios II ConsoleNios II ConsoleAllows for hardware breakpoints and trace data− 2 HWBP’s and 16 Frames of On-

Chip Trace Included

Displays C Source, Assembly, Mixed


Nios II Debug SolutionsNios II Debug SolutionsProduct Provider Description Features

* Nios II IDE

** code|lab ATI Mentor IDE / Debugger JTAG Target Connection, H/W Breakpoints, Data Triggers, On-Chip Trace , FS2 Trace Probe

Watchpoint Sophia Systems

Debugger Supports FS2 ISA-Nios/T

IDE / Debugger

ISA-Nios/T

JTAG Target Connection, H/W Breakpoints, Data Triggers, On-Chip Trace, FS2 Trace Probe

External Trace Capture, Timestamp, Complex Data Triggers

JTAG Trace Probe

Altera

First Silicon Solution (FS2)

* Included in Nios II Development Kits** Evaluation Version Included in Nios II Development Kits


Upgrades from FS2Upgrades from FS2(see www.fs2.com for details)

Feature Nios II IDE FS2 S/W Upgrade

Hardware Execution Breakpoints

4

4

On-Chip128 Frames

Trace (Load / Store) No Yes Yes

Trace (Timestamp) No No YesTarget Connection Altera

USB/B BlasterAltera

USB/B BlasterFS2 Black Box(USB, Ethernet)

Cost Included See FS2 See FS2

Data Triggers

Trace (PC)

FS2 H/W Upgrade

2 4

2 4

On-Chip16 Frames

Off-Chip128K Frames


FS2 System Analyzer UpgradeFS2 System Analyzer UpgradeISA-Nios II System Analyzer− 10-pin JTAG Target Connection− Unlimited Software Breakpoints− 2 Hardware Breakpoints (upgradable to 4)− Supports On-Chip Trace (upgrades available for

deeper trace)

ISA-Nios II/T System Analyzer− 38-pin Mictor Connection− Blackbox probe− Supports 128k frames Off-Chip Trace

in addition to Unlimited On-Chip Trace


User Logic InterfacesUser Logic Interfaces


How to Add Your Logic to Nios II?How to Add Your Logic to Nios II?

Custom peripheral−Behaves like a peripheral to the Avalon

Bus−More Flexible than Custom InstructionCustom Instruction−Add your logic to the ALU−Stalls the CPU while running the

Instruction


No Need to Worry about Bus InterfaceImplement Only Signals NeededPeripherals Adapted to by Avalon Switch FabricTiming Handled AutomaticallyFabric Created for YouArbiters Generated for You

Custom Peripheral InterfaceCustom Peripheral Interface

Concentrate Effort onPeripheral Functionality!

User Logic

Avalon Switch Fabric

Register File


New Component EditorNew Component Editor


Creates InterfaceCreates InterfaceConnect to Existing HDL or board componentMap into Nios II Memory SpaceCan be “Inside” or “Outside” Nios II System

Nios IICPU

Ava

lon

Interfaceto UserLogic

Nios II SystemModule

External User

Peripheral

I/O

I/O

I/O

I/O

Nios IICPU

Ava

lon

InternalUser

PeripheralNios II System

Module

I/O

I/O

I/O

I/O


Create External Component InterfaceCreate External Component Interface

To communicate with off-chip peripheralsBase interface type on data sheet

AMD29LV065AD CFI Flash Chip


Or Add HDL FilesOr Add HDL FilesFor peripheral that has been encoded for FPGA


SummarySummary


Nios II - Leads The IndustryNios II - Leads The IndustryHighest

PerformanceHighest

PerformanceMulti-ProcessorHardware AccelerationCustom Instructions

Concept to System in MinutesFPGA > HardCopy Structured ASIC

GreatestFlexibilityGreatestFlexibility

Most Powerful Design Tools

Most Powerful Design Tools

Fastest Timeto Market

Fastest Timeto Market

ProcessorsPeripheralsOptimized Interconnect

SOPC BuilderNios II IDEOn-Chip Processor DebugSignalTap® II Logic Analyzer

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