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PEALL: Power Efficient And Low Latency

A 40 MSPS 12 bits SAR ADC for LTDJoel Bouvier, Daniel Dzahini, Carolina Gabaldon, Laurent Gallin-Martel

Fatah Ellah Rarbi, Benjamin Trocme, Mohamed ZeloufiLPSC, Universite Grenoble-Alpes, CNRS/IN2P3

LPSC Grenoble

Outline

• Background in ADC design at LPSC– From Pipeline to SAR ADC

• Architecture of asynchronous SAR ADC• Measurements – Proto 1 with external reference voltage– Proto2 with embedded reference

• Problems identified & solutions• Schedule up to production• Conclusion

2

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• ADC & DAC design are a long term research in our lab since 1999

• A full behavioral study was made on pipeline ADC

– Each parasitic effect analyzed. (Rarbi’s thesis)

• 12 bits, 25 MSPS pipeline• 14 bits, 15 MSPS DAC

• Many prototypes published in CMOS .35µm

Strong background in converters design

3

AdB

1.5 bit stage

Digital correction

2.5 bit stage

3 bit flash

Bias stage

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• First analog memory chip with embedded ADC in Collaboration with CEA Saclay.

• CMOS 0,35µm: 3x7mm

ADC IP for NECTAR Chip: CTA experiment

INL DNL

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Why moving from pipeline to SAR?

PIPELINE Architecture• Allow high speed design• Natural important latency• Power dissipation (amplifier)• ∆Vref means more INL • Mismatch in capacitors (*)• Vref buffer bandwidth (*)• Clock frequency (as sampling)• Sampling time (large: 12.5ns)• Total die area could be large• Scaling to future 65nm process

SAR Architecture• IBM 130 allows high speed• The best latency (after a Flash)• The best power dissipation• ∆Vref does not means INL• Mismatch in capacitors (**)• Vref buffer bandwidth (**)• Higher frequency clock (**)• Sampling time brief 3 or 4ns• Die area very small• Ready for scaling to 65nm

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Challenges & solutions for the SAR

Difficulties Our solutions

• Capacitors Mismatch • Vref buffer bandwidth

• Higher frequency clock

• Short sampling time

A trimming optimization

A huge task! We did it

Asynchronous design (only 40 MHz )

A segmented scheme Bootstrap switches

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• Power Efficient and Low Latency SAR ADC

• Main features of our PEALL ADC: – Asynchronous high speed clock (640 MHz) internally generated

from the 40 MHz clock and the output of the comparators.

– Fully differential configuration: array of capacitors is segmented in 2 Small area– Trimming feature to compensate from the capacitor mismatch

• 16 capacitors in parallel that can be disabled on demand to achieve the optimal value for the termination capacitor.• Value can be tuned by slow control

– Very basic and small digital part less affected by SEE that is the main radiation concern in HL-LHC

PEALL ADC architecture (1)

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PEALL ADC architecture (2)

trimming

± Vref

± Vref

± Vref

± Vref

SAR

Fast Clk

Bloc

40Mhz

LVDSOutput

serialiser registers

640Mhz

640MHzReadout

• The unit capacitor is 100 fF leading to a total equivalent of 3,2pF at each input

• The ADC is synchronized with the output stage serialiser.

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READ-OUT Interface

• Timing diagram:• SMPL, SAR clock, End Conversion are generated internally.• Read clock comes from outside to synchronize the serialiser.

Generated Locally fromThe master40MHz

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Prototyping & Results

All the following measurements were done while all the ADC channels were working in parallel

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• 2 channel version with external Vref tested in May 2013– Local clock generator was working properly– The design suffers from sampling noise at the Vref due to inductance problems

caused by the bonding wires from the chip to the package

• A Chip on board made to reduce the inductances from 5nH to 3nH, but we were still limited at 20MSP and ±4LSB of INL

1st SAR Prototype

Packaged prototype Daughter board Chip on board

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1st Prototype: External Vref limitations

For L=5nH; σ=10.24mV

For L=3nH; σ=9.5mV

• Measured noise on both Vref nodes:

Packagedprototype

Chip on board

VrefN=0.25V

VrefN=0.25V

VrefP=1.25V

VrefP=1.25V

Vref never settles properly

20 ns

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Vref settling and noise problems & solutions

Simulations for 1st prototype: External Vref

Simulation for 2nd prototype: Embedded Vref

300mV

100mV

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• 2nd prototype with 4 channels and embedded Vref

– Chip size: 2.8 x 3.4 mm2 in a QFN 64 package.– Power consumption: 5 mW/ch for core ADC, 27mW/ch with Vref driver and output LVDS (specs: 145mW/ch)

• Could ease cooling plate design (challenging in LTDB board)– Latency: 25 ns + 9 ns (serialiser) (specs : 200 ns)

• Could give more time to BackEnd/L1Calo for refined variable computation

2nd SAR Prototype

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Very challenging integrated Vref

• The integrated Vref define the dynamic range for the ADC.• It is built from a bandgap cell (CERN IP) followed by a very high

speed (5 GHz) and low impedance amplifier designed at LPSC. – This amplifier must charge all the capacitors in less than 1 ns.

High speed buffer SAR ADC

• Our testing results confirms that we succeed with the bandwidth of this buffer.– ADC works positively at 40MSPS, with the 640 MHz clock generated.

• Bandgap was qualify to TID by CERN team (30 mV drift over 200 MRad)

BandgapPTAT

IP from CERN 3,2pF

3,2pF

~ mA/1nS

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Vref testing results & improvements• A reference voltage 15% lower is found.

– Consistency between chips, but the mean value is less than the expected nominal value.

• The cause of the dispersion was identified as a current mirror mismatch in the amplifier.• Solution for next prototype found by MC

Simulations.

present prototype

next prototype

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ADC output noise distribution• As expected, the trimming feature has not impact on the random noise (1-2 LSB). • Spikes appear at regular codes reduced but not significantly by the trimming

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Integral Non Linearity • Trimming feature is working INL is progressively reduced• Spikes appear at exactly same codes following the noise results

INL = ±5 LSBfor trimming 16

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Spikes identified at very specific codes• Spikes observed for specific input signal always a fraction of Vref .

– It is not a random distribution.– Obvious correlation between “noise” spikes and INL’s spikes.

19

Time

4

8

Vinput = 0.880 V

Vinput = 0.882 V Vinput = 0.883 V

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• INL could be improved by a better segmentation of the capacitor array.• 3 emulated configurations:

– Improvement in linearity with 7MSB + 5LSB conf.– Total capacitance will not change.

Segmentation impact on INL

1 LSB of Linearity is saved by segmentation improvement

2nd prototype: 5MSB + 7LSB => INL = ±3

6MSB + 6LSB =>INL = ±2.5

7MSB + 5LSB=> INL < ±2

c(LSB) & c(MSB)

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Source & solution for spikes problem• Source of the spikes problem:

– Segmentation gives a 2nd order settling time for the DAC.– Meta-stability of the comparator.

• Spikes could be reduced by a better amplification before the latch comparator.

2nd prototype: Amp. x1 => INL = ±2 LSBAmp. x4 => INL = ±1 LSB

Amp. x8 => INL = ±0.5 LSB

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Dynamic specifications• Dynamic performance of the ADC are determined from the FFT for an

incoming sinus signal: 100 KHz, 1 MHz and 5 MHz .

5 MHz

100 kHz 1 MHz

These results integrate all the limitations:• reduce dynamic range• spikes• jitter (next slides)

Chip 8, channel 0, trimming 16

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ENOB vs. trimming

100 kHz

1 MHz

5 MHz

• Evolution of all channels vs. trimming capacitor:– ENOB increased when the trimming increased– Most efficient trimming 16

Chip 8, channel 0

For 5 MHz input signal ENOB ~ 7.7 – 8.3

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ENOB stability over this prototyping run• ENOB is measured for all channels and for the 11 packaged chips.

– Measurement consistent over chips and over channels.– But lower than specifications ~11.

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Lower ENOB - source & solutions

Theoretical limitations as a function of jitter

• Source of ENOB reduction sampling clock jitter

– 1 to10 ps jitter is needed to reach expectations.

– Simulation studies of 2nd prototype:• RMS jitter 30 ps or ±100 ps peak to peak

Present problem for jitterNew jitter simulated

• Solution:Modifying the architecture of the sampling pulse generator inside the chip.

30 ps

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Crosstalk measurement

• To determine the crosstalk between the ADC channels, a 1 and 5 MHz full scale sine-wave was applied to channel 1 while all the others (0, 2 and 3) are grounded.

Fin CH1 1 – 0 1 – 2 1 – 3

Crosstalk(dB)

1 MHz - 78.9 -76.7 -86.15 MHz -66.7 -69 -77.2

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Prospects for 3rd prototype

• Submission of the 3rd prototype by August 2014.• Digital part remains unchanged.• Minor modifications:– Optimization of the reference voltage.– DAC array segmentation from 5-7 to 7-5 configuration.– Optimization of the sampling clock to improve jitter.– Increase the gain of the first stage of the comparator.

•Simulations is finished and layout is going on.•Starting the test by December 2014.

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INL: Improvement expected (Cadence new configuration for SC ADC simulations)

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Radiation of the 2nd prototype

2 analog boards with 2chips to be irradiated

Digital ZedboardFor data readout and Ethernet DAQ & control

• Chips SEU irradiation was foreseen last week at Louvain Cyclotron facility, but they cancelled this run at the last moment.

• Protons of energy greater than 20 MeV with typical cumulated doses of 1-2*1013protons/cm2.

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Cost & Resources• We have a very small area chip < 8.5mm2

– Cost estimate for <10mm2 is less than 300KEu– Packaging: 10KEu

• Resources:– We were always on time with our schedule (design submission

& test).– LPSC has a long passed experience in testing many circuits for

ATLAS/LARG (SCA, shaper, smux...) with a home made robot.– We plan 3 possibilities for testing PEALL production:

1. Using our home made robot with our testing hardware & software2. Submission to a private company with a handling system3. Using MOSIS testing facilities

– With 2mn/chip=> 2.5months for production testing.

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Handling system for ASIC test in IN2P3

ATLAS FEB

Socket compatible with QFN and easy to open/close

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Schedule

• August 2014: Submission of the upgraded version of PEALL.

• December 2014-Feb 15: Testing this upgraded version

• March 2015: (Engineering run for about 500 chips)

• August to September 2015: test of engineering run.

• December 2015: Production Run

• March to September 2016 : Production Test

• October 2016: Delivery of qualified chips

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Plans for phase II

• While moving from pipeline to SAR architecture, we made a good choice compatible with 65nm.

• All the limitations of a SAR ADC are fully understood now.• In August 2014, we will submit in the IBM 130nm, our

first 12 bits SAR ADC with a redundancy architecture. – A digital correction algorithm is already developed and ready to be evaluated.

• In 2015, we will move this design in 65nm for a 12 bits and next 14bits with a gain selector stage.

• We do have an exiting perspective, and all the main critical points of our design are carefully under control.

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Robustness for redundancy SAR + LMS algorithm

Present version of binary SAR Redundancy version SAR + correction

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Conclusions1. SAR architecture was a challenging but good choice,

fully compatible with easy scaling to 65nm2. We positively reach the 40MSPS with Vref fully

embedded.3. This asynchronous 12 bits 40MSPS is a record4. The latency time, power & chip area are optimal.5. Minor problems identified and solutions found.6. Our next prototype will be at the requirement level. 7. Plans for phase 2 with a redundancy version and LMS

digital correction.

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BACKUP SLIDES

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Requirements targeted for the ADC

• Sampling rate 40MSPS• Dynamic range 12 bits• Resolution (ENOB) ≥11 bits• Differential Nonlinearity 1 LSB• Integral Nonlinearity 1LSB• Latency 200nS• Power dissipation 145mW

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SAR ADC with sampling capacitorsBinary Weighted Capacitor

Segmented Binary Weighted Capacitors

Thermometer control Capacitors

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R=39 Ohm et sans capa d'entreestep 1mV

Less nb. of spikes but HIGHER

1st Prototype: COB

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Vref Noise effect (in our Model)SFDR vs Vref RMS noise

0

20

40

60

80

100

120

0 2 4 6 8 10 12Vref RMS noise (mV)

SF

DR

(d

B)

SFDR

SNR vs Vref RMS noise

0

10

20

30

40

50

60

70

80

0 2 4 6 8 10 12Vref RMS noise (mV)

SN

R (

dB

)

SNR

SFDR(Vref noise) SNR(Vref noise)

THD vs Vref RMS noise

-120

-100

-80

-60

-40

-20

0

0 2 4 6 8 10 12

Vref RMS noise (mV)

TH

D (

dB

) THD

THD(Vref noise)

TID Chip 50 to 200Mrad full sweep

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0.580000

0.590000

0.600000

0.610000

0.620000

0.630000

0.640000

0.650000

Band gap IP testing results provided by CERN

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Robot developed in LPSC for ATLAS (since 1999)

One possibility for our production testing

Irradiations Setup

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SEE tests: Louvain Cyclotron (proton beam) is our main option at the moment.TID: BNL set-up

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Production testing procedure• Our present testing system is already split in two

parts (Analog board +digital board).• This configuration will be used for prod. Testing

and only the analog board will be upgraded with a new socket (with easier open & close)

• Parameters to check: Power consumption; dynamic range; ENOB for trimming 1 and trimming 16 while 5Mhz incoming sinus signal, INL & DNL.

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PhD thesis is going on for phase II SAR ADC 12 to 14 bits

• A Sub radix configuration has been fully simulated.

• A binary scheme with redundancy is also studied.

• An algorithm is written for digital correction purpose.

• The total power dissipation for the 14 bits in 65nm will be really less than for 12 bits in 130nm !!

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DAC (5MSB + 7LSB) DAC (6MSB + 6LSB) DAC (7MSB + 5LSB)

ENOB 8,547 9,373 10,1

SNR 53,78 58,53 63,31

SINAD 53,21 58,19 62,54

THD -62,28 -69,36 -70,42

Model’s Dynamic parameters for 10% mismatch on segmented capacitor