Pengenalan VHDL

7/24/2019 Pengenalan VHDL

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VHDL IntroductionVHDL Introduction


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Digital Circuit History

Prof. Sakir Sezer, Digital System Design, Queens Uniersity


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!lack !o"

!lack #o" model is met$od for descri#ing

digital systems

!lack#o" re%resent a function.

In%uts o ac o" are unction %arameterand t$e out%ut is function result


& ' f" (),!,C,t*

+ ' fy (),!,C,t*

' fz (),!,C,t*

A

BC

X

YZ


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S-itc$ing et-orks/$ere are t-o ty%e of s-itc$ing net-orks,

com#inational and se0uential net-orks (logic*

et-orks (Logic*

Se0uentialet-orks (Logic*



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Com#inational Logic

1ut%ut signal are function of t$e in%ut signal.

Ideally t$is signal are inde%endent of time

(ignore %ro%agation delay*

20uialent to one #oolean formula %er out%ut



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What does HDL stand for?What does HDL stand for?

HDL is s$ort for Hard-are Descri%tion Language

3 VHSIC Hard-are Descri%tion Language

Ver Hi $ S eed Inte rated Circuit

VHDL is a standard (VHDL45678* deelo%ed #y IEEE (Institute of 2lectrical and 2lectronics

2ngineers*. /$e language $as #een t$roug$ a fe- reisions, and you -ill come across t$is

in t$e VHDL community.


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9 Deelo%ed on t$e #asis ofADA -it$ t$e su%%ort of t$e

US) militaries, in order to $el% -$en making

documentation of t$e digital circuits

9 /$e ne"t natural ste% is to use it for simulation of digital

circuits and t$e last ery im%ortant ste% is to use it for

9 Versions: 5;666, >66> and >66< c$ars in VHDLB


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I222 Predefined data ty%esI222 Predefined data ty%es

ty%e StdGulogic is (FUB, F&B, F6B, F5B, FB, FB, FLB, FHB, F4B* FUB 44 Uninitialized

F&B 44 @orcing unkno-n

F6B 44 @orcing zero

F5B 44 @orcing one

FB 44 Hig$ im%edance

FB 44 eak Unkno-n

FLB 44 eak Lo-

FHB 44 eak Hig$

F4B 44 DonBt care

ty%e stdGlogic is resoled stdGulogic

ty%e stdGlogicGector is array (integer range J* of stdGlogic


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)ssignments)ssignments

constant a: integer :' R>=

signal #: #itGector(55 do-nto 6*

' 666666656656

# ' !666666656656

# ' !6666G6665G6656

# ' &65>

# ' 166>>


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Vector T )rray assignmentsVector T )rray assignments

su#ty%e instruction: #itGector(=5 do-nto 6*

signal regs: array(6 to 5R* of instruction

regs > ' regs 6 regs 5

regs(5*(7 do-nto 6* ' regs(6*(55 do-nto *


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)lias Statement

Signal instruction: #itGector(=5 do-nto 6*

)lias o%5: #itGector(= do-nto 6* is instruction(>= do-nto >6*

)lias o%>: #itGector(= do-nto 6* is instruction(5; do-nto 58*

)lias o%=: #itGector(= do-nto 6* is instruction(5R do-nto 5>*

1%5 ' 6666

1%> ' 6665

1%= ' 6656

Megs(#it>int(o%=** ' regs(#it>int(o%5** regs(#it>int(o%>**


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!uilt!uilt44In 1%eratorsIn 1%erators

Logic o%erators

)D, 1M, )D, 1M, &1M, &1M (&1M in VHDLB;= only*

Melational o%erators

, , , , ,

)ddition o%erators

, 4, T

Oulti%lication o%erators

K, A, mod, rem

Oiscellaneous o%erators

KK, a#s, not


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VHDL Data /y%eVHDL Data /y%e


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VHDL Data /y%eVHDL Data /y%e


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Oodeling StylesOodeling Styles

/$ere are t$ree modeling styles:

!e$aioral (Se0uential*

Data flo-

Structural


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VHDL Hierarc$yVHDL Hierarc$y


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Se0uentialSe0uential ss Concurrent StatementsConcurrent Statements

VHDL %roides t-o different ty%es of e"ecution:

se0uential and concurrent.

Different ty%es of e"ecution are useful for

modeling of real $ard-are.

Su%%orts arious leels of a#straction.

Se0uential statements ie- $ard-are from a

%rogrammer a%%roac$.

Concurrent statements are order4inde%endentand async$ronous.


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Se0uential StyleSe0uential Style


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Data flo- StyleData flo- Style


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Structural StyleStructural Style


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Structural Style

Circuits can #e descri#ed like a netlist.

Com%onents can #e customized.

Large, regular circuits can #e created.


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Structural StatementsStructural Statements

Structural VHDL descri#es t$e arrangement and

interconnection of com%onents.

!e$aioral descri%tions, on t$e ot$er $and, define

res%onses to s gna s.

Structural descri%tions can s$o- a more concrete

relation #et-een code and %$ysical $ard-are.

Structural descri%tions s$o- interconnects at anyleel of a#straction.


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/$e com%onent instantiation is one of t$e #uilding #locks ofstructural descri%tions.

/$e com%onent instantiation %rocess

re0uires com%onent declarations and

com%onent instantiation statements.

Com%onent instantiation declares t$e

interface of t$e com%onents used in

t$e arc$itecture.

)t instantiation, only t$e interface is isi#le.

/$e internals of t$e com%onent are $idden.


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Se0uential Style Synta"Se0uential Style Synta"

)ssignments are e"ecuted se0uentially inside

%rocesses.


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Se0uential StatementsSe0uential Statements

WSignal, Varia#leX assignments

@lo- control

ifconditionJ t$en statmentsJYelsifconditionJ t$en statmentsJZ

else statementsJ

end if

for rangeJ loo% statmentsJ end loo% -$ile conditionJ loo% statmentsJ end loo%

case conditionJ is

-$en alueJ 'J statementsJ

-$en alueJ 'J statementsJ

-$en ot$ers 'J statementsJ

ait on signalJ until e"%ressionJ for timeJ


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Data 1#NectsData 1#Nects

/$ere are t$ree ty%es of data o#Nects:

Signals

Can #e considered as -ires in a sc$ematic.

Can $ae current alue and future alues. Varia#les and Constants

Used to model t$e #e$aior of a circuit.

Used in %rocesses, %rocedures and functions.

ll


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Constant DeclarationConstant Declaration

) constant can $ae a single alue of a gien ty%e.

) constantBs alue cannot #e c$anged during t$e

simulation.

Constants declared at t$e start of an arc$itecture can #e

used an -$ere in t$e arc$itecture.

Constants declared in a %rocess can only #e used insidet$e s%ecific %rocess.

C1S/)/ constant_name : type_name Y : ' alueZ

C1S/)/ riseGfallGtime : /IO2 : ' > ns

C1S/)/ dataG#us : I/2[2M : ' 58

V i #l l iV i #l l i


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Varia#le DeclarationVaria#le Declaration

Varia#les are used for local storage of data.

Varia#les are generally not aaila#le to multi%lecom%onents or %rocesses.

)ll aria#le assignments take %lace immediately.

Varia#les are more conenient t$an signals for t$e

storage of (tem%orary* data.

Si l D l iSi l D l i


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Signal DeclarationSignal Declaration

Signals are used for communication #et-een com%onents.

Signals are declared outside t$e %rocess.

Signals can #e seen as real, %$ysical signals.

Some e ay must e incurre in a signa assignment.

Si l ) i tSi l ) i t


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Signal )ssignmentSignal )ssignment

) key difference #et-een aria#les and signals is t$e

assignment delay.

V i #l ) i tV i #l ) i t


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Varia#le )ssignmentVaria#le )ssignment

I@I@ C)S2C)S2 t t t S tt t t S t


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I@I@ 33 ss C)S2C)S2 33 statement Synta"statement Synta"

@1M@1M HIL2HIL2 t t t S tt t t S t


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@1M@1M 33 ss HIL2HIL2 33 statement Synta"statement Synta"

@or is considered to #e a

com#inational circuit #y some

synt$esis tools. /$us, it cannot

$ae a -ait statement to #e

synt$esized.

$ile is considered to #e an @SO

#y some synt$esis tools. /$us, it

needs a -ait statement to #e

synt$esized.

)I/)I/ statement Synta"statement Synta"


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)I/)I/ 33 statement Synta"statement Synta"

/$e -ait statement causes t$e sus%ension of a %rocess statement or a

%rocedure. -ait YsensitiityGclauseZ YconditionGclauseZ YtimeoutGclauseZ

SensitiityGclause ::' on signalGname

wait on CLOCK;

ConditionGclause ::' until #ooleanGe"%ression

wait until Clock = 1;

/imeoutGclause ::' for timeGe"%ression

wait for 150 ns;

SensitiitySensitiity listslists ss aitait onon statementstatement


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SensitiitySensitiity44listslists ss aitait44onon 44 statementstatement

P i l i VHDL iP i l i VHDL i


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Port signal in VHDL ma%%ingPort signal in VHDL ma%%ing

Concurrent Process 20uialentsConcurrent Process 20uialents


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Concurrent Process 20uialentsConcurrent Process 20uialents

)ll concurrent statements corres%ond to a %rocess

e0uialent.U0: q


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Com%onent DeclarationCom%onent Declaration

/$e com%onent declaration declares t$e interface of t$e

com%onent to t$e arc$itecture. ecessary if t$e com%onent interface is not declared

else-$ere (%ackage, li#rary*.

Com%onent InstantiationCom%onent Instantiation


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Com%onent InstantiationCom%onent Instantiation

/$e instantiation statement ma%s t$e interface of t$e

com%onent to ot$er o#Nects in t$e arc$itecture.

Com%onent Instantiation Synta"Com%onent Instantiation Synta"


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Com%onent Instantiation Synta"Com%onent Instantiation Synta"

/$e instantiation $as = key %arts

ame

Com%onent ty%e Port ma%

Com%onent Li#rariesCom%onent Li#raries


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Com%onent Li#rariesCom%onent Li#raries

Com%onent declarationsmay #e made inside

%ackages.

om%onents o not ae to

#e declared in t$earc$itecture #ody

[enerics[enerics


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[enerics[enerics

[enerics allo- t$e com%onent to #e customized u%on

instantiation.

[enerics %ass information from t$e entity to t$e

arc$itecture.

Common uses o generics

Customize timing

)lter range of su#ty%es

C$ange size of arrays

ENTITY adder IS

GENERIC(n: natural :=2);

PORT(

A: IN STD_LOGIC_VECTOR(n-1 DOWNTO 0);

B: IN STD_LOGIC_VECTOR(n-1 DOWNTO 0);

C: OUT STD_LOGIC;

SUM: OUT STD_LOGIC_VECTOR(n-1 DOWNTO 0)

);

END adder;

/ec$nology Oodeling/ec$nology Oodeling


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/ec$nology Oodeling/ec$nology Oodeling

1ne use of generics is to alter t$e timing of a certain com%onent.

It is %ossi#le to indicate a generic timing delay and t$en s%ecify t$e

e"act delay at instantiation.

/$e e"am%le a#oe declares t$e interface to a com%onent named inv.

/$e %ro%agation time for $ig$4to4lo- and lo-4to4$ig$ transitions can

#e s%ecified later.



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/$e [22MIC O)P is similar to t$e P1M/ O)P in t$at it

ma%s s%ecific alues to generics declared in t$e

com%onent.

[enerate Statement[enerate Statement


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[enerate Statement[enerate Statement

Structural for4loo%s: /$e [22M)/2 statement

Some structures in digital $ard-are are re%etitie in nature.(M)O, M1O, registers, adders, multi%liers, *

%ro es t e statement to automat ca y create

regular $ard-are.

)ny VHDL concurrent statement may #e included in a [22M)/2

statement, including anot$er [22M)/2 statement.

[enerate Statement Synta"[enerate Statement Synta"


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[enerate Statement Synta"[enerate Statement Synta"

)ll o#Nects created are similar.

/$e [22M)/2 %arameter must #e discrete and is

undefined outside t$e [22M)/2 statement.

2"am%le: )rray of )D2"am%le: )rray of )D44gatesgates


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% y% y gg

Simulate Design using Quartus II


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Simulate Design using Quartus II

)lteraBs Quartus II is a PLD design soft-are suita#le for $ig$4

density @P[) designs.

Sc$ematic 2ditor, VHDLAVerilog 2ditor, aeform Simulator.

Programma#le Logic Design @lo-


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Programma#le Logic Design @lo-


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/ufft Uniersity

---.ece.tufts.eduAeeA>8Atutoria&sA#hd&2utoria&.%%t

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