International Journal of Applied Engineering Research ISSN 0973-4562 Volume 12, Number 16 (2017) pp. 5525-5531
© Research India Publications. http://www.ripublication.com
5525
Performance Analysis of Cascaded Multilevel Inverter Based DSTATCOM
Adepu Sateesh Kumar
Associate Professor, Department of EEE,
Vaagdevi College of Engineering, Warangal, Telangana India.
K.Prakash
Professor, Member IEEE Department of EEE,
Vaagdevi College of Engineering, Warangal, Telangana India.
Hareesh Kumar Yada
Associate Professor, Department of EEE,
Vaagdevi College of Engineering, Warangal, Telangana India.
Abstract
In this paper, a single-phase Seven-Level and Five-Level
cascaded H-Bridge Inverter (CHB) based Distribution Static
Compensator (DSTATCOM) is presented. A simple control
algorithm based on inverse park PLL was proposed for both
five-level and seven-level inverters. Synchronous Reference
Frame theory (SRF) as control algorithm is used for reference
source current extraction and to generate gating pulses for the
DSTATCOM. The main aim of the CHB is to eliminate source
current harmonics and improve input power factor in the
single-phase distribution system. The multilevel inverter has
some limitations in its applications due to high complexity and
size. The proposed control algorithm has two components,
converting the load current into stationary reference frame
coordinates and estimation of peak amplitude of load currents.
Hence, a simple and reliable controller with ease of
implementation was developed. The algorithm for single-
phase DSTATCOM is aiming to perform with accurate
tracking performance under step changes in load currents and
to provide good dynamic compensation. In this paper, Inverse-
Park transformation is adopted for generating quadrature
component of current because of its dynamic performance
under all varying conditions. The performance of the control
algorithm is tested and evaluated using MATLAB/Simulink.
Keywords: Distribution Synchronous Compensator
(DSTATCOM), Cascaded H-Bridge Inverter (CHB), Power
Quality (PQ), Phase-Locked Loop (PLL).
INTRODUCTION
In recent years, harmonics is the most important issue in terms
of power quality due to wide-spread of power electronic
devices in commercial, industrial and domestic loads. In
distribution systems, the usage of non-linear loads such as
computers, variable/adjustable speed drives, LED lighting
systems and compact fluorescent lamps etc are using widely
and prone to harmonics. These harmonics are causing severe
problems such as power losses in equipments, malfunctioning
of devices, damaging of sensitive loads and motor failures.
Therefore, it is a serious concern in distribution systems for
both consumers and suppliers to eliminate harmonics and meet
the requirements of IEEE 519-1992 or IEC 61000-3-2 [1]-[2].
The harmonics produced by the loads are causing grid voltages
to be distorted. Conventionally, passive filters are employed
for harmonic mitigation and reactive power compensation.
But, these suffer from disadvantages like, cost, bulkiness,
resonance and fixed compensation [3]. Therefore, a dynamic
solution is preferred that fits the compensation is a
DSTATCOM. The role of DSTATCOM is to compensate
harmonic currents and reactive power with improved power
factor produced by the load. The controller has to track the
step changes in the load accurately and to choose reference
current properly for better compensation.
Keeping accuracy and reliability in view, many techniques are
proposed in literature for quadrature signal generation. Zero
Crossing Detector (ZCD) [4] method is simple but, sensitive to
grid variations. The most widely used method is synchronous
reference frame theory and SOGI based theory [4]-[5]. It is
less accurate to unbalanced and lower harmonic components.
But, SRF theory with inverse park transformation based
algorithm is found satisfactory under distorted conditions with
low computational burden. However, application and
implementation of this control strategy for a five level
cascaded H-bridge active power filters has not gained much
attention in the literature.
Multilevel inverters have gained much attention due to its
enormous advantages over conventional voltage source
inverters. The conventional two-level inverter is also capable
of handling reactive power, harmonic reduction and power
factor improvement under various load changes. But, due to
advancement of power electronic devices and controllers,
multilevel inverters have shown their ability to compensate
power quality problems with simplicity, low cost, reliability
and high-quality output. There are many topologies proposed
in the literature [7]-[9], Flying capacitor based inverter, neutral
point clamped inverter and cascaded H-bridge type multilevel
inverter is found suitable for DSTATCOM application with
ease of control.
In this paper, CHB type of multilevel inverter is used to reduce
the rating of the devices used and elimination of harmonics
with an increase in levels of the converter. This method also
reduces the switching losses and decreases the ratings of the
DC link capacitors used. The control algorithm is found
effective in linear/ non-linear and increase in load conditions.
In order to all these topologies, various PWM techniques were
also proposed in the literature which includes selective
harmonic elimination based PWM, Multilevel space vector
based PWM and Carrier based PWM etc [10]-[24]. The main
advantage of this CHB inverter is increasing of switching
International Journal of Applied Engineering Research ISSN 0973-4562 Volume 12, Number 16 (2017) pp. 5525-5531
© Research India Publications. http://www.ripublication.com
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levels by increasing the number of H-bridges in the circuit.
This paper uses a simple SRF based control in addition with
inverse park transformation based PLL to generate quadrature
signal for harmonic elimination and reactive power
compensation.
A CHB based DSTATCOM is proposed in this paper, Non-
linear load conditions under steady state and dynamic
conditions are carried out using Simulink, simpower systems
block set and its performance found satisfactory.
PROPOSED CONFIGURATION AND CONTROL
ALGORITHM
The CHB based DSTATCOM shown in Fig. 1. Each H-bridge
consists of a two-leg Voltage Source Converter (VSC)
consisting of 8 IGBT switches for five-level and Three VSC’s
with 12 IGBT switches with separate DC sources for each
VSC as shown in Fig. 2. DSTATCOM is connected in
between source and load in parallel through an interfacing
inductor Lf at the point of common coupling (PCC). The
proposed controller for DSTATCOM is capable of
maintaining the total harmonic distortion (THD %) within the
limits by eliminating the harmonics in the source current.
Power factor correction, reactive power and harmonic
compensation is also done even under varying linear and non-
linear load conditions to test the performance of the controller.
The DSTATCOM can be operated with required active and
reactive power injection by adjusting the magnitude and phase
of the system. The ratings of the proposed system are listed in
appendix. The rating of the DSTATCOM should be 15% more
than the Load rating for safer and economic operation.
I = Iα
Iq
αβ
dq
Id
Inverse Park Transform
wt
dq
αβ
I’α
I’β
wt
Figure 3: Inverse Park Transformation based Quadrature
Signal Generation
A. Inverse Park Transformation Fig.3 shows the structure of inverse park transformation. In
this method, two loops are formed that are nonlinear and
interdependent. In order to eliminate algebraic loops, First-
order low pass filters are employed for each d and q signal.
Park transformation is done (i.e, αβ0/dq0s) and these outputs
are used for inverse park transformation as shown in fig.3.
Vs
RL
LL
RsLs
Cdc
N
A
Five-Level or
Seven-Level
DSTATCOM
Linear
LoadLf
PCC
Vdc
Figure 1: Line Diagram of the Proposed System.
Seven-Level
DSTATCOM
PCC
Cdc1
Cdc2
S21 S23
S12S14
S13S11
S24 S22
Vdc1
Vdc2
Cdc2
S21 S23
S24 S22
Vdc3
Five-Level
Figure 2: Cascaded H-Bridge Multilevel Inverter
IP-PLL
Vg
wt
Fig. 3 IL
LPFILP
Σ
LPF Σ-
V*dc
PI
Icd
Vdc1
Is*αβ0/d
Id
Iα
Iβ
Σ
Is-
Σ
Vdc2
dq0/αPWM
Generator
Vdc3
CHB-1
CHB-2
CHB-3
Figure 4: Block Diagram of Reference Source Current Generation
International Journal of Applied Engineering Research ISSN 0973-4562 Volume 12, Number 16 (2017) pp. 5525-5531
© Research India Publications. http://www.ripublication.com
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q
d
VV
VV
ˆcosˆsin
ˆsinˆcos (1)
The dynamics of the phase detector mainly depends on the low
pass filter that is used after the transformation to filter out any
noises or harmonics that are present in Vd and Vq.
c
c
wswsLPF
)( where, cw is the cut-off frequency (2)
The difference from other PLL’s is generating a dummy
voltage signal from the feedback loops.
B. Reference Current Generation The peak amplitude of active component of current is
calculated as shown in Fig. 4. The Load current is sensed and
supplied to inverse park transformation to generate quadrature
signals (ILα and ILβ) and then transformed back to Id and
supplied to a low-pass filter. The output is then added with the
output generated by the DC voltage control loop to produce
reference active component of current (ILP + ICD). The
measured voltage (Vdc) across the two DC capacitors for five-
level (Vdc1+Vdc2) and three capacitors for seven level
(Vdc1+Vdc2+Vdc3) are summed and compared with the DC bus
reference voltage (Vdc*). The error of the signal at nth sampling
instant is given by:
Vd(n) = V*dc(n) - Vdc(n) (3)
The voltage error Vd(n) is then supplied to Proportional-
Integral controller to regulate the DC bus voltage of
DSTATCOM. At nth sampling instant, the output of the PI
controller is as:
Icd(n)=Icd(n-1)+kp{Vdcer(n)-Vdcer(n-1)}+kiVdcer(n) (4)
Where, Kp and Ki are proportional gain and integral gains of
the PI controller. Vdcer(n) and Vdcer(n-1) are the DC bus voltage
errors in nth and (n-1)th instant and Icd(n) and Icd(n-1) are the
amplitudes of active component of currents at the fundamental
reference current in nth and (n-1)th instant.
The average magnitude of current (ILP) and the output of the PI
controller (Icd) are summed up and transformed to Iα (reference
source current) from dq0 component and then compared with
the actual source current to produce error magnitude of current
and then supplied to a PWM controller to generate gating
pulses to the multilevel inverter.
SIMULATION RESULTS AND DISCUSSION
In this section, the proposed control algorithm is evaluated and
tested using MATLAB / Simulink on a single-phase
distribution system loaded with linear and non-linear loads.
Fixed time step of 20µs with ode3 (Bogacki - Shampine)
solver is chosen for simulation.
Few test cases are performed for evaluation of DSTATCOM
are: The performance of the controller when a linear load is
applied is shown in fig.5 when time t=0.4s to 0.5s. In Fig.6,
Non - linear load is applied from time t=1s to 2s and increase
in load from time t=2s to 3s is shown in Fig.7. A mixed load
(Linear and Non-linear load) is applied from time t=3s to 4s as
shown in Fig.8. All these test cases are performed under
sinusoidal grid conditions. The five-level and seven-level
results are shown and prove that the seven-level inverter is
found more effective with low total harmonic distortion. The
five-level inverter shows a staircase output across the inverter
whereas the seven-level inverter output is near sinusoidal. This
indicates that the filter capacity that is required is more for
five-level inverter compared to seven-level inverter. The
performance under dynamic conditions is found satisfactory.
The DC bus voltage regulation, reactive power and harmonic
compensation with power factor improvement shows the
effectiveness of the controller. A sinusoidal PWM strategy
was employed for gating the inverters. THD (%) of all the four
cases mentioned above are presented in table-I prove the
effectiveness of the controller.
CONCLUSION
In this paper, a simple and effective control algorithm based
on SRF theory and Inverse-Park based transformation based
PLL for single-phase five-level and seven-level cascaded H-
bridge inverters has been analyzed, compared and validated
using MATLAB / Simulink. This theory is adopted to work in
sinusoidal grid voltage conditions and Non-Linear load
conditions. The source current THD (%) is maintained within
IEEE 519-1992 limits in both the inverter configurations.
Seven-level inverter has proven more promising and reliable
compared to five-level inverter. Seven-level also reduces the
cost of additional filtering component that is required and low
rating DC bus capacitors can be used which makes the overall
cost low. The control algorithm is very promising and easy to
implement because of its simple structure and accuracy. The
harmonic compensation and power factor is effectively done
under all steady-state and dynamic conditions. The injected
current of the DSTATCOM was also very close to the
reference values and proved a smooth and reliable profile. The
DC link voltage is well balanced in seven-level converter
compared to five-level cascaded H-bridge Inverter. Therefore,
a Seven-level CHB is preferred for low to medium power
ratings at the distribution level.
Table-I
THD (%) of Test Cases (Table-I)
Five-level Seven Level
Fig No. Is IL Is IL
5 2.47 2.03 1.8 2.03
6 3.15 35.63 2.4 35.63
7 2.76 33.22 1.96 33.22
8 2.40 27.82 2.12 27.82
APPENDIX (Table-II)
Grid Voltage & Frequency Single-Phase, 230V, 50Hz
Source-side Impedance Rs=0.1 Ω, Ls =2.5mH
Non-linear: Single-phase
diode bridge rectifier
R=40Ω, L= 250mH,
Linear Load R=40 Ω, L=250mH
PWM Switching frequency 2kHz
Reference voltage of DC bus 400V
Interfacing inductor Lf=1.5mH
Gains of PI controller for DC bus Kp =0.32, Ki=6
International Journal of Applied Engineering Research ISSN 0973-4562 Volume 12, Number 16 (2017) pp. 5525-5531
© Research India Publications. http://www.ripublication.com
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Fig.5 Performance of CHB with Linear Load (5 and 7 Level CHB)
Figure 6: Performance of CHB with Non-Linear Load (5 and 7 Level CHB)
-350
0
350
-30
0
30
-10
0
10
-10
0
10
170
200
230
0.46 0.48 0.5 0.52 0.54 0.56 0.58 0.6 0.62 0.64
-350
0
350
Time (s)
Source Voltage (V)
Source Voltage (V)
Source Current (A)
Source Current (A)
Vdc1 (V)
Vdc2 (V)
DSTATCOM Voltage (V)
-10
0
10
Injected Current (A)
Load Current (A)
-350
0
350
-10
0
10
-1
0
1
-3
0
3
125
145
0.46 0.48 0.5 0.52 0.54 0.56 0.58 0.6 0.62 0.64
-350
0
350
-3
0
3
Time (Sec)
Source Voltage (V)
Source Current (A)
Source Current (A)
Load Current (A)
Inverter Voltage (V)
Scaled
Source Voltage (V)
Injected Current (A)
DC Link Voltage (V)
-350
0
350
-30
0
30
-20
0
20
-20
0
20
170
200
230
1.06 1.08 1.1 1.12 1.14 1.16 1.18 1.2 1.22 1.24
-350
0
350
Time (s)
Source Voltage (V)
Source Voltage (V)
Source Current (A)
Source Current (A)
Vdc1 (V)
Vdc2 (V)
DSTATCOM Voltage (V)
-20
0
20
Injected Current (A)
Load Current (A)
-350
0
350
-10
0
10
-101
-303
125
145
1.06 1.08 1.1 1.12 1.14 1.16 1.18 1.2 1.22 1.24
-350
0
350
-303
Time (Sec)
Source Voltage (V)
Source Current (A)
Source Current (A)
Load Current (A)
Inverter Voltage (V)
Scaled
Source Voltage (V)
Injected Current (A)
DC Link Voltage (V)
International Journal of Applied Engineering Research ISSN 0973-4562 Volume 12, Number 16 (2017) pp. 5525-5531
© Research India Publications. http://www.ripublication.com
5529
Figure 7: Performance of CHB with Increase in Non-Linear Load (5 and 7 Level CHB)
Figure 8: Performance of CHB with Linear and Non-Linear Load (5 and 7 Level CHB)
-350
0
350
-30
0
30
-20
0
20
-20
0
20
170
200
230
1.96 1.98 2 2.02 2.04 2.06 2.08 2.1 2.12 2.14
-350
0
350
Time (s)
Source Voltage (V)
Source Voltage (V)
Source Current (A)
Source Current (A)
Vdc1 (V)
Vdc2 (V)
DSTATCOM Voltage (V)
-20
0
20
Injected Current (A)
Load Current (A)
-350
0
350
-10
0
10
-303
125
145
1.46 1.48 1.5 1.52 1.54 1.56 1.58 1.6 1.62 1.64
-350
0
350
-303
Time (Sec)
Source Voltage (V)
Source Current (A)
Source Current (A)
Load Current (A)
Inverter Voltage (V)
Scaled
Source Voltage (V)
Injected Current (A)
DC Link Voltage (V)
-350
0
350
-30
0
30
-20
0
20
-20
0
20
170
200
230
2.96 2.98 3 3.02 3.04 3.06 3.08 3.1 3.12 3.14
-350
0
350
Time (s)
Source Voltage (V)
Source Voltage (V)
Source Current (A)
Source Current (A)
Vdc1 (V)
Vdc2 (V)
DSTATCOM Voltage (V)
-20
0
20
Injected Current (A)
Load Current (A)
-350
0
350
-10
0
10
-101
-303
125
145
2.06 2.08 2.1 2.12 2.14 2.16 2.18 2.2 2.22 2.24
-350
0
350
-303
Time (Sec)
Source Voltage (V)
Source Current (A)
Source Current (A)
Load Current (A)
Inverter Voltage (V)
Scaled
Source Voltage (V)
Injected Current (A)
DC Link Voltage (V)
International Journal of Applied Engineering Research ISSN 0973-4562 Volume 12, Number 16 (2017) pp. 5525-5531
© Research India Publications. http://www.ripublication.com
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REFERENCES
[1] IEEE Recommended Practices and Requirements for
Harmonic Control in Electrical Power Systems. ,
IEEE Std. 519, 1992.
[2] Electromagnetic Compatibility (EMC)—Part 3-2:
Limits—Limits for Harmonic Current Emissions
(Equipment Input Current=16 A per Phase), IEC
61000-3-2, 2005.
[3] Timbus, A., Liserre, M., Teodorescu, R. and
Blaabjerg, F., “Synchronization methods for three
phase distributed power generation systems: an
overview and evaluation,” IEEE PESC 2005, pp.
2474-2481, Jun. 2005.
[4] V. Kaura and V. Blasco, “Operation of a phase
locked loop system under distorted utility
conditions,” IEEE Trans. Ind. Appl., Vol. 33, no. 1,
pp. 58–63, Jan./Feb. 1997.
[5] Yada, Hareesh Kumar, and M. S. R. Murthy. "A new
topology and control strategy for extraction of
reference current using single phase SOGI-PLL for
three-phase four-wire Shunt Active Power Filter",
proc. 2014 IEEE International Conference on Power
Electronics Drives and Energy Systems (PEDES),
2014.
[6] Yada, Hareesh Kumar, and M. S. R. Murthy. "Phase
Locked Loop Techniques for power quality
improvement in polluted grids", Proc. 2016 IEEE
International Conference on Power Electronics,
Integrated Circuits and Energy Systems (ICPEICES),
2016.
[7] K. H. Law, M. S. A. Dahidah, and N. Marium,
“Cascaded multilevel inverter based STATCOM with
power factor correction feature,” in Proc. IEEE Conf.
Sustainable Utilization Develop. Eng. Technol., 2011, pp. 1–7.
[8] F. Z. Peng and J. S. Lai, “Dynamic performance and
control of a static Var generator using cascade
multilevel inverters,” IEEE Trans. Ind. Appl., vol. 33,
no. 3, pp. 748–755, Jun. 1997.
[9] Y. Cheng, Q. Chang, L. C. Mariesa, S. Pekarek, and
S. Aticitty, “A comparison of diode-clamped and
cascaded multilevel converters for a STATCOM with
energy storage,” IEEE Trans. Ind. Electron., vol. 53,
no. 5, pp. 1512–1521, Oct. 2006.
[10] R. Naderi and A. Rahmati, “Phase-shifted carrier
PWM technique for general cascaded inverters,”
IEEE Trans. Power Electron., vol. 23, no. 3, pp.
1257–1269, May 2008.
[11] W. Yao, H. Hu, and Z. Lu, “Comparisons of space-
vector modulation and carrier-based modulation of
multilevel inverter,” IEEE Trans. Power Electron.,
vol. 23, no. 1, pp. 45–51, Jan. 2008.
[12] J. Rodriguez, L. Moran, P. Correa, and C. Silva, “A
vector control technique for medium-voltage
multilevel inverters,” IEEE Trans. Ind. Electron., vol.
49, no. 4, pp. 882–888, Aug. 2002.
[13] G. Narayanan and V. T. Ranganathan, “Extension of
operation of space vector PWM strategies with low
switching frequencies using different overmodulation
algorithms,” IEEE Trans. Power Electron., vol. 17,
no. 5, pp. 788–798, Sep. 2002.
[14] S. Wei, B. Wu, F. Li, and C. Liu, “A general space
vector PWM control algorithm for multilevel
inverters,” in IEEE Appl. Power Electron. Conf.
Expo., vol. 1, Feb. 2003, pp. 562–568
[15] A. K. Gupta and A. M. Khambadkone, “A general
space vector PWM algorithm for multilevel inverters,
including operation in over modulation range,” IEEE
Trans. Power Electron., vol. 22, no. 2, pp. 517–526,
Mar. 2007.
[16] W. Yao, H. Hu, and Z. Lu, “Comparisons of space-
vector modulation and carrier-based modulation of
multilevel inverter,” IEEE Trans. Power Electron.,
vol. 23, no. 1, pp. 45–51, Jan. 2008.
[17] M. S. A. Dahidah and V. G. Agelidis, “Selective
harmonic elimination PWM control for cascaded
multilevel voltage source converters: A generalized
formula,” IEEE Trans. Power Electron., vol. 23, no.
4, pp. 1620–1630, Jul. 2008.
[18] B. Ozpineci, L. M. Tolbert, and J. N. Chiasson,
“Harmonic optimization of multilevel converters
using genetic algorithms,” in Proc. Power Electron.
Spec. Conf., 2004, pp. 3911–3916.
[19] V. G. Agelidis, A. Balouktsis, and M. S. A. Dahidah,
“A five-level symmetrically defined selective
harmonic elimination PWM strategy: Analysis and
experimental validation,” IEEE Trans. Power
Electron., vol. 23, no. 1, pp. 19–26, Jan. 2008.
[20] M. S. A. Dahidah and V. G. Agelidis, “Single-carrier
sinusoidal PWM-equivalent selective harmonic
elimination five-level inverter control,” Electr. Power
Syst. Res., vol. 78, no. 11, pp. 1826–1836, Jun. 2008.
[21] M. S. A. Dahidah, G. Konstantinou, and V. G.
Agelidis, “SHE-PWM and optimized DC voltage
levels for cascaded multilevel inverters control,” in
Proc. IEEE Symp. Ind. Electron. Appl., 2010, pp.
143–148.
[22] K. H. Law, M. S. A Dahidah, and V. G. Agelidis,
“SHE-PWM cascaded multilevel converter with
adjustable DC sources control for STATCOM
applications,” in Proc. IEEE 7th Int. Power Electron.
International Journal of Applied Engineering Research ISSN 0973-4562 Volume 12, Number 16 (2017) pp. 5525-5531
© Research India Publications. http://www.ripublication.com
5531
Motion Control Conf., 2012, pp. 330–334.
[23] Adepu Sateesh Kumar, K.Prakash, “Analysis of Split
Capacitor Based DSTATCOM with LCL Filter Using
Instantaneous Symmetrical Components Theory”
With an ISBN Number: 978-1-4673-9745-2 ©2016
IEEE explore (Ref. no. -37745) 2nd IEEE
International Conference (AEEICB-2016).
[24] Adepu Sateesh Kumar, K.Prakash, Dr.Swati Sharma,
“A Five-Level Cascaded DSTATCOM for Single-
Phase Distribution System”, National Conference &
Journal on Challenges and Issues in Operation of
Competitive Electricity Markets (CIOCEM-2016)
CPRI, Bangalore 2016.