PERFORMANCE EVALUATION OF LARGE RECONFIGURABLE INTERCONNECTS FOR MULTIPROCESSOR SYSTEMS Wim Heirman, Iigo Artundo, Joni Dambre, Christof Debaes, Pham Doan Tinh, Bui Viet Khoi, Hugo Thienpont, Jan Van Campenhout ISEE, HoChiMinh City, 24 October 2007 2 PERFORMANCE EVALUATION OF LARGE RECONFIGURABLE INTERCONNECTS FOR MULTIPROCESSOR SYSTEMS Wim Heirman, ISEE07 HoChiMinh City Abstract The interconnection network inside a multi- processor system has a very irregular load. Can we adapt this network to its (time-varying) demands? Yes, using (optical) reconfiguration technology. We show the resulting network speedup, obtained through system-level simulations. 3 PERFORMANCE EVALUATION OF LARGE RECONFIGURABLE INTERCONNECTS FOR MULTIPROCESSOR SYSTEMS Wim Heirman, ISEE07 HoChiMinh City Introduction to multiprocessor systems (DSM) and interconnection networks Reconfigurable Interconnects and Optical networks Simulation results on performance improvement Conclusions Outline 4 PERFORMANCE EVALUATION OF LARGE RECONFIGURABLE INTERCONNECTS FOR MULTIPROCESSOR SYSTEMS Wim Heirman, ISEE07 HoChiMinh City supercomputer on-chip server Multiprocessor Interconnects Multiprocessing is everywhere: supercomputers servers on-chip (multi-core) Processors need to communicate to solve a single problem Interconnection network becomes main system component Our focus: distributed shared- memory (DSM) servers 5 A DSM machine is made of: Nodes, each composed of: The processing unit Some levels of cache memory The local memory A network interface INTERCONNECTION NETWORK An interconnection network Architecture of a Distributed Shared-Memory system 6 PERFORMANCE EVALUATION OF LARGE RECONFIGURABLE INTERCONNECTS FOR MULTIPROCESSOR SYSTEMS Wim Heirman, ISEE07 HoChiMinh City Distributed Shared-Memory hierarchy Network is part of the memory hierarchy Remote memory access requires network communication Network latency is very influential on performance CPU MEM NetIF CPUMEM NetIF CPUMEM NetIF CPUMEM NetIF CPUMEM NetIF CPU MEM NetIF CPUMEM NetIF CPUMEM NetIF CPUMEM NetIF cache instruction: 0.5 ns cache: 5 ns DDR: 50 ns network: 500 ns 7 PERFORMANCE EVALUATION OF LARGE RECONFIGURABLE INTERCONNECTS FOR MULTIPROCESSOR SYSTEMS Wim Heirman, ISEE07 HoChiMinh City Introduction to multiprocessor systems (DSM) and interconnection networks Reconfigurable Interconnects and Optical networks Simulation results on performance improvement Conclusions Outline 8 PERFORMANCE EVALUATION OF LARGE RECONFIGURABLE INTERCONNECTS FOR MULTIPROCESSOR SYSTEMS Wim Heirman, ISEE07 HoChiMinh City Non-uniform network traffic in space and time => Reconfigurable network? CPUMEM NetIF CPUMEM NetIF CPUMEM NetIF CPUMEM NetIF CPUMEM NetIF CPUMEM NetIF CPUMEM NetIF CPUMEM NetIF CPUMEM NetIF time load Link #9 time load Link #13 Variable communication patterns time load Link #5 9 PERFORMANCE EVALUATION OF LARGE RECONFIGURABLE INTERCONNECTS FOR MULTIPROCESSOR SYSTEMS Wim Heirman, ISEE07 HoChiMinh City CPU MEM CPU MEM CPU MEM CPU MEM CPU MEM CPU MEM CPU MEM CPU MEM CPU MEM Base network (fixed) Extra links/elinks (reconfigurable) Proposed topology reconfiguration 10 PERFORMANCE EVALUATION OF LARGE RECONFIGURABLE INTERCONNECTS FOR MULTIPROCESSOR SYSTEMS Wim Heirman, ISEE07 HoChiMinh City Requirements: Reconfiguration intervals Selection and switching times Reconfiguration interval Traffic pattern locality