510 IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 37. NO. 4. DECEMBER 1988

Computer Flexible Multichannel for Data Acquisition of Low-Frequency Signals

Personal Interface

Abstract-In this paper we describe the structure and give the hard- ware/software implementation of a multichannel interface card which has been built and inserted into an empty slot of a personal computer (PC) with an IBM compatible bus, to enable the PC to perform the data acquisition and storage of signals to be measured. Because of the flexibility of components used in building the card, the user can select from the keyboard several operational parameters such as the sam- pling rate and number of samples to collect from every channel. Soft- ware to control card components are written in assembly language, while that for analyzing collected data is in a high level language. Channels work independently, and their combined sampling rate is limited mainly by the speed of the microprocessor used.

I. INTRODUCTION ITH THE increased processing and storage capa- bilities of personal computers (PC’s), this equip-

ment can be efficiently used to perform miscellaneous measurements, where dedicated equipment were used in the past for these purposes. The availability and the rapid development of modem algorithms in the area of digital signal processing makes it more desirable to replace an- alog signal measurement techniques by digital counter- parts and to be implemented on a PC. Although PC’s can provide needed resources to process and store the mea- sured signal and any intermediate information and display the results, they are often not capable of collecting data without the addition of other circuits to do some specific functions. After a major restructuring of its data acquisi- tion equipment, the Department of Aeronautics at the USAF has recently undertaken a program to incorporate microcomputer-based data acquisition systems where minicomputers were used in the past for this purpose [ 11. PC based data acquisition systems are also used in other applications (e.g., [2]).

In most physical systems, signals are available in ana- log form. However, a PC can process digital samples of the measured signal available in its internal memory. Hence, an interface hardware must be available to accept the analog input signal, convert it into a digital one, and to store it in the internal memory or in the secondary stor- age. In some applications, it is needed to measure more than one signal. In such cases, multichannel interface

Mmuscript received April 21, 1988. This work was supported by a re- search grant from the Jordan University of Science and Technology, Irbid, Jordan.

The authors are with the Department of Electrical Engineering, Jordan University of Science and Technology, Irbid, Jordan.

IEEE Log Number 8823634.

hardware is required. Since it is convenient to enable the user to select the sampling rate depending upon the band- width of the measured signal, we describe in this paper a simple but yet flexible interface which has these features.

11. INTERFACE HARDWARE DESIGN It is rather straightforward to propose an interface with

fixed specifications and capabilities, incorporating an an- alog-to-digital converter (ADC), a latch to save a digital sample until it gets transferred to the PC memory, and timing and control circuitry. Such an interface would comprise MSI/SSI integrated circuits, and the complexity of its control would increase as more flexibility is desired.

In this section we propose a particular design to the in- terface hardware, together with a possible implementa- tion. For this purpose we choose hardware components which are easily interfaced with the IBM PC bus. The suggested hardware was built on a prototype card for the IBM PC using a wire wrapping technique, and inserted into an empty slot inside the PC. The following are the main components of the interface and the integrated cir- cuits used in its implementation.

A . Analog Multiplexer The interface is multichannel, i .e., it allows data col-

lection from several input signals. Since we would like to use only one analog-to-digital converter, only one analog signal can be sampled and digitized at any one instant. Therefore, we use HEF405 1B 8-channel analog multi- plexer/demultiplexer which allows up to 8 input signals simultaneously. The particular input to be sampled is se- lected through software under the user control as will be shown next section.

B. Analog-to-Digital Converter Since physical signals are normally available in analog

form and these need to be processed digitally by the per- sonal computer, an analog-to-digital converter is needed. To provide reasonable accuracy for many applications, it is suggested to use a 12-bit ADC, and the chip AD574 is selected.

C. Programmable Peripheral Interfaces In order to read the digital samples given by the ADC,

a minimum of 12-bit buffer is needed to hold the data tem- porarily while the ADC is converting the next analog

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ELABDALLA AND ABU-EL-HAIJA: LOW-FREQUENCY SIGNALS

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sample; in addition, another buffer will be needed to hold some control lines. Other buffers are needed to receive signals generated from timers and to output control sig- nals going out to the timers. Rather than selecting normal latches (buffers), we propose using two programmable in- terface chips which provide some flexibility in the pro- posed data acquisition interface. It is to be noted that the costs of a normal latch and a programmable interface are roughly comparable. The Intel 8255 programmable pe- ripheral interface (PPI) is used because it is directly com- patible with the IBM PC bus signals.

D. Programmable Timers The sampling rates for different signals are determined

by the user and entered from the PC keyboard. In order to make the data acquisition interface independent of the clock rate used in the PC, and of the type of the micro- processor used (e.g., 8086, 8088, or 80286), one or more programmable timer units are used to generate pulses for controlling the ADC, thus : lowing selectable sampling rates for different channek. Three chips of Intel 8253 (programmable interval tin :r) are used allowing the pos- sibility to select up to eight different sampling intervals for eight channels, because each timer has three indepen- dent 16-bit interval counters.

E. Channel Service Register This register consists of eight J-K flip-flops, where each

flip-flop keeps the status of one channel. The flip-flops are normally clear, and a flip-flop is set when the correspond- ing channel needs service.

F. Crystal Clock The clock input to the timer is obtained from a clock

built on the interface card in order to make the timing completely independent of the PC used. This clock com- prises a 1-MHz crystal oscillator.

A complete block diagram of the interface is shown in Fig. 1. The analog multiplexer, ADC, PPI’s, and timers operate under software control as will be described in the next section. The interface between the PC bus and the programmable chips (the multiplexer, ADC, and timers) is done through the use of two PPI’s.

The operation of Fig. 1 is as follows. The 8 input an- alog signals are fed to the analog multiplexer. Depending upon the select input of the multiplexer, one signal will be input to the ADC. The control inputs of the ADC ( R / C , CE, Ao, CS) are set by the PC to their appropriate values at the time the desired channel is selected. When the ADC finishes conversion of this sample from the se- lected channel, it informs PPI-1 through the status line. The PC then reads the converted sample (a 12-bit quan- tity) through ports A and C of PPI-1 as described in the next section. The programmable interval timers are set initially by software to generate pulses at the appropriate instants according to the desired sampling intervals of up to 8 different channels. When a timer determines that a sample is to be taken from any channel, an ouput pulse is

PER I P H PC

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CLK INTERVAL PR SERVICE GENERATOR TIMERS REGISTER

CLK

GATES 1 MHz PROF CHANNEL CLOCK

Fig. 1 . Block diagram of personal computer flexible interface.

generated by this timer and sets one bit in the channel service register. The output of this register is immediately transferred to port B of PPI-1 which is continuously scanned by the PC. When the PC finds that a channel needs to be serviced, it writes a control word to port A of PPI-2, which in turn selects this channel through the mul- tiplexer, and also sets control signals of the ADC as men- tioned above. Note that the channel service register is necessary in order to change the pulse outputs of the tim- ers into level signals which are kept in PPI-1 until they are processed.

Fig. 2 shows a detailed schematic diagram of the inter- face card which was implemented. It is to be noted that three analog channels can be sampled using this imple- mentation, and the expansion to eight channels is straight- forward by the addition of two timer chips (Intel 8253) and two more chips of dual J-K flip-flop (7478) to in- crease the size of channel service register.

The analog multiplexer and the ADC are configured to process input signals in the range from - 5 V to +5 V. The eight data lines of PPI-1, PPI-2, and the timer are connected with the corresponding lines coming from the bus via a bi-directional 8-bit bus transceiver (74LS245). Lines controlling the PPI’s and timer (Ao, A , , ZOR, ZOW, RESET) are taken from the bus and buffered via an 8-bit line driver (74LS244).

The I/O addresses for the PPI’s and the timer are de- termined via SELECT lines coming from a simple address decoder (74LS138). The chips 74LS244, 74LS245, and 74LS138 are available on the prototype card used (which are commercially available). A picture of the card with the circuit of which it was built on, is shown in Fig. 3.

111. INTERFACE SOFTWARE DESIGN Two types of the components selected for the proposed

data acquisition interface card, namely, the peripheral in- terface and the timers, are programmable and need to be configured before the card can start its operation. More- over, the operation of the multiplexer and the ADC is

512 IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 31, NO. 4, DECEMBER 1988

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Fig. 2. Schematic diagram of the implemented interface.

Fig. 3. Picture of the card with the interface hardware.

controlled through software in order to select the channel to be sampled and the start and end of conversion. Also, since several parameters for the interface card can be set by the user through the PC keyboard, an interface pro- gram between the user and the card must be available. Finally, more software needs to be written if the card is to have more intelligence or when it is needed to be used in real-time signal measurements. The basic software needed can be divided into several modules (see Fig. 4).

A . Main Program and Menu This module interacts with the user, accepts from the

user the channels to be sampled, and the desired sampling rate for each channel. It then calls other modules to ini- tialize hardware and perform data collection. The col-

lected data are saved on disk to enable the user to display it, or perform required measurements or analysis.

B. Conjiguration of the P P I s The PPI has 24 input/output lines divided into three

groups (ports) called A, B, and C. Eight lines are in each port that can be programmed for either input or output [3]. All ports of PPI-1 are configured in mode 0 as input ports, while all ports of PPI-2 are configured in mode 0 as output ports.

C. Conjiguration of the Timers Each timer chip contains three independent 16-bit

counters, which hold the sampling intervals for three dif- ferent channels. The sampling interval is in microseconds

ELABDALLA AND ABU-EL-HAIJA: LOW-FREQUENCY SIGNALS 513

F E L E C T S CHANNELS AND SAMPLING RATES I

INIT PPI’s & TIMERS, AND START THOSE COUNTERS CORRESPONDING TO DESIRED CHANNELS

t t

SET UP SELECT INPUT LINES OF ANALOG MUX I I

I SEND START CONVERSION SIGNAL TO ADC I

FINISHED CONVERSION? 1 I

READ CONVERTED SAMPLE AND STORE IN MEMORY I

I STOP APPROPRIATE COUNTER I

NO

SAVE DATA ON DISK AND RETURN TO DOS

Fig. 4 . Flowchart of software implemented on the data acquisition inter- face.

because a 1-MHz crystal clock is used. This software module programs the timers as rate generators (mode 2) [3] to give a negative pulse at the end of every sampling interval which is held in the channel service register and sent to port B of PPI-1. Note that the output of every counter is forced high as long as its gate input is low, and the counter will start from the initial count when the gate input goes high. Thus the gate input is used to synchro- nize the counters. An out instruction is used to output a zero to port B of PPI-2 to stop all eight counters.

D. Data Collection

The counters were initialized to the sampling intervals of desired channels. The channel service register is cleared, and an output instruction is executed to start those counters corresponding to desired channels. Whenever a sampling interval is elapsed, its counter sets a flag in the channel service register. This register is continuously scanned by the CPU through port B of PPI-1. Once it is found that a channel needs service, the CPU writes to port A of PPI-2 a control word which determines the channel to be se- lected by the analog multiplexer, enables the ADC, and instructs the ADC to start conversion. The end-of-con-

version signal is sent from the ADC to pin ( P C , ) of PPI- 1 , which is monitored by the CPU. When this signal is received, the converted sample is read from ports A and C of PPI-1 and stored in the memory. If the maximum number of samples for this channel has been collected, the corresponding counter for this channel is forced high to prevent requests for more samples. This is accom- plished by writing a zero to the gate of this counter. If the gates of all counters are cleared (contain zeros), then no more samples will be collected. In this case, the collected data are saved on disk, and control is transferred to the operating system.

The hardware and software described above have been tested on various signals. Different waveforms were sam- pled and 400 samples from every waveform were saved on disk, and plotted later (without any processing) as shown in Fig. 5 .

IV. CONCLUSION

The design and hardware/software implementation of a flexible multichannel interface card has been described in this paper. This interface can be used for data acquisition on any IBM PC or compatible with an empty slot. This

5 I4 IEEE TRANSACTIONS ON INSTRUMENTATION A N D MEASUREMENT, VOL. 37, NO. 4, DECEMBER 1988

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interface allows for the collecting of data from up to eight input signals with independent sampling rates. The user has the option of selecting any combinations of the chan- nels to be used. The interface is based upon versatile and programmable integrated circuits which make the inter- face simple but flexible in its operation. By using this in- terface, several measurement methods (e.g., [4]) which would normally require dedicated equipments, can now be implemented on PC’s.

REFERENCES [ l ] V. M. Parisi 11, “Upgrading to a micro computer data acquisition sys-

tem,” in Proc. IEEE Instrumentation/Technology Conf., pp. 82-85, Apr. 1987.

[2] J . H. Posenau and B. J. Neilson, “A portable PC based data acquisi- tion system for water quality monitoring,” in Proc. IEEE Instrumen- tation/Technology Conf., pp. 93-96, Apr. 1987.

131 Intel Reference Manual and Data Sheets, Intel Corporation, Santa Clara, CA, 1983.

[41 A. I . Abu-El-Haija and A. M. Elabdalla, “Frequency determination of weak sinusoids buried in noise,” IEEE Trans. Instrum. Meas., vol. IM-36, pp. 971-974, Dec. 1987.