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Published by WS 0763 BG CD Customer Service Printed in the Netherlands Subject to modification EN 3122 785 16940
© Copyright 2007 Philips Consumer Electronics B.V. Eindhoven, The Netherlands.
All rights reserved. No part of this publication may be reproduced, stored in a
retrieval system or transmitted, in any form or by any means, electronic,
mechanical, photocopying, or otherwise without the prior permission of Philips.
Colour Television Chassis
LC7.1ELA
H_16940_000.eps080307
ME7
Contents Page Contents Page1. Technical Specifications, Connections, and Chassis
Overview 2
2. Safe ty Inst ruct ions, Warnings, and Notes 6
3. Directions for Use 8
4. Mechanical Instructions 9
5. Service Modes, Error Codes, and Fault Finding 16
6. Block Diagrams, Test Point Overview, and
Waveforms
Wiring Diagram 32” 27
Wiring Diagram 37”-42” 28Block Diagram Supply 29
Block Diagram Video 30
Block Diagram Audio 31
Block D iagram Cont rol & C lock S igna ls 32
Test Point Overview SSB (Bottom Side) 33
I2C IC’s Overview 34
Supply Lines Overview 35
7. Circuit Diagrams and PWB Layouts Diagram PWB
SSB: DC/DC (B02) 36 52-61
SSB: Tuner & Demodulator (B03A) 37 52-61
SSB: Micro Processor (B04A) 43 52-61
SSB: Video Processor (B04B) 44 52-61
SSB: PNX2015: Audio Processor (B04C) 45 52-61
SSB: YPBPR & Rear IO (B06A) 46 52-61
SSB: I/O Scart 1 & 2 (B06B) 47 52-61SSB: HDMI (B06C) 48 52-61
SSB: Headphone Amp & Muting (B06D) 49 52-61
SSB: Audio (B07) 50 52-61
SSB: SRP List 51 52-61
Side A/V Panel (D) 62 63
Keyboard Control Panel (E) 64 65
Front IR / LED Panel (J) 66 67
8. Alignments 69
9. Circuit Descriptions, Abbreviation List, and IC Data
Sheets 73
Abbreviation List 80
IC Data Sheets 83
10. Spare Parts List 88
11. Revision List 92
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Technical Specifications, Connections, and Chassis OverviewEN 2 LC7.1E LA1.
1. Technical Specifications, Connections, and Chassis Overview
Index of this chapter:
1.1 Technical Specifications
1.2 Connection Overview
1.3 Chassis Overview
Notes:
• Figures can deviate due to the different set executions.
• Specifications are indicative (subject to change).
1.1 Technical Specifications
1.1.1 Vision
Display type : LCD
Screen size : 32” (82 cm), 16:9
: 42” (107 cm), 16:9
Resolution (HxV pixels) : 1366 x 768
Min. contrast ratio : 4000:1 (32”)
: 5000:1 (42”)
Min. light output (cd/m2
) : 500Typ. response time (ms) : 8 (32”)
: 5 (42” )
Viewing angle (HxV degrees) : 178x178
Tuning system : PLL
TV Colour systems : PAL B/G, D/K, I
: SECAM B/G, D/K, L/L’
Video playback : NTSC
: PAL
: SECAM
Suppor ted computer fo rmats : WXGA (1366x768)
Supported video formats : 640x480i - 1fH
: 720x576i - 1fH
: 640x480p - 2fH
: 720x576p - 2fH
: 1920x1080i - 2fH: 1280x720p - 3fH
Presets/channels : 100 presets
Tuner bands : VHF
: UHF
: S-band
: Hyper-band
1.1.2 Sound
Sound systems : NICAM D/K, I, L/L’
: 2CS D/K, B/G
Equalizer : 7-bands
Maximum power (WRMS) : 2 x 10
1.1.3 Miscellaneous
Power supply:
- Mains voltage (VAC) : 220 - 240
- Mains frequency (Hz) : 50 / 60
Ambient conditions:
- Temperature range (°C) : +5 to +40
- Maximum humidity : 90% R.H.
Power consumption (values are indicative)
- Normal operation (W) : ≈ 140 (32”)
: ≈ 240 (42”)
- Stand-by (W) : < 1
Dimensions (WxHxD cm) : 80.5x54.6x11.5 (32”)
: 104.5x68.6x11.6 (42”)
Weight (kg) : 15.5 (32”)
: 25 (42”)
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Technical Specifications, Connections, and Chassis Overview EN 3LC7.1E LA 1.
1.2 Connection Overview
Figure 1-1 Side and rear I/O connections
Note: The following connector colour abbreviations are used
(acc. to DIN/IEC 757): Bk= Black, Bu= Blue, Gn= Green, Gy=
Grey, Rd= Red, Wh= White, and Ye= Yellow.
1.2.1 Side Connections
EXT3: Headphone - Out
Bk - Headphone 32 - 600 ohm / 10 mW
EXT3: Cinch: Video CVBS - In, Audio - In
Rd - Audio R 0.5 VRMS / 10 kohm Wh - Audio L 0.5 VRMS / 10 kohm Ye - Video CVBS 1 VPP / 75 ohm
EXT3: S-Video (Hosiden): Video Y/C - In
1 -Ground Y Gnd
2 -Ground C Gnd
3 - Video Y 1 VPP / 75 ohm
4 -V ideo C 0.3 VPPP / 75 ohm
1.2.2 Rear Connections
EXT1: Video RGB - In, CVBS - In/Out, Audio - In/Out
Figure 1-2 SCART connector
1 -Audio R 0.5 VRMS / 1 kohm
2 -Audio R 0.5 VRMS / 10 kohm
3 -Audio L 0.5 VRMS / 1 kohm
4 -Ground Audio Gnd
5 -Ground Blue Gnd 6 -Audio L 0.5 VRMS / 10 kohm 7 -Video Blue 0.7 VPP / 75 ohm
8 -Function Select 0 - 2 V: INT
4.5 - 7 V: EXT 16:9
9.5 - 12 V: EXT 4:3
9 -Ground Green Gnd
10 - Easylink P50 0 - 5 V / 4.7 kohm
11 - Video Green 0.7 VPP / 75 ohm
12 -n .c.
13 - Ground Red Gnd
14 - Ground P50 Gnd
15 -Video Red 0.7 VPP / 75 ohm
16 - Status/FBL 0 - 0.4 V: INT
1 - 3 V: EXT / 75 ohm 17 - Ground Video Gnd
18 - Ground FBL Gnd
19 -Video CVBS 1 VPP / 75 ohm
20 -Video CVBS 1 VPP / 75 ohm
21 -Shield Gnd
EXT2: Video YC - In, CVBS - In/Out, Audio - In/Out
Figure 1-3 SCART connector
1 -Aud io R 0 .5 VRMS / 1 kohm 2 -Aud io R 0 .5 VRMS / 10 kohm
3 -Aud io L 0 .5 VRMS / 1 kohm
4 -Ground Audio Gnd
5 - n.c.
6 -Aud io L 0 .5 VRMS / 10 kohm
7 -C -out 0.7 VPP / 75 ohm
8 -Function Select 0 - 2 V: INT
4.5 - 7 V: EXT 16:9
9.5 - 12 V: EXT 4:3
9 - n.c.
10 - Easylink P50 0 - 5 V / 4.7 kohm
11 -n .c.
12 -n .c.
13 -n .c.
14 - Ground P50 Gnd
15 -C 0 .7 VPP / 75 ohm
16 - Status/FBL 0 - 0.4 V: INT
1 - 3 V: EXT / 75 ohm
17 - Ground Video Gnd
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21
20
1
2
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21
20
1
2
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Technical Specifications, Connections, and Chassis OverviewEN 4 LC7.1E LA1.
18 - Ground FBL Gnd
19 -Video CVBS 1 VPP / 75 ohm 20 - Video CVBS/Y 1 VPP / 75 ohm
21 -Shield Gnd
Service Connector (UART)
1 -UART_TX Transmit
2 -Ground Gnd
3 -UART_RX Receive
Aerial - In
- -IEC-type (EU) Coax, 75 ohm
Service Connector (ComPair)
1 - SDA-S I2C Data (0 - 5 V) 2 - SCL-S I2C Clock (0 - 5 V)
3 -Ground Gnd
HDMI 1 & 2: Digital Video, Digital Audio - In
Figure 1-4 HDMI (type A) connector
1 -D2+ Data channel
2 -Shield Gnd
3 -D2- Data channel
4 -D1+ Data channel
5 -Shield Gnd
6 -D1- Data channel 7 -D0+ Data channel
8 -Shield Gnd
9 -D0- Data channel
10 - CLK+ Data channel 11 -Shield Gnd
12 - CLK- Data channel 13 -n .c.
14 -n .c.
15 - DDC_SCL DDC clock
16 - DDC_SDA DDC data
17 -Ground Gnd
18 -+ 5V
19 - HPD Hot Plug Detect
20 -Ground Gnd
EXT4: Cinch: Video YPbPr - In, Audio - In
Gn -Video Y 1 VPP / 75 ohm
Bu - Video Pb 0.7 VPP
/ 75 ohm
Rd - Video Pr 0.7 VPP / 75 ohm Wh - Audio L 0.5 VRMS / 10 kohm
Rd - Audio R 0.5 VRMS / 10 kohm
1.3 Chassis Overview
Figure 1-5 PWB/CBA locations (32” models)
19 1
18 2
E_06532_017.eps250505
G_16860_047.eps310107
B
POWER SUPPLY UNIT
DSIDE I/O PANEL
SMALL SIGNALBOARD
JLED PANEL
ECONTROL BOARD
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Technical Specifications, Connections, and Chassis Overview EN 5LC7.1E LA 1.
Figure 1-6 PWB/CBA locations (42” models)
H_16940_008.eps
050307
B
POWER SUPPLY UNIT
DSIDE I/O PANEL
SMALL SIGNAL
BOARD
JLED PANEL
ECONTROL PANEL
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Directions for UseEN 8 LC7.1E LA3.
3. Directions for Use
You can download this information from the following websites:
http://www.philips.com/support
http://www.p4c.philips.com
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Mechanical Instructions EN 9LC7.1E LA 4.
4. Mechanical Instructions
Index of this chapter:
4.1 Cable Dressing
4.2 Service Positions
4.3 Assy/Panel Removal
4.4 Set Re-assembly
Notes:
• Figures below can deviate slightly from the actual situation,
due to the different set executions.
• Follow the disassemble instructions in described order.
They apply to the 32” sets.
4.1 Cable Dressing
Figure 4-1 Cable dressing (32” models)
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310107
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Mechanical InstructionsEN 10 LC7.1E LA4.
Figure 4-2 Cable dressing (42” models)
H_16940_009.eps
050307
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Mechanical InstructionsEN 12 LC7.1E LA4.
Figure 4-5 Keyboard control panel
4.3.3 Side I/O Panel
1. Remove the rear cover, as described earlier.
2. Unplug connector [a].
3. Remove screws [b] and remove the complete module. One
of the screws is T10 tapping, the other one is T10 parker.
See fig. “Side I/O module”.
4. Remove T10 parker screw [c]. See fig. “Side I/O panel 1”.
5. Push catch [d] (located at the underside of the bracket) and
slide the unit to the right from its bracket [e]. See fig. “Side
I/O panel 2”.
6. To remove the PWB from its bracket, you have to lift the
catch [f] loacted on top of the headphone connector. At the
same time, slide the PWB out of its bracket [g]. See fig.
“Side I/O panel 3”.
When defective, replace the whole unit.
Figure 4-6 Side I/O module
Figure 4-7 Side I/O panel [1/3] top side
Figure 4-8 Side I/O panel [2/3] bottom side
G_16850_007.eps
090207
1
1
2
3
G_16860_066.eps010207
a b (1x)
b (1x)
G_16860_075.eps010207
c
G_16860_076.eps010207
2d
2e
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Mechanical Instructions EN 13LC7.1E LA 4.
Figure 4-9 Side I/O panel [3/3]
4.3.4 IR/LED Panel
1. Remove the rear cover, as described earlier.
2. Refer to fig. “IR/LED panel“ below.
3. Unplug connector(s) [1].
4. Release clip [2] and remove the board.
When defective, replace the whole unit.
Figure 4-10 IR/LED panel
4.3.5 Mid-range Speakers
1. Remove the rear cover, as described earlier.
2. Refer to fig. “Mid-range speakers“ below.
3. Unplug connectors [1].
4. Remove T10 parker screws [2].
Figure 4-11 Mid-range speakers
4.3 .6 Tweeters
1. Remove the rear cover, as described earlier.
2. Refer to fig. “Tweeters” below.
3. Unplug connectors [1].
4. Remove T10 parker screws [2].
Figure 4-12 Tweeters
4.3.7 Small Signal Board (SSB)
1. Remove the rear cover, as described earlier.
2. Refer to fig. “SSB removal“ below.
3. Disconnect all cables [a] on the SSB.
4. Remove the T10 tapping screws [b] that hold the SSB. See
Figure “SSB removal”.
5. Remove the screws that hold the CINCH and HDMI
connectors at the connector panel.
6. Lift the SSB from the set.
Figure 4-13 SSB removal
G_16860_077.eps010207
2g f
G_16850_009.eps110107
1
2
G_16850_010.eps110107
2 1 2
G_16850_011.eps110107
2 1
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a a
b (2x)b (3x)
b (3x)
b (2x)
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Mechanical InstructionsEN 14 LC7.1E LA4.
4.3.8 Main Supply Panel
1. Remove the rear cover, as described earlier.
2. Refer to fig. “Main supply panel“ below.
3. Unplug cables [a].
4. Remove the fixation screws [b].
5. Take the board out (it hinges at the left side).
Figure 4-14 Main supply panel
4 .3.9 LCD Panel
1. Remove the rear cover, as described earlier.
2. Refer to fig. “LCD panel“ below.
3. Unplug the connectors on the Main Supply Panel [a] and
the LED & IR board [c].
4. Unplug the outer connectors [d] from the mid-range
loudspeakers.
5. Do NOT forget to unplug the LVDS connector [e] from the
SSB. Important: Be careful, as this is a very fragileconnector!
6. Remove T10 parker screw [b] that holds the Side I/O
module bracket.
7. Remove T10 parker screws [f] of the central sub-frame.
8. Remove LCD panel fixation screws [g] and lift the complete
central sub-frame from the set (incl. the PSU, SSB, and
Side I/O boards and wiring).
9. Lift the LCD panel [7] from the front cabinet.
Figure 4-15 LCD panel [1/2]
G_16860_065.eps010207
aa
a
b (3x)
d d
a
e
G_16860_067.eps310107
c (1x)
g (2x)
f (3x)
f (2x)
f (1x)
g (2x)
b
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Mechanical Instructions EN 15LC7.1E LA 4.
Figure 4-16 LCD panel [2/2]
4.4 Set Re-assembly
To re-assemble the whole set, execute all processes in reverseorder.
Notes:
• While re-assembling, make sure that all cables are placed
and connected in their original position. See figure "Cable
dressing".
• Pay special attention not to damage the EMC foams.
Ensure that EMC foams are mounted correctly (one is
located above the LVDS connector on the display, between
the LCD display and the metal sub-frame).
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S i M d E C d d F lt Fi di EN 17LC7 1E LA 5
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Service Modes, Error Codes, and Fault Finding EN 17LC7.1E LA 5.
Display Option Code Selection
When after a display exchange, the display option code is not
properly set, it will result in a TV wi th “no display”. Therefore, it
is required to set this display option code after such a repair.
To do so, press the following key sequence on a standard RC
transmitter: “062598” directly followed by MENU and “xxx”,
where “xxx” is a 3 digit decimal value of the panel type (see first
column in table “Display Code Overview” or sticker on the side/
bottom of the cabinet). When the value is properly acceptedand stored in NVM, the set will switch to Stand-by, to indicate
that the process has been completed successfully.
Figure 5-1 Location of Display Option Code sticker
During this algorithm, the NVM-content must be filtered,
because several items in the NVM are TV-related and not SSB-
related (e.g. Model and Prod. S/N). Therefore, “Model” and
“Prod. S/N” data is changed into “See Type Plate”.
In case a call centre or consumer reads “See Type Plate” in
CSM mode, he needs to look to the side/bottom sticker to
identify the set, for further actions.
Table 5-1 Display option code overview
PHILIPS
MODEL:
32PF9968/10
PROD.SERIAL NO:
AG 1A0620 000001
040
39mm
2 7 m m
(CTN Sticker)
Display OptionCode
E_06532_038.eps290107
Display
option HEX
Display
type Brand Size
Vert.
resolution
Hor.
resolution Type number 12 NC
045 2D LCD LPL 26 768p 1366 LC260WX2-SLB2 9322 234 13682
046 2E LCD LPL 32 768p 1366 LC320W01-SL06 9322 230 03682
068 44 LCD CMO 26 768p 1366 V260B1-L03 9322 249 37682
069 45 LCD CMO 32 768p 1366 V315B1 L05 9322 248 65682070 46 LCD CPT 32 768p 1366 CLLAA320WB02P 9322 245 31682
071 47 LCD LPL 37 768p 1366 LC370WX1-SLB1 9322 246 96682
072 48 LCD AUO 37 768p 1366 T370XW02V5 9322 249 77682
073 49 LCD LPL 42 768p 1366 LC420WX3-SLA1 9322 246 97682
076 4B LCD AUO 42 768p 1366 T420XW01V8 9322 249 10682
083 53 PDP SDI 42 768p 1024 S42AX-YD04(PS-426-PH) 9322 246 76682
085 55 PDP SDI 50 768p 1366 S50HW-YD05(PS-506-PH) 9322 246 81682
091 5B LCD AUO 32 768p 1366 T315XW02VD 9322 249 06682
093 5D LCD LPL 42 1080p 1920 LC420WU2-SLA1 9322 246 84682
103 67 LCD LPL 20 480p 640 LC201V02-SDB1 9322 242 65682
105 69 LCD CMO 19 900p 1440 TPM190A1-L02 9965 000 43654
106 6A LCD AUO 23 768p 1366 T230XW01V3 9322 249 79682
107 6B LCD LPL 42 768p 1366 LC420WX5-SLD1 9322 249 09682
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Service Modes, Error Codes, and Fault FindingEN 22 LC7.1E LA5.
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Table 5-4 Error code overview
Notes
1. Some of the error codes reported are depending on the
option code configurations.
2. This error means: no I2C device is responding to the
particular I2C bus. Possible causes: SCL/SDA shorted to
GND, SCL shorted to SDA, or SCL/SDA open (at uP pin).
The internal bus of the Trident platform should not cause
the entire system to halt as such an error can be reported.
5.4.4 How to Clear the Error Buffer
The error code buffer is cleared in the following cases:
• By using the CLEAR command in the SAM menu:
– To enter SAM, press the following key sequence on the
remote control transmitter: “062596” directly followed
by the OSD/i+ button (do not allow the display to time
out between entries while keying the sequence).
– Make sure the menu item CLEAR is selected. Use the
MENU UP/DOWN buttons, if necessary.
– Press the MENU RIGHT button to clear the error
buffer. The text on the right side of the “CLEAR” line will
change from “CLEAR?” to “CLEARED”
• If the contents of the error buffer have not changed for 50
hours, the error buffer resets automatically.
Note: If you exit SAM by disconnecting the mains from the
television set, the error buffer is not reset.
Error
code1) Description
Item
nr. Remarks
0 No error.
1 DC Protection of
speakers.
2 +12V protection error. 12V missing or "low".
3 Reserved.
4 General I2C error. note 2
5 Trident Video
Processor
communication error.
7202 When Trident IC is
defective, error 10
and 14 might also be
reported. Trident
communicates via
parallel bus, not via
the I2C bus. The I2C
bus of Trident is only
used in ComPair
mode.
6 I2C error while
communicating with
the NVM.
7315 The TV will not start-
up due to critical dta
not available from the
NVM, but the LED
will blink the error
code.
7 I2C error while
communicating with
the Tuner.
1101
8 I2C error while
communicating with
the IF Demodulator.
7113
9 I2C error
communicating with
the Sound Processor.
7411
10 SDRAM defective. 7204
11 I2C error while
communicating with
the HDMI IC.
7817
12 I2C error while
communicating with
the MOJO PNX8314.
7G00 if applicable
13 DVB HW
communication error.
7F01,
7K00,
7G00
if applicable
14 SDRAM defective. 7205
15 Reserved.
16 Reserved.
17 Reserved.
18 I2C error while
communicating withthe iBoard processor.
if applicable
19 I2C error while
communication with
1080p bolt-on module.
if applicable
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Service Modes, Error Codes, and Fault FindingEN 24 LC7.1E LA5.
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Figure 5-7 Start-up flowchart
AC ON
Start Up
M16C RST_H = HIGHRST_HDMI = LOWRST_AUD = LOWRESET_n = LOW
LCD_PWR_ON = LOWSDI PDP => CTRL_DISP1 = LOW
M16C RST_H to LOWRST_HDMI = HIGHRST_AUD = HIGHRESET_n = HIGH
RENEAS POR by +3VSTBY (2)STANDBYn = LOW
+5VSTBY & +3V3STBY Available (1)
Initialise Trident CXBL_ADJ = HIGH (100% Duty Cycle)
DPTVInit( )
LCD_PWR_ON = HIGH(Same function as CTRL-DISP2)SDI PDP => CTRL_DISP1 = LOW
For LCD:BL_ON_OFF = HIGH
* BL_ADJ keep 100% for 3000ms before dimming.
Switch ON LVDS Signal
Wait for 20 ms
Init. Warm Component(For software)
Initialise IF Demodulator, AfricTDA9886T
Initialise Tuner
Initialise HDMI, Sil9023
Initialise MicronasMute Audio
Initialise FHP Panel* For FHP PDP Sets only
Initialise Bolt-ON* For iTV, 1080P, Ambi Light
Last status is ON?
End
Wait for RC key orWake up event
20ms
STANDBYn = HIGH(Same function as CTRL-DISP3)
Is Power Down =HIGH?
Enable Power Down INTEnable DC_PROT INT
Wait for 500ms
Wait for 100msTime out = 2000ms
NoError 2
[Protection]
Wait for 100ms
Blank PicturePicture Mode Setup & Detection
Error 5 -Trident[Protection]
Yes
DVB recording mode
No
YesWP for NVM
STANDBYn = LOW
StandbyNormal Mode
Recording Mode finished
Software Shutdown:
LED = BLUE for Normal modeLED = RED for Recording mode
User wake up the setsin DVB recording mode
BLOCK RC Key
Enable RC Key
Yes
Error 7
Error 8
Error 9
Error 11
Error 3[Protection]
Standby Normal Mode(RED LED)
1000ms to1500ms
500ms
100ms
1700ms
SDI PDP => CTRL_DISP1 = HIGH
For DVB Sets only (Semistandby)Recording mode
Notes:
---------
1. LC07 TV software only start communication with IBOZ oncereceive the INT message from IBOZ.
160ms
Port Assignment in STANDBY
Port Assignment in STANDBY
unBlank Picture &UnMute Audio
Read NVM completed.STOP I²C activities.
InitCold Component:1. Check SDM port.
-I f SDM pin = LOW and NVM first 20Byte =0xFF, reload Software default NVM value.2. Check Panel port.-I f Panel Pin = LOW and check slave address 0x65 = 0xA5, Enter Panel Mode.
Error 6 -NVM[Protection]
Error 10 – SDRAM 7204[Protection]
Error 14 – SDRAM 7205[Protection]
Error 19 –1080P
Error 17 – AmbiLight
Error 18 – iTV iFace
For PDP:3000ms delay
No
(2) to be measured at pin 4 of BD45275G (item 7312)
(1) +5VSTBY to be measuredat PDTC114ET (item 7322)
G_16860_070.eps220207
Service Modes, Error Codes, and Fault Finding EN 25LC7.1E LA 5.
http://-/?-http://-/?-http://-/?-http://-/?-
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Figure 5-8 Semi Stand-by/Stand-by flowchart
SEMISTANDBY/ STANDBY Start
Mute Audio
WriteProtect for NVM
STANDBYn = LOW
Software Shutdown:
BL_ON_OFF = LOW
Wait 300ms
Switch OFF LVDS
Wait 20ms
LCD_PWR_ON = LOW
End
LED = NO LED
for Standby soft mode
Standby using
“power key”LED = RED No
Yes
For DVB Sets only (Semistandby)
SDI PDP => CTRL_DISP1 = HIGH
Off Air Downloading/ Recording Mode
IBOZ send shut down command
BL_ADJ stop dimming
(PWM duty cycle 100%)
Port Assignment in STANDBY
300ms
20ms
Total = 360ms
40ms
Wait for 3000ms
Sets go to standby here
Blocking for the next start up to ensure
power supply discard properly.
Disable Power Down INT &
DC_PROT_INT
Wait for 3000ms
Except power tact switch
BL_ADJ = LOW
(PWM duty cycle 0%)
G_16860_071.eps
220207
Service Modes, Error Codes, and Fault FindingEN 26 LC7.1E LA5.
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Figure 5-9 Power Down & DC_PROT flowchart
Start
WriteProtect for NVM
Mute Audio & VIdeo
Power Down INT:AC OFF or Transient INT
DC_PROT INT
STANDBYn = LOW
Wait 5000 ms
Re-start: Start up
End
No
Notes:1. Power Down INT will be based on fall edge triggering2. +3V3STBY will stay for 15ms, software must perform
WriteProtect for NVM within 15ms.
Poll the Power DownINT for 5 times
End
Avoid false trigger
Start
Mute Audio & VIdeo
No
End
Avoid false trigger
is DC_PROT = LOWfor 3 sec?
Log Error Code
STANDBYn = LOW
WriteProtect for NVM
Error 1[Protection]
End
Yes
Yes
G_16860_072.eps220207
Block Diagrams, Test Point Overview, and Waveforms 27LC7.1E LA 6.
6. Block Diagrams, Test Point Overview, and Waveforms
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Wiring Diagram 32”
1304
11P
1G51
30P
1735
4P
1M20
7P
1C01
9P
1 3 0 4
1 1 P
C N 1
2 P 3
INLET
C N 7
8 P
C N 2
1 4 P
C N 3
1 2 P
WIRING 32” LCD (STYLING ME7)
C N 2
1 4 P
RIGHT SPEAKER LEFT SPEAKER
B SSB
D SIDE I/O
8304
8C01
8735 8735
8521
8520
8 0 0 2
C N 6
9 P
LVDS
30P
1P11
8P
8P11
8G51
SUPPLY
INVERTER
8 1 9 1
8 1 9 2 ( U K )
(1005)
(1116)
LCD DISPLAY(1004)
28LC7.1E LA 6.Block Diagrams, Test Point Overview, and Waveforms
Wiring Diagram 37”-42”
WIRING 37”- 42” LCD (STYLING ME7)
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1304
11P
1G51
30P
1735
4P
1M20
7P
1C01
9P
C N 1
2 P 3
INLET
X403
12P
X404
14P
WIRING 37 42 LCD (STYLING ME7)
C N 2
1 4 P
RIGHT SPEAKER LEFT SPEAKER
B SSB
8735
8521
8520
8 0 0 2
LVDS
30P
1P11
8P
8G51
SUPPLY
INVERTER
X406
8P
X412
9P
8C01
8P11
8 1 9 1
8 1 9 2 ( U K )
(1005)
LCD DISPLAY(1004)
Block Diagrams, Test Point Overview, and Waveforms 29LC7.1E LA 6.
Block Diagram Supply
SUPPLY 32” LCD
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CN1
CN2
DISPLAY SUPPL1. +24V
2. +24V3. +24V4. +24V
5. +24V6. GND7. GND
8. GND9. GND
10. GND11. DIM12. BL-ON13. PWM
14. N.C.
PRIMARY SIDE
AC-IN
SUPPLY 32” LCD
CN3
DISPLAY SUPPLY1. +24V2. +24V
3. +24V4. +24V5. +24V
6. GND7. GND
8. GND9. GND10. GND11. N.C.
12. N.C.
SECONDARY SIDE
CN6
CONTROL:
1. BL-DIM
2. PG3. BL-ON
4. GND5. N.C.6. PSON
7. N.C.8. 12V.
CN7
CONTROL1. -12VA
2. +12VA3. GND4. 5.2VS5. 5.2VS6. 5.2VS7. GND
8. GND.9. GND
220 - 240V
50/60Hz
30LC7.1E LA 6.Block Diagrams, Test Point Overview, and Waveforms
Block Diagram Video
VIDEOB04B
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ADC
HDMIB06C
YPBPR & REAR IOB06A
IO - SCART 1 & 2B06B
VIDEO PROCESSORB04B
SIDE FACING SIDE AVD MICROPROCESSORB04A
TUNER IF & DEMODULATORB03A
ANALOG
MUX
1
5
4
1102
SIF1
SIF2
VIF1
VIF2
23
24
1
2
17CVBS
DEMODULATOR
7113TDA9886T/V4
2
4
1304 1304
2
4
1
5S VIDEO
24
3
1301
1302
FRONT_C_IN
FRONT_Y_CVBS_IN
IF_ATV
VIDEO
1101TD1318S/A
MAIN
TUNER
11IF_OUT3
14
1
VIF1
VIF2
1
5
4
1103SIF1
SIF2
1504
20
11
15
21
1
2x SCART
19
7
EXT1
CVBS_RF
1633535 EF
7503
189
1506
20
15
19
EXT2
EF
7114
SC1_B_IN
SC1_G_IN
SC1_R_IN
SC1_CVBS_IN
181
197
SC2_Y_CVBS_IN
SC2_C_IN
SC2_CVBS_MON_OUT
198
1615
Y
Pr
Pb
188
180
196
1 9
1
1 8
2
1
1810
3
4
7
9
10
12
6
19
RX2+A
RX2-A
RX1+A
RX1-A
RX0+A
RX0-A
RXC+A
RXC-A
2x HDMICONNECTOR
7814
HDMI_HOTPLUG_RESETB04A
7817
SII9025CTU
182
192
FRONT_Y_CVBS_IN_T
FRONT_C_IN_T
HDMI(MAIN)
VIDEOPROCESSOR
2
3
52
51
48
47
44
43
40
39
+
-R0X2
+-
R0X1
+
-R0X0
+
-R0XC
HDMI_H
HDMI_VVSYNC
HSYNC
121 HDMI_VCLKODCK 23
8 SC1_STATUS
16 SC1_FBL_IN
8 SC2_STATUSB04A
HD_Pr_IN
HD_Y_IN
HD_Pb_IN
CVBS_OUT1
Y_G2
PB_B3
FB1
PB_B2
120114M31
205
204
XTALI
XTALO
173
B04A
1DE
1 9
1
1 8
2
1
1811
3
4
7
9
10
12
6
19
RX2+B
RX2-B
RX1+B
RX1-B
RX0+B
RX0-B
RXC+B
RXC-B
7860
HDMI_HOTPLUG_RESETB04A
71
70
67
66
63
62
59
58
+
-R1X2
+
-R1X1
+
-R1X0
+
-R1XC
HDMI_Cb(0-7)
HDMI_Y(0-7)
HDMI_Cr(0-7)
HDMI_DE
7202SVP CX32-LF
4
5
6
DP_HS
DP_HS
DP-CLK
DP_DE_FLD
7I
7I
DQ(0-31)
CX_MA
TXCn
TXCp
TXCLKn
TXCLKp
TXDn
TXDp
TXAp
TXBn
TXBp
TXAn51
50
49
48
45
44
43
42
41
40
TA1
TB1
TC1
TCLK1
TD1
SC1_RF_OUT_CVBS
PR_R2
162
190PR_R3
FS2
CVBS_OUT2
70
Y_G1
PB_B3
PR_R1
Y_G3
C
RF_AGC
169CVBS1
MEMORY
8-BIT
SINGLE
LVDS TX
DIN_PORTD(24BIT)
SOUND TRAPS4.5 to 6.5 Mhz
VIF-PLL
SINGLE REFERENCE QSS MIXER
INTERCARRIER MIXER ANDAM-DEMODULATOR
TUNER AGC VIF AGC
TAGCSIF AGC
I2C-BUS TRANSCEIVER
MAD
S C L
S D A
SUPPLY
+5VS
(16-31)
(0-15)
(0-11)
(0-11)
3528
3523
3516
3545
3528
3518
3522
3529
3552
3550
3537
EF
7500
3521
3617
3618
3619
4120
+VTUN
9
3111
15
11044M0
Block Diagrams, Test Point Overview, and Waveforms 31LC7.1E LA 6.
Block Diagram Audio
AUDIOAUDIOB07AUDIO PROCESSORB04CTUNER IF & DEMODULATORB03A
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HEADPHONE AMP & MUTINGB06D
AUDIOB07
HDMIB06C
I0 - SCART 1 & 2B06B
AUDIO PROCESSORB04C
YPBPR &REAR IOB06A
MICROPROCESSORB04ASIDE FACING SIDE AVD
TUNER IF & DEMODULATORB03A
15
4
1102
23
24
1
2
12
6
1304 1304
6
8 8
IF-ATV
1101TD1318S/A
MAINTUNER
11IF_OUT3
14RF_AGC
1
VIF1
VIF2
1 5
4
1103SIF1
SIF2
1504
6
2
1
21
1
2xSCART
3
EXT1
7411MSP4450P-VK-E8 000 Y
SIF 50
33
SC1_AUDIO _OUT_L
SC1_AUDIO_IN_R
SC1_AUDIO _OUT_R
SC1_AUDIO_IN_L
53
34
52
1302
48
49
1 9
1
1 8
2
2x HDMICONNECTOR
7817SII9025CTU
HDMI
27
26
SOUNDPROCESSOR
+
-RX2
+
-RX1
+
-RX0
+
-RXC
58SC5-IN-R
L_FRONT_IN
R_FRONT_IN
ANA-IN1+
SC2-OUT-R
SC2-IN-R
SC2-OUT-L
SC2-IN-L
DACM-L
DACM-R
1506
6
2
1
3
EXT2
SC1_AUDIO _OUT_L
SC2_AUDIO_IN_R
SC2_AUDIO _OUT_R
SC2_AUDIO_IN_L
36SC1-OUT-R
53SC1-IN-R
37SC1-OUT-L
54SC1-IN-L
AUDIOL/R IN
SIDE_AUDIO_IN_L_CON
SIDE_AUDIO_IN_R_CON
RXxxA
1615
COMP_AUDIO_IN_L
COMP_AUDIO_IN_R
AUDIOL/R IN
7810UDA1334ATS/N2
HDMI_AUDIO_IN_L
HDMI_AUDIO_IN_R
57SC5-IN-L
50SC3-IN-L
51SC3-IN-R
AUDIO-LS
AUDIO-LS
HDMI_I2S_SCK 186
HDNI_I2S_WS 285
HDMI_I2S_SD 384
877
BCK
WS
DATAI
MUTE
SCK
WS
SD0
MUTE
AUDIODAC
7901
HP_AUDIO_OUT_L
HP_AUDIO_OUT_R
MUT
ANTI_PLOP
1 9
1
1 8
2
RXxxB
14
16
VOUTL
VOUTR
SC1_AUDIO _MUTE_R
SC1_AUDIO _MUTE_L
SC2_AUDIO _MUTE_R
SC2_AUDIO _MUTE_L
B06D
B06D
B06D
B06D24
23
DACA-L
DACA-R
COMP_AUDIO_IN_L
COMP_AUDIO_IN_R
SC4-IN-L
SC4-IN-R
CONT
POWER_DOWN
STANDBY
MUTEn
B04A
B04A
B04A
B04A
4CL
7DA1
5 WS
SIF1
SIF2
VIF1
VIF2
CVBS
DEMODULATOR
7113TDA9886T/V4
SOUND TRAPS4.5 to 6.5 Mhz
VIF-PLL
SINGLE REFERENCE QSS MIXERINTERCARRIER MIXER AND
AM-DEMODULATOR
TUNER AGC VIF AGC
TAGCSIF AGC
I2C-BUS TRANSCEIVER
MAD
S C L
S D A
SUPPLY
12SIOMAD
+5VS
7109
B04ASAW_SW
6 1 0 3
141118M432
67
68
XTALIN
XTALOUT
+VTUN
9
311115
1104
4M0
SUPPLY +5V_D
+8V
+5V_AUD
12
13
38
40
39
32LC7.1E LA 6.Block Diagrams, Test Point Overview, and Waveforms
Block Diagram Control & Clock Signals
VIDEO PROCESSOR
B04B
CONTROL & CLOCK SIGNALS
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MICROPROCESSORB04A
KEYBOARD CONTROLE
IR/LED/LIGHT-SENSORJ
HDMIB06C
1G51
18
18
93
95
87
7311M30300SAGP
MICROPROCESSOR
KEYBOARD
LED1
IRSENSOR
RC
1M20 1M20
6 6
3 3
4 4
7011
+5V2_STBY
70103010
6010
LED1BLEU
+5V2-STBY3012
1M01
2
1M01
2
7 7
1011
1012
1013
1014
1015
1016ON / OFF
CHANNEL -
VOLUME +
VOLUME -
CHANNEL +
MENU
LED2
70126011
LED2RED
+5V2-STBY3013
LED1
LED2
REMOTE
KEYB
25 4301SDM3361 3
3 6 6
+3V3_STBY
130110M
13
11
7202SVP CX32-LF
VIDEOPROCESSOR
7204IS42S16400D-6TL
DRAM1Mx16x4
7205IS42S16400D-6TL
DRAM1Mx16x4
DQ(0-31)
CX_MA(0-11)
+
-R0
HDMI_Cb(0-7)
HDMI_Y(0-7)
HDMI_Cr(0-7)
1 9
1
1 8
2
2x HDMICONNECTOR
RXxxA
1 9
1
1 8
2
RXxxB
7817SII9025CTU
+
-R1
37
38
37
38
112
111CX_MCLK
CX_CLKE
HDMI_CCLK121 23
TXCLKn43 TXCLKn1
20TXCLKP42 TXCLKP1TO DISPLAY
(LVDS)
1312
6ITV_SPI_CLK9
ITV_CONNECTOR A
21 1 LIGHT_DENSORN.C.
91SC1_STATUSB06B
90SC2_STATUSB06B
89 HDMI_HOTPLUG_RESETB06C
88 RST_AUDB04C
3 STANDBYnB04B
7322 STANDBY
B07
B02 B06D
4 RST_HB04B
100 E_PAGE
7315M24C64-WMN6P
EEPROM
8Kx8
7
99 LCD_PWR_ONB04B
19 DCC_RESETB06C
5ITV_SPI_DATA_IN8
23 SAW_SWB03A
21 DVB_SWB03A
36RST
102
78 MUTEnB06D
75 BL_ON_OFFB02
74 ANTI_PLOPB06D
72 POWER_DOWN B6D
71DC_PROTB07
104HDMI_INTB06C
H_16940_003.eps270207
7310M29W800DT
EPROM
1Mx8512Kx16 A(0-19)
AD(0-7)
A(0-7)
AD(0-7)
86 4RST_H
56 18INT
61 45CS
63 42RD
62 44WR
84 38ALE_EMU
CPU_RST12
10
26
48
CE
1 1 2 8
7312BD45275G
4
(3V3)VOUT
2,3
+3V3_STBY
5
Block Diagrams, Test Point Overview, and Waveforms 33LC7.1E LA 6.
Test Point Overview SSB (Bottom Side)A110 E5A115 E5A116 E5A124 E5
F126 E7F127 E7F128 D5F129 D5
F218 A4F219 A5F220 A5F221 A5
F304 A3F305 B4F309 B4F310 A4
F324 B4F325 A3F326 B3F327 A3
F341 B3F342 F7F343 F7F344 F6
F361 B4F362 A4F363 B5F364 B5
F386 A5F387 A3F401 B3F402 C3
F522 D2F523 D2F524 D2F525 C3
F540 D3F541 D3F542 D2F543 E1
F613 E1F614 F2F615 F5F616 F3
F870 F3F871 F4F872 F4F873 F3
FA04 A2FA05 A3FA06 A3FA07 A1
FB19 D7FB20 C8FB21 A8FB22 A8
FC26 A6FC27 A6FC28 A6FC29 A6
FF24 C10FF25 F8FF26 E7FF27 F8
FG20 C10FG21 C10FG24 C9FG25 C9
FG40 C9FG41 C9FG42 C10FH00 B9
FJ25 F9FJ26 C8FJ27 C9FK01 F9
FK20 D9FK21 E9FK22 E9FK23 E9
FK37 E9FK38 D9FK39 E9FK40 E9
FK54 D8FK55 E8FK56 E8FK57 E8
FK74 D9FK75 E9FK80 D10FK81 F10
I114 E5I118 E5I120 E5I121 E7
I137 I138 I139 I141
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3139 123 6261.1
A124 E5A125 E5F111 E5F112 E7F114 E7F115 F6F116 F6F117 F6F118 E6F119 E6F120 E6F121 E6F122 E6F123 D6
F129 D5F130 D5F131 E6F132 E7F133 E6F134 F7F140 D5F210 A5F211 C4F212 A4F213 A4F214 A4F215 A4F217 A4
F221 A5F222 A4F223 A4F224 A4F225 A4F226 A4F227 A4F228 A4F229 A4F230 A4F231 C4F232 B4F302 B3F303 C4
F310 A4F311 B4F312 A3F313 B4F314 A3F315 B3F316 A3F317 B4F318 A3F319 B3F320 A3F321 B3F322 A3F323 A3
F327 A3F328 B3F329 B3F330 A5F331 B3F332 B3F333 B3F334 B3F335 B3F336 A3F337 A3F338 B4F339 B4F340 B3
F344 F6F345 C7F346 B5F347 B5F348 B5F349 B5F350 B5F351 A3F352 A4F353 B5F354 B5F356 A5F357 A3F360 A3
F364 B5F365 B5F366 B3F367 A4F368 A3F369 B4F370 F7F379 A4F380 A4F381 B4F382 A3F383 A3F384 A3F385 A4
F402 C3F403 C4F510 E2F511 E3F512 E1F513 E2F514 E1F515 E3F516 D2F517 D2F518 D1F519 E2F520 D2F521 D2
F525 C3F526 C3F527 C2F528 C2F529 C1F530 C2F531 D3F532 D2F534 E3F535 E3F536 E2F537 E2F538 D3F539 D2
F543 E1F544 D1F601 F5F602 F5F603 E5F604 F5F605 F1F606 F2F607 F2F608 F2F609 F2F610 F6F611 F5F612 F1
F616 F3F801 E3F802 E3F805 D3F806 E3F832 F4F840 F4F841 F4F842 F4F843 F4F850 F4F851 E4F861 F3F869 F3
F873 F3F874 F4F875 E3F876 D3F877 E4F901 B2F902 B2F903 B1F904 C2F905 B1F908 B2F910 B2FA01 A3FA02 A2
FA07 A1FA08 A1FA09 B3FA10 A1FA11 A1FA12 A3FA32 A2FB10 B8FB11 C4FB13 C6FB14 E6FB15 A8FB16 C8FB17 D6
FB22 A8FB23 A8FB24 A8FB25 A8FB26 A8FB27 B6FB28 A9FB29 A7FB30 A8FB31 A7FB32 A6FB33 A6FB34 A6FC25 A7
FC29 A6FF10 C8FF11 E8FF12 F8FF13 F7FF14 F8FF16 E7FF17 E8FF18 E7FF19 E8FF20 E7FF21 F7FF22 E8FF23 E7
FF27 F8FF28 E7FF29 E7FF30 E7FG10 B10FG11 B10FG12 B10FG13 D10FG14 C10FG15 B10FG16 B10FG17 C10FG18 B10FG19 C10
FG25 C9FG26 C10FG27 C9FG28 C9FG29 C8FG30 B9FG31 B10FG32 C10FG33 B10FG34 C10FG35 C10FG36 C10FG37 B9FG39 C9
FH00 B9FH01 D9FH02 B10FH03 B10FH04 B10FH05 D10FH06 D9FH07 C8FH08 D10FJ01 D9FJ02 F9FJ22 C9FJ23 C9FJ24 F9
FK01 F9FK02 F10FK05 D8FK06 E9FK10 E9FK11 E9FK12 D9FK13 E9FK14 E9FK15 E9FK16 D9FK17 E9FK18 E9FK19 E9
FK23 E9FK24 D9FK25 E9FK26 E9FK27 E9FK28 D9FK29 E9FK30 E9FK31 E9FK32 E9FK33 E9FK34 D9FK35 E9FK36 E9
FK40 E9FK41 E8FK42 D9FK43 E9FK44 E8FK45 E8FK46 D8FK47 E8FK48 E8FK49 E8FK50 D8FK51 E8FK52 E8FK53 E8
FK57 E8FK58 D8FK59 E8FK60 E8FK61 E8FK62 E10FK63 E8FK67 E10FK68 E10FK69 E10FK70 D10FK71 E10FK72 E10FK73 E9
FK81 F10FK82 F9FK83 D9FK84 F9FL20 A2FL21 A2FL22 A2FL23 A2FL24 A2FL25 A2FL26 A2I110 E5I111 E7I112 E5
I121 E7I122 F6I123 E6I124 D5I125 D5I126 D5I127 D5I128 D5I129 D5I130 D5I131 D5I133 D5I135 D5I136 D4
I141 I142 I143 I144 I145 I146 I147 I210 I211 I213 I214 I215 I216 I217
34LC7.1E LA 6.Block Diagrams, Test Point Overview, and Waveforms
I2C IC’s Overview
I²CMICROPROCESSORB04A B06C AUDIO PROCESSORB04CHDMI
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VIDEO PROCESSORB04B
IIC_SDA_up
IIC_SCL_up
28
7311M30300SAGP
MICROPROCESSOR
27
27 28
+3V3_STBY
3 3 7 9
3 3 7 7
IIC_SDA
IIC_SCL
3 8 9 7
3 8 9 6
3382
3378
BOLT_ON_SDA
BOLT_ON_SCL
33
34
3354
3356
1 9
1
1 8
2
2x HDMICONNECTOR
1810
16
15
7850M24C02
EEPROM
5 6
DOC_SDAA
DOC_SCLA
SDA2
SCL2
RXD0
TXD0
PROT04 3 2
7411 MSP4450P
SOUNDPROCESSOR
3 4 1 1
3 4 1 0
+3V3_STBY
3 3 5 1
3 3 5 2
1 9
1
1 8
2
181116
15
DOC_SDAB
7817SII9025CTU
HDMICONTROL
7811M24C02
EEPROM
5 6
DOC_SCLB
31
32
29
30
1G51
27
293246
3247
ERR11
7851-7852
7812-7813
ERR09
1314
1
3
COMPAIRSERVICE
CONNECTOR
2
3343
3345
1311
1
3
UARTCONNECTOR
(FOR DEVELOPMENT ONLY)
2
3L09
3L08
+3V3_STBY
3 L 0 7
3 L 0 6
29
30
TXD1
RXD1
5 6
7315 M24C64
EEPROM(NVM)
3 3 5 7
3 3 5 5
ERR06
7320
7321
+3V3_SW
3 3 8 8
3 3 0 5
(LVDS CONNECTOR)
(NOT STUFFED)
7310
M29W800DT
EPROM
1Mx8512Kx16A(0-19)
AD(0-7)
+5V_SW +3V3_SW
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36LC7.1E LA 7.Circuit Diagrams and PWB Layouts
7. Circuit Diagrams and PWB Layouts
SSB: DC/DC
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36/92
COM
OUTIN
COM
OUTIN
COM
OUTIN
COM
OUTIN
FB
OUT
COMP
VREFVCC
INH
SYNC
GND GND_HS
DC - DC
ITV Connector
R E S
R E S
ONLY FOR LCD
LCDPDP
4C55 / 4C56 / 4C61 / 4C624C57 / 4C58 / 4C59 / 4C60
RES
R
E S
RES
R E S
R E S
R E S
R E S
T O / F R O M P S U
5V2
-12V2
+12V2
T O / F R O M P S U2V9
2V8
1V60V(5V)
0V(5V)
(---V) MEASURED IN STANDBY
*********
1 2 3 4 5 6 7
1 2 3 4 5 6 7
A
B
C
D
E
F
LD1117DT33C7B02
1 0 n
2 C 6 1
1 0 n
2 C 6 0
1 0 0 n
2 C 5 9
4C60
4C62
4C59
4C61
FB34
5B1122u
22u5B10
IB20
IB18
IB19
FB33FB32
FB30
FB31
FB29FB28FB27
FB25FB23 FB26FB24
FB21
5 B 0 6
FB22
6 8 u
1 0 K
3 B 1 9
5B05
33u
2
C 5 8
1 n 0
4C01
+5V_SW4C57
4C58
4C56
4C55
GNDSNDGNDSND
+5V_STANDBY
FC28
FC29
FC27
FC26
FC25
2 C 5 6
1 n 0
1 n 0
2 C 5 7
2 C 5 5
1 n 0
-AUDIO_POWER
+AUDIO_POWERGNDSND
7
8+12V_DISP
+5V_STANDBY
12
345
6
8
9
B8B-PH-K-S
1P11
1
234
5
67
1C01
B9B-PH-K
1B11
123
4 5
B3B-PH-SM4-TBT(LF)
6K8
3B18
IB15
3 B 1 0
IB14
GNDTUN
2 B 2 0
1 0 0 p
1 K 0
3 B 1 5
6 B 0 3
B A V 9 9
5 B 0 4
1 0 0 u
7B032N7002
2 2 0 R
3 B 1 3
2 B 1 6
1 0 0 n
2 B 2 5
3 B 1 1
4 K 7
5B03
33u
1 0 0 n
2 B 1 7
2 B 1 3
IB17
FB15
FB10
IB12
6 K 8
3 B 1
7
3
5 V
4 u 7 2
B 2
2
2 3
+5V_SW
+5V_STANDBY
5 6 7 8
4
17B05
SI4423DY
S S 2 4
470R
3B12
6 B 0 1
+5V_SW
1 %
1 K 0 3
B 1 4
IB11
IB13
2 B 1 4
2 2 0 p
2 B 1 5
2 2 n
GNDDC
10u
5B01
2 B 1 2
2 2 u
4
5
7
9
31
2
8 6
L5973D
7B01
Φ
+5V_SW
+5V_SW
FB20
2 B 2 6 1
6 V
1 0 u
FB19
FB16
1 0 u 2
B 2 3 1
6 V
1 6 V
FB17
+3V3_STBY
+5V_SW
1 0 u 2
B 2 1
FB13
LD1117DT7B08
1
3 2
1
3 2
4 7 u
7B06LD1117DT33C
2 B 1 8
1 0 u 1 6 V
1 6 V
2 B 2 4
LD1085D2T337B04
1
3 2
+5V_STANDBY
1
3 2
POWER_DOWN
STANDBY
BACKLIGHT_BOOST
BL_ADJUST
BL_ON_OFF
STANDBY
B02
3139 123 6261.1
Item E U - L
C D
E U - P
D P
E U i T V -
L C D
DescriptionRLOC02MP7U4V53MSPACLE22B2
RLOC02MPU01V61MSPACLE32B2
RLOC02MPU01V61MSPACLE62B2
LOC5MP8K63060MSTSR71B3
LOC5MP8K63060MSTSR81B3
LOC50R0.PMUJ3060MSTSR55C4
LOC50R0.PMUJ3060MSTSR65C4
LOC50R0.PMUJ3060MSTSR75C4
LOC50R0.PMUJ3060MSTSR85C4
LOC50R0.PMUJ3060MSTSR95C4
LOC50R0.PMUJ3060MSTSR06C4
LOC50R0.PMUJ3060MSTSR16C4
LOC50R0.PMUJ3060MSTSR26C4
R)HSIV(50B7
R)00TS(C33TD7111DLMSCI60B7
R)00TS(TD7111DLMSCI80B7
Circuit Diagrams and PWB Layouts 37LC7.1E LA 7.
SSB: Tuner & Demodulator
TUNER IF & DEMODULATOR
1 2 3 4 5 6 7 8 9 10
B03A
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COM
OUTIN
IO2ISWIO1
GND
I
O2IGND
O1
GND
4X1
G4
4X2
1
2
VDD
VEEVSS
MTMT
SIFAGC
AFC DETECTOR
PORTS
INTERCARRIER MIXER ANDAM-DEMODULATOR
I C-BUS TRANSCEIVER2
RC VCO
NARROW-BAND FM-PLL
DIGITAL VCO CONTROL
SOUND TRAPS4.5 to 6.5 Mhz
AUDIO PROCESSING
MAD
TUNER AGC VIF AGC
SUPPLYOUTPUT
VIF-PLL
SINGLE REFERENCE QSS MIXER
AND SWITCHES
DEMODULATOR
RES
RES
DEMODULATOR
TUNERSAW FILTERS
DVB ONLY
41104111
4112
4113
4114
4115
4116
4117
4118
4119
R E S
R E S
RESERVED
40.4MHz
Trap
3113/4110 & 2110/4111at same position
RES
4120
4121
4122
4123
4124
ONLY FOR ANALOG TV
RES
RES
RESRES
RESRES
RES
RES
1V3
1V3
4V9
4V3
2V
2V
2V
2V
0 V
2V1
1V5
2 V 1 2
V 3
* *
*
*
** ****
*
*
* *
*
*
*
*
1 2 3 4 5 6 7 8 9 10
A
B
C
D
E
F
G
H
I
I131
7109BC847B
5121 120R
5120 120R
I147I146
50V10u2151
I145
5118
220R+12V_DISP
1 0 0 n
2 1 4 8
3 3 0 n
2 1 4 7
47R
3137
3
47R
3136
7133L78M05CDT
2
1
1 u
0
2 1 4 6
3 1 3 5
1 5 R
I143 I144
I142
+5V_IF
I141
3134
1R0
1R0
3133
2 1 4 4
1 0
n
1 n
0
2 1 4 3
2 1 4 5
1 n
0
51
51
10
10
220R5112
I139F140
I138
I136
I137
+5V_IF
7132BSH111
4K73132
BSH1117131
31314K7
+5V_IF
F132
50V214210u
1K03130
5117
RES
4124
5u6
5116
2 1 3 5
1 5 p
1 5 p
2 1 3 4
I110
I112
1 8 0 R
3 1 2 6
A116
A115
F112
F130
41114110
I123
F134
I121
F 1 1 5
F 1 1 6
2 1 2 8
1 0 n
1 u
0
2 1 1 5
2 1 1 6
1 u
0
F111
21143p3
2111
68p
2110
220p
3113
47R
3
4 5 6
7
8
5110
1 2
A125
A124
1 5 0 R
3 1 2 5
+5VS
BC847B7114
4
3
1 5
F114
38M9
1102
OFWK3953M
4 1 2 3
OFWK9656M
1103
38M9
3
1 54
F 1 2 3
F 1 2 2
F 1 2 1
F 1 1 9
F 1 2 0
F 1 1 8
I120
F 1 1 7
I114
I118
+5V_IF
6K83116
2 K 2
3 1 1 7
2117
10n
5113
RES
10n
2113
2120
22u
15p2121
4122
4121
4 1 1 6
212215p
100n2119
+5V_SW
S C L
4
S D A
5 6
X T A L
_ O U T4112
I F_
A G C
9
I F_
O U T 1
8
I F_
O U T 2
1 0
1 1
I F_
O U T 3
12
1314
15
R F
_ A G C
2
TUNER
7
+ 5 V
C S
3
D C
_ P W R
1
TD1316AF/IHP-2
1101
4120
+VTUN
4113
4 1 1 8
4 1 1 9
4 1 1 7
4 1 1 5
5
14
15
4
4 1 1 4
9
1 6
7 8
13
1
3
12
2
74HCT4053D7111
MDX 6
11
10
F 1 2 7
F 1 2 6
3120 10R
F133
I122
3121 10R
10n
2118
A110
+5V_IF
31182K2
6 1 0 3
5111390n
1 S S 3 5 6
3119
22K
312218K
I130
I128
I129
I125
I133
+5VS
F128
+5V_SW
9
T O P
V A G C
1 6
1 VIF1
2 VIF2
1 9
V P L L
2 0 V p
O P 2
1 5
R E F
1 1 S C L
1 0 S D A
2 3 S IF 1
2 4 S IF 2
1 2 S I O M A D
1 4
T A G C
A G N D
8AUD
17CVBS
5DEEM
7 D G N D
4 F M P L L
1 3 N C
3 O P 1
2 2
TDA9886T/V47113 2
1
A F C
6AFD
1 8
2136
470n
10n
2133
3127
5K610n
2137
390p
2139
I 1 2 6
I 1 2 7
I135
I124
2141
2140100R
100R3129
10n
3128
2138
2 2 p
4M0
1104
2 1 2 7
330R
3123
1n5
2123
2 1 2 5
4 7 0 n
2 2 0 n
2 1 2 6100R
22n
2124
3124
+12V_DISP
CVBS_RF
SAW_SW
SIF1
IF_ATVVIF2VIF1
SIF2
VIF2
VIF1
SIF2
SIF1
SIF
RF_AGC
IIC_SCL
IIC_SDA
B03A
3139 123 6261.1
38LC7.1E LA 7.Circuit Diagrams and PWB Layouts
SSB: DVB - Demodulator (Not implemented in this chassis)
DVB - DEMODULATOR
1 2 3 4 5 6 7 8 9
B03B
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M P E G - T S ( P A R A L L E L )
I 2 C
M P E G - T S ( S E R I A L )
M P E G - T S ( S E R I A L )
J T A G
NC
1
NC
1
COFDMCHANNEL DECODER
3V2
1V3 1V6
3V2
1V3 1V6
2V8
1V3
1V5
1V5
0V7
0V6
2V3
3V2
4V6
4V6
5V
5V
2V22V2
2V2
2V22V2
2V22V2
2V2
1V7
1V3
0V
0V
2V2
3V3
3V3
3V2
TDA10046AHT
1 2 3 4 5 6 7 8 9
A
B
C
D
E
F
G
IF32
+3V3FE
FF14
FF12
FF30
FF11
FF29
FF27
FF19
FF25
FF13
FF17
FF10
+5V_SW
+3V3
+5V_SW
+5V_SW
+5V_SW
+3V3FE
10K
3F33
IF1274AHC1GU04GW
2
3 1
54
330R
7F03
3F12
220K3F17
330R
3F14
680K
3F15
IF11
+3V3
74AHC1GU04GW2
3 1
54
7F02
390R
3F16
220K3F13
330R
3F10
680K
+3V3FE
+3V3FE
3F11
+5V_SW +5V_SW
+1V8S_SW
+5V_SW
+5V_SW +5V_SW
IF18 IF17
2F16100n
FF16
FF20
FF24
FF18
FF21
33R
3F30
10p
2F33
1 0 0 n
2 F 3 0
4 K 7
3 F 2 3
I
4F11
100n
2F27
3F24
100K
5
67
8
4
4
LM393D
7F04-2
LM393D
7F04-1
3
21
8
FF28
FF26
FF22
IF10
IF13
IF16IF154F12
IF14
1K0
4K7
3F20
100n
3F26
2F29
3F48 100R
100R3F46
3F44 100R
100R3F40
100n2F26
6 8 0 K
100n2F28
1 0 0 K
3 F 2 2
3 F 2 7
4K7
3F19
100K
3F25
100K
3F28 3F29
100K
FF23
2F31
IF19
2F32 100n
100n
2K7
3F41 3F42
2K7
2F15100n100n
2F14
2 F 1 2
1 0 0 n
2F17100n
2F19100n100n
2F13
2F23100n
1 0 0 n
2 F 2 2
3F18
10K
V S S A
_ O S C
V S S A
_ O S C
V S S
_ P L L
_ A D C
V S S
_ P L L
_ A D C
58
XIN54
XIN
55XOUTXOUT
7
V S S 1
15
V S S 2
V S S 2
V S S 3
24
V S S 3
29
V S S 4
V S S 4
V S S 5
V S S 5
40
V S S 6
45
V S S 6
V S S 7
52
V S S 7
63
V S S A
_ A D C
V S S A
_ A D C
56
V D D E 3 3
_ 2
V D D E 3 3
_ 2
V D D E 3 3
_ 3
V D D E 3 3
_ 3
475
V D D I 1 8
_ 1
V D D I 1 8
_ 1
V D D I 1 8
_ 2
V D D I 1 8
_ 2
22
V D D I 1 8
_ 3
42
V D D I 1 8
_ 3
50
V D D I 1 8
_ 4
V D D I 1 8
_ 4
VIM61
VIM
VIP62
VIP
V S S 1
TRST
UNCOR33
UNCOR
V D D 1 8
_ P L L
_ A D C
59
V D D 1 8
_ P L L
_ A D C
64
V D D 3 3
_ A D C
V D D 3 3
_ A D C
V D D A 1 8
_ O S C
53
V D D A 1 8
_ O S C
V D D A 1 8
_ P L L
57
V D D A 1 8
_ P L L
60
V D D A 3 3
_ A D C
V D D A 3 3
_ A D C
19
V D D E 3 3
_ 1
V D D E 3 3
_ 1
34
S_PSYNCS_PSYNC
S_UNCORS_UNCOR27
TCKTCK18
TDI17
TDI
TDO20
TDO
TEST12
TEST
16TMSTMS
TRST14
SADDR1SADDR1
SCLSCL6
SCL_TUNSCL_TUN3
SDA8
SDA
4SDA_TUNSDA_TUN
30S_DENS_DEN
32S_DOS_DO
S_OCLKS_OCLK31
28GPIO021
GPIO1GPIO123
GPIO225
GPIO2
GPIO3GPIO326
OCLK37
OCLK
PSYNC35
PSYNC
SACLK51
SACLK
SADDR011
SADDR0
10
DO241
DO2
DO3DO34344
DO4DO4
DO5DO546
DO648
DO6DO7
49DO7
ENSERI13
ENSERI
GPIO0
7F01
AGC_IF2
AGC_IF
AGC_TUNAGC_TUN1
9CLR_CLR_
DEN36
DEN
DO038
DO0
DO139
DO1
4MHZ_CLK
FE_LOCK
COMP_OUT
IF_AGC_IBO
4MHz_MOJO
I2C_TDA_SCL
I2C_TDA_SDA
VIP_IBO
VIM_IBO
RF_AGC_IBO
I2C_LOCAL_SDA
I2C_LOCAL_SCL
RES
RES
RESET_FE_n
COMP_OUT
B03B
3139 123 6261.1
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40LC7.1E LA 7.Circuit Diagrams and PWB Layouts
SSB: DVB - Mojo (Not implemented in this chassis)
(SDR0
DVB-MOJO0V
RES
1 2 3 4 5 6 7 8 9 10 11
FG10
FG11 FG13
4
ROW_21G01-2
21
3
ROW_11G01-1
3G18 10K
FG12
10K3G38
3G19 10K 113
7G0PNX83
SDRAM_DATA(0:15)
MOJO_TDI
MOJO_TRST
SDRAM_DATA(0)B03D
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2
AVDD
1
2
IDUMP
(PWR)
VDDC
VDDP
VSSC
VSSP
0
1
TS_DATA
(TS)01
23
4
56
7
TS_VAL
TS_STROBE
TS_SYNC
Y
C
CVBS
G
R
SD_OUT
SCK_OUT
WS_OUT
SPDIF
FSCLK
Y
CVBS
CVBS
Y
C
(AV)
B
8
9
10
11
12
13
14
15
1
2
3
4
5
6
7
SDRAM_DATA
S
0
45
6
78
9
MIU_CS_N3
MIU_OE_N
MIU_WEN
MIU_MASK0
MIU_DATA
(
3
21
10
11
1213
14
15
MIU_RDY
MIU_CS_N0
MIU_CS_N1
MIU_CS_N2
SC0_CCK
USB_DM
USB_DP
USB_PWR
SC0_CMDVCC
(I2C-USB-SCO)
SCL1
SDA0
SCL0
SDA1
SC0_DA
USB_OVRCUR
SC0_OFFSC0_RST
PIO
VS
SC1_DA
SC1_CMDVCC
SC1_RST
SC1_OFF
SC1_CCK
CTS0
RTS0
RX0
TX0
DCD0
PLL_OUTX0
(GIR_IN
IR_OUT
PWM
VPP
C4
C8
D S U
_ T P C 0
1 2 0 1 2 S Y S
_ R E S E T N
T D I
T D O
P C S T 0
P C S T 1
T M S
T R S T
T C K
R E S E T N
X T A L
_ I N
X T A L
_ O U T
A V D D
_ P L L
A V S S
_ P L L
( J T A G - E
T A G - S
Y S )
D S U
_ C L K
D S U
_ T P C 1
0
100MHz
100MHz
100MHz
1 %
2V22V22V22V22V22V2
2V22V2
0V
1V6
1V3
0V
1V
1V6
0V
0V
0V
0V
4V6
4V6
3V3
3V3
3 V 2
3 V 2
3 V 3
3 V 3
0 V
3 V 3
0 V
1 V 2
1V2
3V3
1V2
0V
2V3
2V3
2V3
0V
2V5
0V
2V5
2V9
2V3
3V3
0V
4V6
3V3
0V
0V
0V
3V3
0V
0V
0V
0V0V0V0V0V0V0V0V0V0V0V0V0V0V0V0V
3V3
3V3
3V3
3V3
3V3
2V6
2V6
2V6
2V6
2V6
RES
0V
POWER ON RESET
FOR DEV. ONLY
3V33V3
FOR DVE. ONLY
PRO. FOR USB
CONFIGURABLE
RES
4G05FOR DEVELOPMENTONLY
4G01,4G02, 4G03,4G04FOR PRODUCTION
RES
RES
RES
RES
RES
R E S
R E S
1 2 3 4 5 6 7 8 9 10 11
A
B
C
D
E
F
G
H
I
F G 2 6
IG21
4G31
100n2G31
100n
IG19
IG20
2G32
IG18
4G05
4G04
4G03
4G02
4G01
2
34
56 7
BM05B-SRSS-TBT
1G04
1
20
46
8
1012
14
1618
FTSH
19
35
7
911
13
1517
FG42
FTSH
+3V3_VDDP
+3V3_VDDP
+3V3_VDDP
3 G 1 1
1 0 K
IG17
IG15
IG16
IG14
3G20 10K
4G10
4G09FG40
FG41
10u
2G24
16V
2G23
10u16V
2G22
16V10u
60R
1 0 u
5G04
1 6 V
2 G 1 8
2 G 1 7
1 6 V
1 0 u
FG35
FG36
FG34
FG32
FG18
FG39
FG37
+3V3
+3V3
3G65
1K0
1
3 3 n
2 G 3 4
NCP303LSN307G06
CD5
GND
3
INP2
4
NC
OUTP
3
4
1
2
S K Q T L B
1 G 0 3
3G63 10K
3G62
3G61
33R
3G60
33R
45
33R
73G59-4 33R3G59-2 23G56-4 45
33R
3G56-2 2733R
3G58-4 4533R
45
33R7
33R3G57-43G58-2 33R2
3G57-2 33R27
33R1836
3G59-136
3G56-3 33R18
33R3G59-3
633R3G56-1
3G58-3 333R3G58-1 1833R
33R3633R18
3G57-3
+1V2_MOJO
3G57-1
3G15
+1V2_MOJO
FG16
10K FG12
FG15
FG14
+3V3
3 G 4 0
1 K 2
FG33
FG31
10u 16V
2G33
IG13
1 0 K
3 G 1 2
3 G 4 8
3
3 R
5G03
100n2G11
2G10
2G09
100n
100n
100n2G06
2G07 100n
2G08
2G03 100n
100n
100n2G04
100n2G05
2G14 100n
100n
100n2G16
2G15
2G12 100n5G02
100n2G13
5G01
2 G 0 2
1 0 u
1 6 V
+3V3clean
2G21 100n
100n2G20
100n2G19
1 5 9
1 9 6
1 9 5
4
5
3 2 0 8
2 0 7 1 2
1 5 8
1 5 7
1 6 0
1 8 6
1 8 7
1 9 4
1 8 9
1 8 8
1 9 7
45
46
47
48
7 G 0 0 - 8
P N X 8 3 1 4 H S
185
33
34
35
13
14
15
16
32
7GPNX
31
49
12
3938
6
8
7
9201
200
198
199
7G00-6PNX8314HS
40
37
36
536866
106
70
109
108
646258565452
6563595755
74
73
72
71
6967
7G
123
115
116
117
118
121
122
132
129
PNX
114
128
127
126
125
124
203
202
206
204170
163
168
172
205 165
167
25
2627
29
30
28
PNX8314HS7G00-3
2021222324
44
61
77
95
112
131
162
193
PNX8314HS7G00-2
130
161
190
173
42
79
120
135
192
11
174
41
78
119
134
191
10
43
60
76
94
111
7G00-1
175
169
164
171
166
10K
PNX8314HS
3G16
10K3G17
3G35 22R
3G33 22R
22R
FG17
3G34
FG19
3G44 100R
100R3G43
3G47 100R
4MHZ_MOJO
JTAG_TCK
JTAG_TRST
JTAG_TMS
STV_TDI
100R3G46
TS_DATA(0:7)
MIU_DATA(0:15)
MIU_WEN
NOR_RYBY
10046_TDO
10046_TDO
TS_CLK
TS_SYNC
TS_VALID
DSW_n
MIU_DATA(13)MIU_DATA(12)MIU_DATA(11)MIU_DATA(10)MIU_DATA(9)MIU_DATA(8)MIU_DATA(7)MIU_DATA(6)MIU_DATA(5)MIU_DATA(4)MIU_DATA(3)MIU_DATA(2)MIU_DATA(1)MIU_DATA(0)
MIU_OEN
STV_CS
NOR_CS
RXD0
TXD0
USB_DMUSB_DP
USB_OVRCURUSB_PWR
MOJO_TCK
M O J O_
T C K
MOJO_TMS
M O J O_ T M S
M O J O_ T
R S T
RESET_n
RESET_n
RESET_n
MIU_DATA(15)MIU_DATA(14)
1V2_CORE
MOJO_I2S_OUT_SD
MIU_RDY
NOR_RYBY
1V2clean
MIU_WEN
MOJO_I2S_OUT_WS
STV_A25
STV_INT
NOR_WP
C_CVBS
B|Pb
G|Y
R|Pr
SDRAM_DATA(1)
SDRAM_DATA(2)
SDRAM_DATA(3)
SDRAM_DATA(4)
SDRAM_DATA(5)
SDRAM_DATA(6)
SDRAM_DATA(7)
SDRAM_DATA(8)
SDRAM_DATA(9)
SDRAM_DATA(10)
SDRAM_DATA(11)
SDRAM_DATA(12)
SDRAM_DATA(13)
SDRAM_DATA(14)
SDRAM_DATA(15)
FE_LOCK
user_EEPROM_WP
TS_DATA(1)TS_DATA(2)TS_DATA(3)TS_DATA(4)TS_DATA(5)TS_DATA(6)TS_DATA(7)
RESET_STV
I2C_LOCAL_SCL
I2C_LOCAL_SDA
RESET_FE_n
IIC_SCL
IIC_SDA
MOJO_I2S_OUT_SCK
TS_DATA(0)
3139 123 6261.1
Circuit Diagrams and PWB Layouts 41LC7.1E LA 7.
SSB: DVB - Mojo Memory (Not implemented in this chassis)
DVB-MOJO MEMORY
1 2 3 4 5 6
B03E
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41/92
SCL
ADR
0
12 SDA
WC
10
4
98
76
0
32M-1
0A
D
5
11
2
1
17
OE
12
1314
15
VPP/WP_
20
19
18
16
RB
43
2
CE
76
WERP
1
0
BYTE
3
NC
5
89
10
1112
1314
15
A-1
U
11
6
1
11
D
A
DQML
2
3
9
3
78
9
10
CLK
4
BA
CS
5
RAS
2
CAS
WE
15
7
10
NC
6
12
8
1
VSS VSSQ
0
10
0
VDD VDDQ
13
14
CKE
4
5
2/4/8MB
NOR
FLASH
I2C ADDRESS:A0
100MHz
100MHz
0V0V
0V
0V0V
0V0V
0V
0V0V
0V
0V
0V
0V
1V53V3
3V3V3V
0V
1V3
1V31V
1V31V3
1V20V
1V4
1V3
1V3
1V1V41V4
1V3
1V20V7
3V3
2V2
5V
5V
4V
4V
4V
3V2
3V2
3V2
3V23V2
3V2
3V2
3V2
3V2
3V2
3V23V2
3V2
3V2
3V2
3V23V2
3V2
0V
0V0V
0V
0V
0V
0V0V
0V
100MHz
1 2 3 4 5 6
A
B
C
D
E
1 0 0 n
2 H 0 3
FH03
FH05
3H14
1R0
2H15
220n
FH08 +3V
1 6 V
1 0 u 2
H 0 7
+5V_SW
220n
2H14
3 H 1 1
+3V3 5H02
+3V3
+5V_SW
+3V3_NOR48
+3V3_NOR48
FH01
IH04
4H04
4H01
3H00 4H003K3
28
15
12
37
27 46
11
18
8
7
4726
1
4817
16
9
23
10
2221
20
19
4Mx8/2Mx16
25
24
6
54
3
2
EPROM
M29W320ET70N7H00
8
4
7
M24C64-WMN6
7H03
12
3
6
5
(8Kx8)
Φ
EEPROM
5H03
4H02
4H03
FH06
2 H 0 4
1 0 0 n
FH07
43 49
28 41 54 6 12 46 52
1615
36
40
18
39
1 1 4 27 3 9
5051
53
5
78
1011
13
42
44
2021
17
37
38
19
2
4
4547
48
2235
25
26
29
3031
3233
34
EDS1216AGTA
SYNC
Φ
4x2Mx16
SDRAM
2324
5H01
7H02
1 6 V
1 0 u 2
H 0 6
2 H 1 1
1 0 0 n
2 H 0 8
1 0 0 n
2 H 1 2
1 0 0 n
1 0 0 n
2 H 0 9
1 0 0 n
2 H 1 0
2 H 1 3
1 0 0 n
NOR_RYBY
MIU_ADDR(20)
MIU_ADDR(21)
SDRAM_ADDR(0:14)
SDRAM_DATA(0:15)
NOR_CS
MIU_WEN
MIU_ADDR(12)MIU_ADDR(13)
MIU_ADDR(14)
MIU_ADDR(15)MIU_ADDR(16)
MIU_ADDR(17)MIU_ADDR(18)
MIU_ADDR(19)MIU_ADDR(20)
MIU_ADDR(22)
MIU_OEN
RESET_n
SDRAM_ADDR(6)
SDRAM_ADDR(5)SDRAM_ADDR(4)
SDRAM_ADDR(3)
SDRAM_ADDR(2)SDRAM_ADDR(1)
SDRAM_ADDR(0)
SDRAM_ADDR(14)
SDRAM_ADDR(13)
MIU_ADDR(1)
MIU_ADDR(2)
MIU_ADDR(3)
MIU_ADDR(4)MIU_ADDR(5)
MIU_ADDR(6)
MIU_ADDR(7)MIU_ADDR(8)
MIU_ADDR(9)
MIU_ADDR(10)
MIU_ADDR(11)
SDRAM_DATA(5)
SDRAM_DATA(6)
SDRAM_DATA(7)SDRAM_DATA(8)
SDRAM_DATA(9)
SDRAM_DATA(10)SDRAM_DATA(11)
SDRAM_DATA(12)SDRAM_DATA(13)
SDRAM_DATA(14)SDRAM_DATA(15)
SDRAM_ADDR(11)
SDRAM_ADDR(10)SDRAM_ADDR(9)
SDRAM_ADDR(8)
SDRAM_ADDR(7)
SDRAM_ADDR(12)
SDRAM_DQM1
SDRAM_DQM0SDRAM_WE
SDRAM_CASSDRAM_RAS
SDRAM_CKE
SDRAM_CLK
SDRAM_DATA(0)
SDRAM_DATA(1)
SDRAM_DATA(2)SDRAM_DATA(3)
SDRAM_DATA(4)
RES
RES
B03E
3139 123 6261.1
42LC7.1E LA 7.Circuit Diagrams and PWB Layouts
SSB: DVB - Mojo Analog Back End (Not implemented in this chassis)
DVB-MOJO ANALOG BACK END
1 2 3 4 5 6 7
B03F
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42/92
E S D P r o t e c t i o n
UART CON FOR COMPAIR ONLY
RES
RES
R E S
RES
RES
R E S
R E S
R E S
1V8
1 2 3 4 5 6 7
A
B
C
D
E
FJ22
P E S D 5 V 0 S 1 B A
6 J 6 3
6 J 6 2
P E S D 5 V 0 S 1 B A
P E S D 5 V 0 S 1 B A
6 J 6 1
6 J 6 0
P E S D 5 V 0
S 1 B A
B A S 3 1 6
6 J 0 3
3J03
100R
FJ23
F J 0 2
IJ01
1 0 0 2
1 0 0 1
4
4
FJ25
FJ24
3J15
3J14
6 J 1 5
B Z X 3 8 4 - C 6 V 8
34 5
B Z X 3 8 4 - C 6 V 8
6 J 1 4
1J14S3B-PH-SM4-TB
1
2
2 J 0 1
1
0 u 1 6 V
60R
5J01
2 J 0 2
1 0 0 n
+1V8S_SW
3 J 0 1
3J02
12K
+3V3_MOJO
7J05PDTC114ET
FJ27
FJ26
4 7 R
3 J 6 6
3 J 6 4
4 7 R
4 7 R
3 J 6 2
4 7 R
3 J 6 0
2J71
22p
22p
2J68
2J64
22p
22p
2 J 7 3
2J60
6 8 p
2 J 7 2
1 8 0 p
6 8 p
2 J 7 0
2 J 6 9
1 8 0 p
6 8 p
2 J 6 7
1 8 0 p
2 J 6 6
2 J 6 2
1 8 0 p 6 8 p 2
J 6 3
1 8 0 R
3 J 6 1
3u3
5J53
3 J 6 5
5J55
3u3
1 8 0 R
3 J 5 9
3u3
1 8 0 R
5J52
3 J 6 3
1 8 0 R
3u3
5J54
IJ66
IJ64
IJ65
IJ63
IBO_G_IN
IBO_B_IN
IBO_CVBS_IN
IBO_R_IN
B|Pb
R|Pr
C_CVBS
G|Y
3139 123 6261.1
Circuit Diagrams and PWB Layouts 43LC7.1E LA 7.
SSB: Micro Processor
MICROPROCESSORE
I O RES *RES *
1 2 3 4 5 6 7 8 9 10 11
4L20
4L21
1304 0 p
3L20 100R
0 p
100R3L21
YY V 3
_ S T B Y
FRONT_Y_CVBS_INB04A Item i T V w i t h S i d e
A V
O t h e r r e g
i o n
DescriptionBHP00.2MP11VNOC4031
RHPMS00.2MP01VNOC2131
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DA1
8
TA3OUT
W
9
W
ADDR
V
P1
4
ANEX0
HLDA
6
HOLD
RXD1
INT
7
TA2IN
XTAL
TA4OUT
RESET
SOUT4
CLK4
AVCC
TA1IN
VSS
TA2OUT
SIN4
TXD1
BYTE
8910
11
P9
6
CLK3
CTS1
SDA2
RDY
WRL
4
5
6
NMI
3
TA3IN
CLK1
12
TA1OUT
TB5IN
TA0OUT
17
SIN3
ANEX1
DA0
5
23
3
21
3
P6
TA4IN
INT
D
ADDR
012
0
KI
AN0
WRHBHE
RD
U
7
P3
RTS1
19
P7
DATA
CLK2V
CTS2RTS2
D
TBIN5
0
VCC
16
CLKOUT
P4
ALE
P5
OUT
AVSS
P0 S OUT3
IN
12
BCLK
ADDR
ADTRG
CNVSS
13
TA0IN
RXD2SCL2
XCOUT
A
P2
4
WR
AN
18
U
P8
SDA1
SDA0
SCL1
CTS0
ZP
RTS0
CTS0
CLK0
7
CLKS1
VREF
10
111213
CS
TXD0
RXD0
TXD2
V
DATA
P10
XCIN
1415
14
15
01
0
21
AN2
SCL1
SUB
ER
GND
VOUT
VDD
SCL
ADR
0
1
2 SDA
WC
RES
SDM
COMPAIR
ITV_Connector A:
E M C
E M C
E M C
E M C
EMC
TO / FROM IR/ LED & KEYBOARD
RES
R E S
R E S
R E S
R E S
R E S
R E S
RES
RES
RES
R E S
R E S
R E S
R E S
R E S
R E S
R E S
R E S
RES
RES
RES
RES
RES
RES FOR PSU_STBY
NC
R E S
R E S
F o r D e v e l o p m e n t o n l y
BOOT LOADER R E S
R E S
RES
RES
RES
RES
R E S RES
RES
RES
R E S
R E S
RES
U A R T C O N
PANEL
RES
RESRES
R E S
RES
RES
RES
RES
R E S
RES
FOR DVB ONLY
RES FOR BDS
RES FOR BDS
RES
R E S
RES
R E S
T O / F R O M S I D E
R E
S
R E
S
R E S
R E S
R E S
RES
* *
* * *
*RES *
RESRES
R E S
* R E S
* R E S
*
RES
1V5
1V5
3V3
0V8
3V2
3V3
3V3
1 2 3 4 5 6 7 8 9 10 11
A
B
C
D
E
F
G
H
I
I388100R3L26I399 43254324
4L25
4L24
IL
IL3L24
33R
33R
3L25
2 L 3 1
1 n 0
1 n