Photonic interconnects

Anuroop VidapalapatiPradheep Khanna Kaliraj

Outline:Photonic interconnects :• Motivation• Implementation problems• Hybrid NOC• Implementation• Topologies

Motivation :

• Increase in number of cores in a chip (CMP)• Latency requirements• Need for larger bandwidth• Lesser power consumption• Lesser thermal dissipation

80% of the power consumption in near futureInterconnect : Saturation point?

Pentium 4 processors currently heat generated over the kitchen baking tray. Intel estimated that unless this issue cfind a solution, otherwise the heat generated by the futureprocessors will continue to grow, perhaps even nuclearplants and comparable to the core of the site.

- Quoted from ‘ ZUNSHAN ’

Photonic interconnect : A suitable candidate!!!!!!-- Provides higher bandwidth-- Consumes lesser power-- It is fast .(3x10^8 m/s)--Better performance per watt scaling--No need for extra hardware

-Repeaters, regenerators, Buffers.Feasibility?Advancement in “Nanoscale silicon photonics”Photonic elements as library cells in Std. CMOS process

Interconnect Basics :1.The data is sent in packets.

-Packets are divided into flits1.The first flit is called Header flit2.Header flit:• contains Routing information

- Source address ,Destination address, Message length etc

• creates path for following message flits• Buffered at every router for processing4.Body flit:• Follows the path created by the header.• Requires no processing

Bottlenecks!Photonic message cannot be buffered .

An attempt -Will leave a major footprint.Will require a photo detector and a light

source at every switch.

Solution?

Hybrid NOCContains the advantages of both

photonic and electronic transmissions.Electronic Messages :

- Control message- Used for header processing- Used to transmit Short messages a

The header flits - electronic messages

Photonic messages:Body flits are transmitted as light

a

I/O controllers

Operation :Path setup Packet (Priority / Flow id)

Path established acknowledgement

Message transmission

Ack from receiver

Tear down packet

Special packets:

1.Packet dropped packetRouter to sender during congestion

2.Terminate on Time out packetSender to Router where the path setup packet is blocked

Implementation : Switches Basic building Blocks - Broadband Photonic switching elements

(Micro ring resonator)

OFF state : Frequency of rings is different from wavelengthON State : Resonance shifts and the light is coupled into ringsMerits :

Small footprint – 12 micro metersLesser power consumption – 0.5 mW.Switching time <2 ns

4 X 4 Switch Controlled by electronic router

Problem of blocking:Message from South to east

-Blocks messages from W to S and E to NWIDE turn message blocks narrow turn message

A possible approach to avoid blocking :

Three switches :

1.Gateway switch : Injected messages should turn toward injection switches.

2.Injection switch : Messages on network do not turn to injectionpaths-no blocking

3.Ejection switch : Messages arrive from Network, they either turn for ejection or pass straight through.

Flow control :With the use of Hybrid technology ,the flow control differs .

Latency :Short Messages : Zero- Load path setup latency.Long messages : Contention Dominated.

Solution :

Transmit –Short messages as electronic messageLong message as photonic message

During contention –Path setup packet is buffered- Causes latency

Solution:1.Reduce buffers

- send Packet dropped packet to Sender2.Sender will use the Path multiplicity

- to transmit data in different path

•Path Multiplicity :Several parallel lanes exist in each row/column.

Limitations : • PM has diminishing returns beyond a factor of x3• Increases footprint

To fully utilize the efficiency of Hybrid architecture

•Use DMA – large block of data are exchanged between modules with Minimal CPU overhead.

•Photonic path can be used to transfer huge chunks of data without latency.

Topology for Photonic interconnects :

Four possible topologies :• 2-D Folded Torus topology • Corona• Single Folded Bus• Multiple-Segment Buses

Each topology has its own merits and demerits

2-D Folded Torus topology

The clusters communicate through set of vertical & horizontal Torus ringsThe rings are connected by transport matrix rings in the middle.

Merits :Less network diameter at the expense of long pathsWith the use of photonics, long paths are not a problem

Demerits:WDM transmission is limited since the paths are

wavelength lockedPathways are thermally tuned to specific wavelengths

To overcome this we can use more MRRsBUT

• will increase complexity • Will increase loss due to optical loss and switch crosstalk

along pathways

Corona :

•Clusters are connected by dedicated waveguide .•Clusters receive fixed set of clusters from remaining clusters•Bus terminates back in the originating cluster•Clusters are connected through buses in a ring like fashion

Merits :• Simpler topology• Suitable for tile with less number of cores

Demerits:• Requires large number of waveguides• Waveguides traverse through a large area• Requires number of micro-rings• Leads to large waveguide loss and insertion loss• Has low BER performance

Single Folded Bus (SFB)

•Uses a single folded bus ,with inner and outer waveguide•Bus traverses all the clusters in the tile•Receives data from inner waveguide, sends data through outer waveguide•Uses WDM to transmit data

Merits : • Less number of buses.• Suitable for Small architectures• Simple implementation

Demerits:• Uses a large number of MRRs – Insertion loss• Waveguide losses between cluster pairs - large signal loss.• Low BER performance with increasing number of clusters

Multiple segment Buses (MSB)

•Segments pass through less number of clusters when compared to corona.•Adjacent row clusters are connected by segmented buses.•Non-adjacent rows are connected by Inter segment routers

Merits :• Number of clusters traversed by a bus is less.• Low Waveguide loss.• The number of clusters traversed decreases with increase in number of

Inter segment register (ISR).

Demerits:The message should travel a long path when the number of clusters are

high.Number of ISRs increase with large architecture.

YET , the performance of MSB for 64 cluster tile is good when compared to other topologies discussed earlier

Conclusion :

Thanks to IBM ,We are closing on to reality of photonic interconnects.“The resulting CMOS chip achieved nanosecond-scale delays, which could work in network connections today to reduce congestion at busy switches. Each ring resonator slows the light passing through it by forcing it to circle around many times before passing along to the next ring.By ganging 100 ring resonators in series, IBM also demonstrated the

feasibility of on-chip photonic silicon delays lines.”

-- EE times article

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