PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide · Mode), and Mobile DDR. The IP has a...

PHY Lite for Parallel InterfacesIntel® FPGA IP User Guide

Updated for Intel® Quartus® Prime Design Suite: 20.4

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Contents

1. About the PHY Lite for Parallel Interfaces IP ................................................................. 41.1. Device Family Support............................................................................................41.2. Features...............................................................................................................5

2. PHY Lite for Parallel Interfaces Intel Agilex FPGA IP...................................................... 62.1. Release Information...............................................................................................62.2. Functional Description............................................................................................ 6

2.2.1. Intel Agilex I/O Sub-bank Interconnects....................................................... 82.2.2. Intel Agilex Input DQS/Strobe Tree.............................................................102.2.3. PHY Lite for Parallel Interfaces Intel Agilex FPGA IP Top Level Interfaces..........102.2.4. Dynamic Reconfiguration.......................................................................... 17

2.3. Getting Started....................................................................................................222.3.1. Parameter Settings.................................................................................. 232.3.2. Signals................................................................................................... 26

2.4. I/O Standards..................................................................................................... 292.4.1. Input Buffer Reference Voltage (VREF)........................................................292.4.2. On-Chip Termination (OCT)....................................................................... 30

2.5. Design Guidelines................................................................................................ 312.5.1. Guidelines: Group Pin Placement................................................................312.5.2. Reference Clock.......................................................................................342.5.3. Reset..................................................................................................... 34

2.6. Design Example...................................................................................................342.6.1. Generate the Design Example....................................................................35

3. PHY Lite for Parallel Interfaces Intel Stratix 10 FPGA IP.............................................. 403.1. Release Information............................................................................................. 403.2. Functional Description.......................................................................................... 40

3.2.1. Top Level Interfaces................................................................................. 423.2.2. Clocks.................................................................................................... 423.2.3. Output Path............................................................................................ 433.2.4. Input Path...............................................................................................463.2.5. Dynamic Reconfiguration.......................................................................... 49

3.3. Getting Started....................................................................................................643.3.1. Parameter Settings.................................................................................. 643.3.2. Signals................................................................................................... 72

3.4. I/O Standards..................................................................................................... 763.4.1. Input Buffer Reference Voltage (VREF)........................................................773.4.2. On-Chip Termination (OCT)....................................................................... 80

3.5. Design Guidelines................................................................................................ 823.5.1. Guidelines: Group Pin Placement................................................................823.5.2. Reference Clock.......................................................................................833.5.3. Reset..................................................................................................... 843.5.4. Constraining Multiple PHY Lite for Parallel Interfaces to One I/O Bank............. 843.5.5. Dynamic Reconfiguration.......................................................................... 843.5.6. Timing....................................................................................................84

3.6. Design Example...................................................................................................923.6.1. Generate the Design Example....................................................................92

Contents

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4. PHY Lite for Parallel Interfaces Intel Arria 10 and Intel Cyclone 10 GX FPGA IPs......... 994.1. Release Information............................................................................................. 994.2. Functional Description.........................................................................................100

4.2.1. Top Level Interfaces............................................................................... 1014.2.2. Clocks.................................................................................................. 1034.2.3. Output Path...........................................................................................1054.2.4. Input Path.............................................................................................1074.2.5. Dynamic Reconfiguration.........................................................................111

4.3. Getting Started..................................................................................................1234.3.1. Parameter Settings.................................................................................1244.3.2. Signals................................................................................................. 131

4.4. I/O Standards....................................................................................................1364.4.1. Input Buffer Reference Voltage (VREF)...................................................... 1384.4.2. On-Chip Termination (OCT)..................................................................... 141

4.5. Design Guidelines.............................................................................................. 1444.5.1. Guidelines: Group Pin Placement..............................................................1444.5.2. Reference Clock..................................................................................... 1444.5.3. Reset....................................................................................................1454.5.4. Constraining Multiple PHY Lite for Parallel Interfaces to One I/O Bank............1454.5.5. Dynamic Reconfiguration.........................................................................1454.5.6. Timing..................................................................................................145

4.6. Design Example................................................................................................. 1534.6.1. Generate the Design Example.................................................................. 153

4.7. Application Specific Design Example..................................................................... 1674.7.1. Implementation using the PHY Lite for Parallel Interfaces IP.........................168

5. PHY Lite for Parallel Interfaces IP Core User Guide Document Archives..................... 172

6. Document Revision History for the PHY Lite for Parallel Interfaces IP User Guide ..... 173

Contents

Send Feedback PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

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1. About the PHY Lite for Parallel Interfaces IPThis user guide describes the PHY Lite for Parallel Interfaces Intel® Agilex™ FPGA IP,PHY Lite for Parallel Interfaces Intel Stratix® 10 FPGA IP, PHY Lite for ParallelInterfaces Intel Arria® 10 FPGA IP, and PHY Lite for Parallel Interfaces Intel Cyclone®

10 GX FPGA IP cores. The PHY Lite for Parallel Interfaces IP core is primarily used forbuilding custom memory interface PHY blocks. You can use this solution to interfacewith protocols such as DDR2, LPDDR2, LPDDR, TCAM, Flash, ONFI (SynchronousMode), and Mobile DDR.

The IP has a dedicated PHY clock tree in each I/O bank. The PHY clock tree is shorterwhich yields lower jitter and duty cycle distortion (DCD), enabling designs to achievehigher performance.

In addition, this IP supports Dynamic Reconfiguration feature which enablesreconfiguration of the data and strobe delays. You can align the data and strobe viacalibration to achieve timing closure at high frequencies.

This IP controls the strobe-based capture I/O elements. Each instance of the IP cansupport an interface up to 18 individual data/strobe capture groups. Each group cancontain up to 48 data I/Os as well as the strobe capture logic.

Related Information

PHY Lite for Parallel Interfaces IP Core User Guide Document Archives on page 172Provides a list of user guides for previous versions of the PHY Lite for ParallelInterfaces Intel FPGA IP core.

1.1. Device Family Support

The PHY Lite for Parallel Interfaces IP supports the following devices:

• Intel Agilex

• Intel Stratix 10

• Intel Arria 10

• Intel Cyclone 10 GX

For Arria V, Cyclone V, and Stratix V devices, use the ALTDQ_DQS2 Intel FPGA IPinstead.

Related Information

ALTDQ_DQS2 IP Core User GuideFor more information about the ALTDQ_DQS2 IP

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Intel Corporation. All rights reserved. Agilex, Altera, Arria, Cyclone, Enpirion, Intel, the Intel logo, MAX, Nios,Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/orother countries. Intel warrants performance of its FPGA and semiconductor products to current specifications inaccordance with Intel's standard warranty, but reserves the right to make changes to any products and servicesat any time without notice. Intel assumes no responsibility or liability arising out of the application or use of anyinformation, product, or service described herein except as expressly agreed to in writing by Intel. Intelcustomers are advised to obtain the latest version of device specifications before relying on any publishedinformation and before placing orders for products or services.*Other names and brands may be claimed as the property of others.

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1.2. Features

The PHY Lite for Parallel Interfaces IP:

• Supports input, output, and bidirectional data channels.

• Supports DQS-group based data capture, with up to 48 I/Os (including data,strobes, PLL reference clock) per IP for Intel Agilex devices and 48 I/Os (includingstrobes) per group for Intel Stratix 10, Intel Arria 10, and Intel Cyclone 10 GXdevices.

• Supports DQS gating/ungating circuitry for strobe-based interfaces.

• Supports output delays via interpolator.

• Supports dynamic on-chip termination (OCT) control.

• Supports quarter-rate for Intel Agilex devices and quarter-rate to half-rate andhalf-rate to full-rate of the interface clock conversions for Intel Stratix 10, IntelArria 10, and Intel Cyclone 10 GX devices.

• Supports input, output, and read/DQS/OCT enable paths.

• Supports single data rate (SDR) and double data rate (DDR) at the I/Os.

• Supports PHY clock tree.

• Supports dynamically reconfigurable delay chains using Avalon® memory-mappedinterface for Intel Agilex, Intel Stratix 10, Intel Arria 10, and Intel Cyclone 10 GXdevices.

• Supports process, voltage, and temperature (PVT) or non-PVT compensated inputand DQS delay chains

Note: The non-PVT compensated component of the input delay is set throughthe .qsf assignment in the Intel Quartus® Prime software.

1. About the PHY Lite for Parallel Interfaces IP



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2. PHY Lite for Parallel Interfaces Intel Agilex FPGA IP

2.1. Release Information

Intel FPGA IP versions match the Intel Quartus Prime Design Suite software versionsuntil v19.1. Starting in Intel Quartus Prime Design Suite software version 19.2, IntelFPGA IP has a new versioning scheme.

The Intel FPGA IP version (X.Y.Z) number can change with each Intel Quartus Primesoftware version. A change in:

• X indicates a major revision of the IP. If you update the Intel Quartus Primesoftware, you must regenerate the IP.

• Y indicates the IP includes new features. Regenerate your IP to include these newfeatures.

• Z indicates the IP includes minor changes. Regenerate your IP to include thesechanges.

Table 1. PHY Lite for Parallel Interfaces Intel Agilex FPGA IP Release Information

Item Description

IP Version 20.3.0

Intel Quartus Prime Version 20.4

Release Date 2020.12.14

Related Information

PHY Lite for Parallel Interfaces Intel FPGA IP Core Release NotesProvide a list of changes made in each release of the PHY Lite for Parallel InterfacesIntel FPGA IP.

2.2. Functional Description

The PHY Lite for Parallel Interfaces Intel Agilex FPGA IP utilizes the I/O banks in IntelAgilex devices. Each I/O bank has two I/O sub-banks in each device. The top sub-bank is placed near the edge of the die, and the bottom sub-bank is placed near theFPGA core.


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Each each sub-bank contains the following components:

• Hard memory controller

• I/O PLL and PHY clock trees

• DLL

• Input DQS/strobe trees

• 48 pins, organized into four I/O lanes of 12 pins each

Figure 1. Intel Agilex I/O Bank Structure

3F

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I/O PLL I/O VR

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Intel Agilex FPGA

Intel Agilex FPGA

2E 2F

2A 2CSDM 2E 2F

1 1

1 1

1 1

1 1

1 When SERDES is used, the differential RX and TX buffer pairs are unidirectional as shown in this diagram.When SERDES is not used, these differential I/O buffers can be configured as RX or TX with a maximum of three differential RX pairs per lane.

2B

2B

HPS3D3C3B3A 3E 3F

HPS3D3C3B3A 3E




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Related Information

• Design Guidelines on page 31For more information about placement restrictions

• I/O Bank Architecture in Intel Agilex DevicesFor more information about Intel Agilex I/O bank architecture

2.2.1. Intel Agilex I/O Sub-bank Interconnects

There are interconnects between the sub-banks which chain the sub-banks into a row.The following figures show how I/O lanes in various sub-banks are chained together toform the top and bottom I/O rows in various Intel Agilex device variants. Thesefigures represent the top view of the silicon die that corresponds to a reverse view ofthe device package. Each sub-bank is labeled with ID number to facilitate pinplacement.

Figure 2. Sub-Bank Ordering with ID in Top I/O Row in Intel Agilex AGF012 andAGF014, package R24A

1 3 4 6

0 2 5 7

Figure 3. Sub-Bank Ordering with ID in Bottom I/O Row in Intel Agilex AGF012 andAGF014, package R24A

0 2 5 7

1 3 4 6




8

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Figure 4. Sub-Bank Ordering with ID in Top I/O Row in Intel Agilex AGF014, packageR17A

0 2 5 7

1 3 4 6

Figure 5. Sub-Bank Ordering with ID in Bottom I/O Row in Intel Agilex AGF014,package R17A

0 2 5 7

1 3 4 6

Figure 6. Sub-Bank Ordering with ID in Top I/O Row in Intel Agilex AGF022 andAGF027 devices, package R25A

0 2 4 6 9 11

1 3 5 7 8 10

Figure 7. Sub-Bank Ordering with ID in Bottom I/O Row in Intel Agilex AGF022 andAGF027 devices, package R25A

0 2 4 7 9 11

1 3 5 6 8 10




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2.2.2. Intel Agilex Input DQS/Strobe Tree

The input DQS/strobe tree is a balanced clock network that distributes the readcapture strobe (such as DQS/DQS#) from the external device to the read captureregisters inside the I/Os.

The DQS/strobe tree is used for input and bidirectional pin types.

Within every bank, only certain physical pins at specific locations can drive the inputDQS/strobe trees. The pin locations that can drive the input DQS/strobe trees vary,depending on the size of the group.

Table 2. Pins Usable as Read Capture Clock / Strobe Pair

Data pins of a group occupies whichlanes?

Group Size Strobe Pins (1)(2)

0 x8 / x9 Pin 4, 5

1 x8 / x9 Pin 16, 17

2 x8 / x9 Pin 28, 29

3 x8 / x9 Pin 40, 41

0, 1 x18 Pin 4, 5

2, 3 x18 Pin 28, 29

1, 2 x36 Pin 16, 17

0, 1, 2 x36 Pin 16, 17

1, 2, 3 x36 Pin 16, 17

0, 1, 2, 3 x36 Pin 16, 17

2.2.3. PHY Lite for Parallel Interfaces Intel Agilex FPGA IP Top LevelInterfaces

The PHY Lite for Parallel Interfaces Intel Agilex FPGA IP consists of the following ports:

• Clocks and reset

• Core data and control (broken down into input and output paths)

• I/O (broken down into input and output paths)

(1) For strobe pin, use either pin for single-ended and use both pins for differential.

(2) In quarter rate, unused strobe pin cannot be used as data pins.




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Figure 8. Top-Level InterfaceThis figure shows the top-level diagram of the PHY Lite for Parallel Interfaces Intel Agilex FPGA IP interface.

PLLI/O Lane

I/O Lane

Tile Control

I/O Lane

I/O LaneVCO/Interpolator

phy_clkphy_clk_phs

core_clk_out

group_<n>_strobe_in/out/io

group_<n>_data_in/out/ioData to/from Core

Group

ref_clk

Reference ClockCore Clock

PHY ClockInterface Clock

Legend

Intel FPGA Core Logic

(From external oscillator)

(From /to external devices)

Intel FPGA Device

PHY Lite for Parallel Interfaces IP Core

Related Information

• Output Path on page 12For more information about the IP output path.

• Input Path on page 13For more information about the IP input path.

• Signals on page 26For more information about the IP data, control, and I/O interfaces.

2.2.3.1. Clocks

The PHY Lite for Parallel Interfaces IP uses a reference clock that is sourced from adedicated clock pin to the PLL inside the IP. This PLL provides four clock domains forthe output and input paths.

Table 3. PHY Lite for Parallel Interfaces IP Clock Domains

Clock Domain Description

Core clock This clock is generated internally by the IP and it is used for all transfers between the FPGA corefabric and I/O banks. The clock phase alignment circuitry ensures that this clock is kept in phasewith the PHY clock for core-to-periphery and periphery-to-core transfers.

PHY clock This clock is used internally by the IP for PHY circuitry running at the same frequency as thecore clock.

VCO clock This clock is generated internally by the PLL. It is used by both the input and output paths togenerate PVT compensated delays in the interpolator.

Interface clock This is the clock frequency of the external device connected to the FPGA I/Os.

Table 4. PHY Lite for Parallel Interfaces Intel Agilex FPGA IP Supported InterfaceFrequency

Core ClockRate

Speed Grade –1 (MHz) Speed Grade –2 (MHz) Speed Grade –3 (MHz)

Min Max Min Max Min Max

Quarter 100 1,200 100 933 100 933

Note: The PHY Lite for Parallel Interfaces Intel Agilex FPGA IP supports only quarter coreclock rate.




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2.2.3.1.1. Clock Frequency Relationships

The following equations describe the relationships between the clock domainsavailable in the PHY Lite for Parallel Interfaces IP.

Core Clock Rate = Interface clock frequency / Core clock frequency

VCO frequency Multiplier Factor = VCO clock frequency(3) / Interface clock frequency

2.2.3.2. Output Path

The output path consists of a FIFO and an interpolator.

Table 5. Blocks in Output PathThis table lists the blocks in the output path.

Block Description

Write FIFO Serializes the output data from the core with a serialization factor of up to 8 (in DDR quarter-rate).

Interpolator Works with the FIFO block to generate the desired output delay.

Figure 9. Output PathThis figure shows the output path for the PHY Lite for Parallel Interfaces Intel Agilex FPGA IP.

Write FIFO group_<n>_data_io/group_<n>_data_out

Interpolator

interpolator_clk

group_<n>_data_from_coregroup_<n>_oe_from_core

phy_clk

VCO clock

group_<n>_strobe_ingroup_<n>_strobe_out_en group_<n>_strobe_out/

group_<n>strobe_io

PHY Lite for Parallel Interfaces IPTo external interfaceFrom Intel FPGA core

Data path

Strobe pathInternal signal

(1)

(1)

(1)

(2)

(2)The Output Strobe Phase and Write Latency parametersin Parameter Editor sets the phase shift in this module.

Legend

(1)

(3) You can obtain this value from the VCO clock frequency parameter under General Tab inthe IP parameter editor.




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Related Information

Output Path Signals on page 27For more information about output path signals.

2.2.3.2.1. Output Path Data Alignment

The group_data_from_core and group_oe_from_core signals are arranged intime slices, which are separated into the individual pins in the group. The first timeslice is on the LSBs of the buses, which matches the Intel FPGA PHY interface (AFI)bus ordering of the External Memory Interfaces IP.

Example of time slices with individual pins correlation:

time(n),time(n-1),time(n-2),... time(0)

Where time0 = pin(n),pin(n-1),pin(n-2),...pin0

Figure 10. Example Output for Quarter Rate DDR

Related Information

AFI 3.0 Specification

2.2.3.3. Input Path

The input path of the IP consists of a data path, a strobe path, and a read enablepath.

Table 6. Blocks in Data, Strobe, and Read Enable PathsThis table lists the information about these paths.

Path Description

Data Path Receives data from external device to the FPGA core logic.The data path consists of a PVT compensated delay chain, a DDIO and a read FIFO.• DDIO and read FIFO—Responsible for deserialization with a factor of up to 8 (in DDR quarter-rate).

The transfer between the DDIO and the read FIFO is a zero-cycle transfer.Signals used in this path are:• group_data_in—Input data from external device.• group_data_io—Input and output data from/to external device.• group_data_to_core (output)—Output data to the Intel FPGA core.• phy_clk—This is an internal clock signal that provides clock to the blocks used in this path.The IP supports SDR input by sending data on single clock cycle from the external device.

Strobe Path Input strobe (dqs) to capture input data from external device.The strobe path consists of pstamble_reg (a gating component) and a PVT compensated delay chain.• pstamble_reg—This gating circuitry ensures that only clock edges associated with valid input data are

used.• PVT compensated delay chain—Provides a phase offset between the strobe and the data (for

example, center aligning edge-aligned inputs).Signals used in this path are:

continued...




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Path Description

• group_strobe_in, group_strobe_in_n (input)—Input strobe from external device. .• group_strobe_io, group_strobe_io_n(bidirectional)—Input and output strobe from/to external

device. group_strobe_io_n is used when strobe configuration is set to Differential.• dqs_clean(output)—This internal signal is the refined version of strobe_in signal.• dqs(input)—This internal signal is an input strobe to DDIO and Read FIFO in the data path, after

phase shift adjustment.

Read andStrobe EnablePath

Generates control signals for strobe calibration and reading data from Read FIFO.The read and strobe enable path consists of VFIFO, DQS_EN FIFO, and an interpolator.• VFIFO—Takes the rdata_en signal from the core and delays it separately for two outputs, one for

the read enable on the Read FIFO, and one for the strobe enable. These delays are calculated atgeneration time based on the read latency that you provide.

• DQS_EN FIFO and interpolator—Used for the strobe enable delay, the DQS_EN FIFO and interpolatorare identical to the Write FIFO and interpolator circuitry in the output path. The DQS_EN FIFO andinterpolator are configured to match the output delay for a group with no additional output delay(Write latency = 0).

Signals used in this path are:• group_rdata_valid (output)—This signal determines which data are valid when reading from

Read FIFO. This signal is delayed by the Read latency value set in the parameter editor.• group_rdata_en (input)—This signal represents the number of expected words to read from the

external device.• dqs_enable_in (input)—This is an internal signal that provides dqs delay value to the

pstamble_reg module to process a refined dqs signal.• dqs_enable_out (output)— This is an internal strobe with the delayed value specified by the

dqs_enable_in signal.• phy_clk—This is an internal clock for VFIFO and Read FIFO modules.• phy_clk_phs—This is an internal clock for the interpolator.• interpolator_clk—This is an internal clock for DQS_EN FIFO module.




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Figure 11. Input PathThis figure shows the input path of the IP.

Read FIFO DDIO Delay Chain (PVT)

group_<n>_data_to_core group_<groupnumber>_data_in

phy_clk

group_<n>_strobe_in

dqs

Delay Chain (PVT)

dqs_cleanpstamble_reg

DQS_EN FIFO

Interpolator

interpolator_clk

dqs_enable_out

phy_clk_phs

VFIFO

read_enable

dqs_enable_ingroup_rdata_en

phy_clk

group_<n>_rdata_valid

group_<groupnumber>_data_io

group_<n>_strobe_iogroup_<n>_strobe_in_n

6

1 2

34

5 56

# # = sequence number. This represent read operationsequence.

To Intel FPGA core PHY Lite for Parallel Interfaces IP To external interface

Data path

Strobe path

Read and Strobe Enable path

Control signal

group_<n>_strobe_io_n

Legend:

Internal signals

(1)

(1)

(1)

(1)

(1)

(1)

(1)(1)

(1)

(1)

(2)

(2)This module is controlled by Read Latency parameter in the Parameter Editor.

This module is uses the Capture Phase Shift parameter to generate the delay for the incoming strobe.(3)

(3)

Table 7. Read Operation SequenceA read operation is performed as listed in this table.

Read OperationSequence Number

Operation

1 The core asserts the rdata_en signal to the PHY Lite for Parallel Interfaces IP and issues a readcommand to the external device.

2 VFIFO and DQS_EN FIFO generate the dqs_enable signal to pstamble_reg. This signal isdelayed by the programmed read latency (which should match the latency of the externaldevice).

3 The pstamble_reg generates dqs_clean signal as valid data enters the read path.

4 The Delay Chain (PVT) adjusts the strobe with phase offset between the strobe and the inputdata (for example, 90° phase shift for DDR center-alignment).

5 The dqs signal is then used as strobe to read data from external device into the DDIO and ReadFIFO modules.

6 The VFIFO asserts the read_enable signal to Read FIFO and the rdata_valid signal to thecore simultaneously. The PHY Lite for Parallel Interfaces IP sends the captured data to the corewith the associated valid signal.

Related Information

Input Path Signals on page 28For more information about input path signals.




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2.2.3.3.1. Input Path Data Alignment

The bus ordering of group_data_to_core, group_rdata_en, andgroup_rdata_valid is identical to the ordering of the output path. The LSBs of thebus hold the first time slice of data received.

The group_rdata_valid delay is always set by the IP to match thegroup_rdata_en alignment. For example, quarter-rate delays are multiples of fourexternal memory clock cycles (one quarter rate clock cycle).

Reading from an unaligned memory address is called unaligned reads. Unalignedreads will result in unaligned group_rdata_valid and group_data_to_core withdata and valid signals packed to the LSBs. This request causes the IP to do two ormore read operations.

The following waveform shows an example of aligned reads on the input path of thePHY Lite for Parallel Interfaces Intel Agilex FPGA IP. At the first rising edge of thecore_clk_out signal, the group_0_rdata_en bus shows data of 4'hf, whichrepresents all incoming data are aligned. The group_0_rdata_valid bus shows thedata of 4'hf, which represents all incoming data are valid. Therefore, the incomingread data on the group_0_data_to_core bus matches the data seen on thegroup_0_data_io bus.

Figure 12. Example Input (Quarter Rate DDR) - Aligned

The following waveform shows an example of unaligned reads on the input path of thePHY Lite for Parallel Interfaces Intel Agilex FPGA IP.

The data from an unaligned read operation comes in two phases. At the first risingedge of the core_clk_out signal, the group_0_rdata_en bus shows value of 4'he,which shows there are 6 bytes of incoming data from group_0_data_io bus. On thesubsequent clock cycle, the group_0_rdata_en bus shows value of 4'h1, whichshows there are 2 bytes of incoming data from group_0_data_io bus.

The valid data are transfer to the IP through the group_0_data_to_core bus. Atfirst rising edge of the core_clk_out signal, group_0_rdata_valid bus shows avalue of 4'h7, which represents the first 6 bytes of the data from thegroup_0_data_to_core bus are valid and the last 2 bytes are invalid. On thesubsequent clock cycle, group_0_rdata_valid bus shows the value of 4'h1, whichshows the last 2 bytes of the data from the group_0_data_to_core bus are valid.

Figure 13. Example Input (Quarter Rate DDR) - Unaligned




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2.2.4. Dynamic Reconfiguration

You must perform calibration to achieve timing closure at a high frequency because ofthe asynchronous nature of the PHY. At a high level, calibration involves reconfiguringinput and output delays in the PHY to align data and strobes. With the PHY Lite forParallel Interfaces Intel Agilex FPGA IP, you can perform calibration using the dynamicreconfiguration feature. The dynamic reconfiguration feature allows you to modify theinput and output delays by writing to a set of control registers using an Avalonmemory-mapped interface.

2.2.4.1. Connectivity

The PHY Lite for Parallel Interfaces IP exposes the Avalon memory-mapped interfaceswhen you enable the dynamic reconfiguration feature. The connectivity of the PHY Litefor Parallel Interfaces Intel Agilex FPGA IP to the Avalon memory-mapped interfacesmust be performed via Calibration IP. One Calibration IP must be shared acrossdifferent PHY Lite for Parallel Interfaces IPs within the same row. For example, all IPsin the bottom row are connected to one Calibration IP and all IPs in the top row areconnected to another Calibration IP. This Calibration IP does not perform anycalibration for the PHY Lite for Parallel Interfaces IP. The Calibration IP only providesan access path (Avalon memory-mapped bus) to all the registers of interest forreconfiguration.

2.2.4.2. Reconfiguration Features and Register Addressing

Each reconfigurable feature of the interface has a set of control registers with anassociated memory address to store the reconfigurable settings; however, this addressis placement dependent. If PHY Lite for Parallel Interfaces IPs and the ExternalMemory Interface IPs share the same I/O column, you must track the addresses ofthe interface lanes and the pins.

The following two sets of control registers store the reconfiguration feature settings:

• Control/status registers (CSR)—You can only read the values of these registers.The values are set through the IP parameters. The CSR registers contain thedefault setting in the IP.

• Avalon memory-mapped registers—You can read and write to these registers usingAvalon interface. Perform an RTL simulation to show an accurate timing whichcorrelates to the hardware operation.

2.2.4.2.1. Control Registers Addresses

For the PHY Lite for Parallel Interfaces Intel Agilex FPGA IP, the address register mapis automatically generated when the IP is generated. The address register map can beobtained in the ip/ed_synth/<PHY Lite IP folder>/altera_arch_fm_xxx/synth/addr_map.vh.

Table 8. Control Register Addresses Description

Feature Bit Description

Pin Output Delay [26:24] The Avalon controller calibration bus base address. Value is fixed to3’h3.

[23:21] Reserved with value 3’h0.

[20:13] The lane address of an interface.

continued...




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[12:8] The address for the physical location of a pin within a lane.

[7:0] Reserved with value 8’d0

Pin Input Delay [26:24] The Avalon controller calibration bus base address. Value is fixed to3’h3.



[12:9] Reserved with value 4’hC.

[8:7] DQ pin sets to access.• 2'h1: DQ 0 to DQ 5• 2'h2: DQ 6 to DQ11

[6:4] Specific DQ pin to access.• 3'h0: DQ 0 and DQ 6• 3'h1: DQ 1 and DQ 7• 3'h2: DQ 2 and DQ 8• 3'h3: DQ 3 and DQ 9• 3'h4: DQ 4 and DQ 10• 3'h5: DQ 5 and DQ 11


Strobe Input Delay [26:24] The Avalon controller calibration bus base address. Value is fixed to3’h3.



[12:0] Reserved with value 13'h18E0.

Strobe Enable Phase [26:24] The Avalon controller calibration bus base address. Value is fixed to3’h3.



[12:0] Reserved with value 13'h18F0.

Strobe Enable Delay [26:24] The Avalon controller calibration bus base address. Value is fixed to3’h3.



[12:0] Reserved with value 13'h1808.

Read Valid Delay [26:24] The Avalon controller calibration bus base address. Value is fixed to3’h3.



[12:0] Reserved with value 13'h180C.

2.2.4.2.2. Control Registers

When you generate a read operation to the control registers addresses, the Avaloninterface returns a set of values from the control registers.




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Table 9. Control Register Bit DescriptionThis table shows the definition of the bits for each control register.


Pin Output Delay [31:13] Reserved.

[12:0] Phase value.• Strobe minimum setting: Refer to the Output and Strobe

Enable Minimum and Maximum Phase Settings topic.• Strobe maximum setting: Refer to the Output and Strobe

Enable Minimum and Maximum Phase Settings topic.• Incremental delay: 1/128th VCO clock period.The CSR value for DQS is set through the Output Strobe Phaseparameter during IP instantiation.Note: The pin output delay switches from the CSR register value

to the Avalon register value after the first Avalon write.The delay is only reset to the CSR register value on areset of the interface.

Pin Input Delay [31:13] Reserved.

[12] Enable bit to select access to Avalon register or CSR register.• 0 = Delay value is 0. CSR register is not available for this

feature.• 1 = Select delay value from Avalon register.

[11:9] Reserved.

[8:0] Delay value.• Minimum setting: 0• Maximum setting: 511 steps• Incremental delay: 1/256th VCO clock period

Strobe Input Delay [31:13] Reserved.

[12] Enable bit to select access to Avalon register or CSR register.• 0 = Delay value is 0. CSR register is not available for this

feature.• 1 = Select delay value from Avalon register.Modifying these values must be done on all lanes in a group.

[11:10] Reserved.

[9:0] • Minimum setting: 0• Maximum setting: 1023 steps• Incremental Delay: 1/256th VCO clock periodModifying these values must be done on all lanes in a group.

Strobe Enable Phase [31:13] Reserved.

[12] Enable bit to select access to Avalon register or CSR register.• 0 = Select delay value from CSR register. The CSR value is set

through the Capture Strobe Phase Shift parameter duringIP instantiation.

• 1 = Select delay value from Avalon register.Modifying these values must be done on all lanes in a group.

[11:10] Reserved.

[9:0] • Minimum setting: 0• Maximum setting: 1023 VCO clock periods• Incremental delay: 1/256th VCO clock periodModifying these values must be done on all lanes in a group.

continued...




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Strobe Enable Delay [31:16] Reserved.

[15] Enable bit to select access to Avalon register or CSR register.• 0 = Select delay value from CSR register• 1 = Select delay value from Avalon registerModifying these values must be done on all lanes in a group.

[14:6] Reserved.

[5:0] Delay value.• Minimum setting: 0 external clock cycles• Maximum setting: 63 external memory clock cycles• Incremental delay: 1 external memory clock cycleModifying these values must be done on all lanes in a group.

Read Valid Delay [31:16] Reserved

[15] Enable bit to select access to Avalon register or CSR register.• 0 = Select delay value from CSR register• 1 = Select delay value from Avalon registerModifying these values must be done on all lanes in a group.

[14:7] Reserved.

[6:0] Delay value.• Minimum setting: 0 external clock cycles• Maximum setting: 127 external memory clock cycles• Incremental delay: 1 external memory clock cycleModifying these values must be done on all lanes in a group.

Example Structure of Address Map (addr_map.vh)

This example shows the address value, mask value, delay field offset, and delay fieldwidth of an address map (addr_map.vh file). The address value is generated basedon information in the Control Register Addresses Description table. The mask value isto be masked with the 32-bit data register pin output delay in the Control DataRegister Bit Description table. The delay width of value 13 corresponds to bit 12 to bit0 for pin output delay in the Control Data Register Bit Description table.




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Figure 14. Example Structure of Address Map

Pin DQ4 is skipped to pin 6 because the strobe pins are reserved at pin 4 and pin 5.

localparam GROUP_0_PIN_0_OUTPUT_DATA_DELAY__ADDR = 27'h30000D0;

localparam GROUP_0_PIN_0_OUTPUT_DATA_DELAY__MASK = 32'h1fff;

localparam GROUP_0_PIN_0_OUTPUT_DATA_DELAY__PHASE_DELAY__FIELD_OFFSET = 0;

localparam GROUP_0_PIN_0_OUTPUT_DATA_DELAY__PHASE_DELAY__FIELD_WIDTH = 13;





























Related Information

• Output and Strobe Enable Minimum and Maximum Phase Settings on page 22Provides the strobe minimum and maximum settings for the control registerspin output delay feature.

• Control Registers Addresses on page 17Provides the information to generate address value in the address map.

2.2.4.3. Dynamic Reconfiguration Guidelines

The PHY Lite for Parallel Interfaces Intel Agilex FPGA IP allows you to dynamicallyreconfigure the features of the interface. However, performing calibration is anapplication-specific process. This section provides the general guidelines for calibratingIntel Agilex I/O architecture.

2.2.4.3.1. Strobe Enable Windowing

The read pointer in the read FIFO buffer resets when read intervals are far apart (80core clock cycles). However, the data inside the FIFO is not cleared. Therefore, use analternating pattern to find the end to the strobe-enable window to avoid reading staledata in the FIFO.




21


2.2.4.3.2. Output and Strobe Enable Minimum and Maximum Phase Settings

When dynamically reconfiguring the interpolator phase settings, keep the valueswithin the ranges in the following table to ensure proper operation of the circuitry.

Table 10. Output and Strobe Enable Minimum and Maximum Phase Settings

VCOMultiplication

Factor

Core Rate Minimum Interpolator Phase MaximumInterpolator

PhaseOutput Bidirectional Bidirectional withOCT Enabled

1 Full 0x080 0x100 0x100 0xA80

Half 0x080 0x100 0x100 0xBC0

Quarter 0x080 0x100 0x100 0xA00

2 Full 0x080 0x100 0x180 0x1400

Half 0x080 0x100 0x180 0x1400

Quarter 0x080 0x100 0x180 0x1400

4 Full 0x080 0x100 0x280 0x1FFF

Half 0x080 0x100 0x280 0x1FFF

Quarter 0x080 0x100 0x280 0x1FFF

8 Full 0x080 0x100 0x480 0x1FFF

Half 0x080 0x100 0x480 0x1FFF


2.3. Getting Started

You can instantiate the PHY Lite for Parallel Interfaces Intel Agilex FPGA IP from IPCatalog in Intel Quartus Prime software. Intel provides an integrated parameter editorthat allows you to customize this IP to support a wide variety of applications.

This IP is located in Libraries Basic Functions I/O of the IP catalog.

Related Information

• Introduction to Intel FPGA IP CoresProvides general information about all Intel FPGA IP cores, includingparameterizing, generating, upgrading, and simulating IP cores.

• Creating Version-Independent IP and Qsys Simulation ScriptsCreate simulation scripts that do not require manual updates for software or IPversion upgrades.

• Project Management Best PracticesGuidelines for efficient management and portability of your project and IP files.




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https://www.intel.com/content/www/us/en/programmable/documentation/mwh1409960181641.html#esc1444754592005


2.3.1. Parameter Settings

Table 11. PHY Lite for Parallel Interfaces IP Parameter Settings

GUI Name Values DefaultValues

Description

Parameter

Number of groups 1 to 4 1 Number of data and strobe groups in theinterface. The value is set to 1 by default.

General Tab- these parameters are set on a per interface basis

Clocks

Interface clock frequency 100 MHz - 1200MHz

533.0 MHz External interface clock frequency.

Use recommended PLLreference clock frequency

On, Off On If you want to calculate the PLL reference clockfrequency automatically for best performance,turn on this option.If you want to specify your own PLL referenceclock frequency, turn off this option.

PLL reference clock frequency Dependent oninterface clock

frequency

133.25 MHz PLL reference clock frequency. You must feed aclock of this frequency to the PLL referenceclock input of the memory interface.Select the desired PLL reference clock frequencyfrom the drop-down list. The values in the listchanges when you change the interface clockfrequency or the user clock rate logic.

VCO clock frequency Calculatedinternally by PLL

1066.0 MHz The frequency of this clock is calculatedinternally by the PLL based on the interfaceclock and the core clock rate.

Clock rate of user logic Quarter, Half, Full Quarter Determines the clock frequency of user logic inrelation to the memory clock frequency. Forexample, if the memory clock sent from theFPGA to the memory device is toggling at 800MHz, a "Quarter rate" interface means that theuser logic in the FPGA runs at 200 MHz.

Dynamic Reconfiguration

Use dynamic reconfiguration On, Off Off Exposes an Avalon memory-mapped interface,allowing you to control the configuration of thePHY Lite for Parallel Interfaces IP settings.Note: The PHY Lite for Parallel Interfaces Intel

Agilex FPGA IP does not support dynamicreconfiguration feature in the IntelQuartus Prime v20.3.

I/O Settings

I/O standard SSTL-121.2-V POD

SSTL-12 Specifies the I/O standard of the interface'sstrobe and data pins written to the .qip file ofthe IP instance.

Reference clock I/Oconfiguration

Single-ended,True Differential

with on-chiptermination,

True Differentialwithout on-chip

termination

Single-ended Specify the reference clock I/O configuration.

Group <x> - these parameters are set on a per group basiscontinued...




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Description

Group <x> Pin Settings

Pin type Input, Output,Bidirectional

Bidirectional Direction of data pins. This value is set toBidirectional by default.

Pin width 1 to 45 (4) 9 Number of pins in this data/strobe group. Thepin width includes the number of strobe pins.

DDR/SDR DDR, SDR DDR Double/single data rate.

Group <x> Input Path Settings

Read latency 7 to 63 externalinterface clock

cycles

7 Expected read latency of the external device inmemory clock cycles.Refer to the Read Latency table for minimumread latency settings based on FPGA core clockrate.

Capture strobe phase shift 0, 45, 90, 135,180

90 Internally phase shift the input strobe relative toinput data.

Group <x> Output Path Settings

Write latency 0 to 3 0 Additional delay added to the output data inmemory clock cycles.Refer to the Write Latency table for writelatency settings based on FPGA core clock rate.

Output strobe phase 0, 45, 90, 135,180

90 Phase shift of the output strobe relative to theoutput data.

Group <x> General Strobe SettingsNote: These parameters are disabled when Copy parameters from another group is enabled.

Strobe configuration Differential Differential Select the type of strobe.Note: The differential strobe configuration uses

a differential input buffer, whichproduces a single clock for the captureDDIO and read FIFO. The output pathfunctionality is the same.

Refer to the I/O Standards table for a list ofsupported I/O standards.

Group <x> OCT Settings

OCT enable size 0 - 15 1 Specifies the delay between the OCT enablesignal assertion and the dqs_enable signalassertion. You must set a value that is largeenough to ensure that the OCT is turn on beforesampling input data.

Use Default OCT Values On, Off On Use default OCT values based on the I/Ostandard parameter setting.

Input OCT Value 60 ohm withcalibration, 50

ohm withcalibration

60 ohm withcalibration

Specifies the group's data and strobe inputtermination values to be written to the .qip ofthe IP instance. The list of legal values isdependent on the I/O standard parametersetting. Refer to the I/O Standards table.Disable the Use Default OCT Valuesparameter to select the desired input OCT value.

continued...

(4) The maximum value varies depending on the configuration, such as number of groups,Quarter Rate/Half Rate/Full Rate, and single-ended or differential PLL reference clock.




24



Description

Output OCT Value 34 ohm withcalibration, 40

ohm withcalibration

40 ohm withcalibration

Specifies the group's data and strobe inputtermination values to be written to the .qip ofthe IP instance. The list of legal values isdependent on the I/O standard parametersetting. Refer to the I/O Standards tablesupported termination values.Disable the Use Default OCT Valuesparameter to select the desired output OCTvalue.

Pin Placement

Physical Sub-bank ID 0–15 0 ID of the physical sub-bank to be used forplacement.Refer to diagrams in the Intel Agilex I/O Sub-bank Interconnects topic.

Pin Parameter Settings On, Off Off By default, all the data pins are placed adjacentto each other with no gap between the pins.Enable this option if require a gap between thedata pins.Refer to the Guidelines: Group Pin Placementtopic for pin placement guidelines for PHY Litefor Parallel Interfaces Intel Agilex FPGA IP.

Pin Placement Settings Comma separatedvalues

— Enter the location list of the data pins.Provide the data pins location list in values. Forexample, enter value of 0, 1, 8, 9 to placedata[0] on pin 0, data[1] on pin 1, data[2] onpin 8, and data[3] on pin 9 of the I/O bank. Inthis case, pin 2 to pin 7 are not used.Refer to the Guidelines: Group Pin Placementtopic for pin placement guidelines for PHY Litefor Parallel Interfaces Intel Agilex FPGA IP.

Related Information

• Table 12 on page 26For more information about the IP read latency values.

• Table 13 on page 26For more information about the IP write latency values.

• I/O Standards on page 29For more information about the supported I/O standards in Intel Agilexdevices.

• Intel Agilex I/O Sub-bank Interconnects on page 8Provides the physical sub-bank ID for pin placement.

• Guidelines: Group Pin Placement on page 31For more information about pin placement guidelines in Intel Agilex devices.




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2.3.1.1. Read Latency

Table 12. Minimum Read LatencyThis table shows the minimum read latency value supported by PHY Lite for Parallel Interfaces Intel AgilexFPGA IP based on the core clock rate and VCO multiplier factor settings.

Core Clock Rate VCO Multiplier Factor Read Latency (External Memory ClockCycle)

Quarter rate 1 7

2 7

4 7

8 7

2.3.1.2. Write Latency

Table 13. Maximum Write LatencyThis shows the maximum write latency value supported by PHY Lite for Parallel Interfaces Intel Agilex FPGA IPbased on the core clock rate and VCO multiplier factor settings.

Core Clock Rate VCO Multiplier Factor Write Latency (External Memory ClockCycle)

Quarter rate 1 3

2 3

4 3

8 2

2.3.2. Signals

2.3.2.1. Clock and Reset Interface Signals

Table 14. Clock and Reset Interface Signals

Signal Name Direction Width Description

ref_clk Input 1 Reference clock for the PLL. The reference clock must besynchronous with group_strobe_in to ensure the dqs_enablesignal is in-sync with group_strobe_in.

reset_n Input 1 Resets the interface. Deassertion of this signal should besynchronous to the ref_clk.

interface_locked Output 1 Interface locked signal from PHY Lite for Parallel Interfaces IntelAgilex FPGA IP to the core logic. This signal indicates that the PLLand PHY circuitry are locked.Data transfer should starts after the assertion of this signal.

core_clk_out Output 1 Use this core clock in the core-to-periphery transfer of soft logicdata and control signals.The core_clk_out frequency depends on the interfacefrequency and clock rate of user logic parameter.




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2.3.2.2. Output Path Signals

Table 15. Output Path SignalsOutput path signals are signals that are available when you set the Pin Type parameter to either Output orBidirectional. The <n> in the signal names below represents the group number in the IP.


group_oe_from_core Input Quarter-rate: 4 Output enable signal from FPGA core.Synchronous to the core_clk_outoutput from the IP.This signal is shared across allgroups.

group_<n>_data_from_core

InputQuarter rate-DDR: 8 x PIN_WIDTHQuarter-rate SDR: 4 x PIN_WIDTH

Data signal from Intel FPGA core.Synchronous to the core_clk_outoutput from the IP.

group_strobe_out_en

Input Quarter-rate: 4 Strobe output enable from FPGAcore. Synchronous to thecore_clk_out output from the IP.This signal is shared across allgroups.

group_<n>_data_out/group_<n>_data_io

Output/Bidirectional

1 to 34 Data output from the IP. Synchronousto the group_<n>_strobe_out orgroup_<n>_strobe_io output fromthe IP.If the Pin Type parameter is set toOutput, the group_<n>_data_outsignals are used. If the Pin Typeparameter is set to Bidirectional,the group_<n>_data_io signals areused.

group_<n>_strobe_out/group_strobe_io/group_<n>_strobe_io


1 Positive output strobe from the IP. Ifthe Pin Type is set to Output, thegroup_<n>_strobe_out signal isused. If the Pin Type is set toBidirectional thegroup_<n>_strobe_io signal isused.

group_<n>_strobe_out_n /group_<n>_strobe_io_n


1 Negative output strobe fro the IP.This is used if the StrobeConfiguration is set to Differential.If the Pin Type is set to Output, thegroup_<n>_strobe_out_n signal isused. If the Pin Type is set toBidirectional, thegroup_<n>_strobe_io_n signal isused.




27


2.3.2.3. Input Path Signals

Table 16. Input Path SignalsInput path signals are signals that are available when you set the Pin Type parameter to Input orBidirectional. The <n> in the signal names below represents the group number in the IP.


group_<n>_data_to_core

Output Quarter-rate DDR: 8 x PIN_WIDTHQuarter-rate SDR: 4 x PIN_WIDTH

Output data to the core logic. Validon group_<n>_rdata_valid.

Synchronous to the core_clk_outoutput from the IP.

group_rdata_en Input Quarter-rate: 4 This signal represents the number ofexpected words to read from the

external device.This signal is set to high after a readcommand is issued. Synchronous tothe core_clk_out output from the

IP.When using the IP as a receiver,

assert this signal afterinterface_locked signal is

asserted and group_strobe_in isstable.

This signal is shared across allgroups.


Output Quarter-rate: 4 This signal determines which data arevalid when reading from Read FIFO.

Delayed by READ_LATENCY withmargin and aligned to the core clockrate. For example, in quarter-rate,the delay is a multiple of 4 external

clock cycles.Synchronous to the core_clk_out

output from the IP.

group_<n>_data_in/

group_<n>_data_io

Input/Bidirectional

1 to 34 Input and output data from/toexternal device. Synchronous to the

group_<n>_strobe_in orgroup_<n>_strobe_io input. Thefirst data_in must be associated with

positive edge ofgroup_<n>_strobe_in/group_<n>_strobe_io.

If the pin type is set to Input, thegroup_<n>_data_in ports are

used. If the pin type is set tobidirectional, the

group_<n>_data_io ports areused.

group_<n>_strobe_in/

group_<n>_strobe_io

Input/Bidirectional

1 Input and output strobe from/toexternal device. If the pin type is set

to Input, thegroup_<n>_strobe_in signal is

used. If the pin type is set toBidirectional, the

group_<n>_strobe_io signal isused.

group_<n>_strobe_in_n/


Input/Bidirectional

1 Negative strobe from/to externaldevice. This is used if the Strobe

Configuration parameter is set toDifferential. If the pin type is set to

Input, thecontinued...




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group_<n>_strobe_in_n signal isused. If the pin type is set to

Bidirectional, thegroup_<n>_strobe_io_n signal is

used.

2.4. I/O Standards

The PHY Lite for Parallel Interfaces Intel Agilex FPGA IP allows you to set I/Ostandards on the pins associated with the generated configuration. The I/O standardcontrols the available strobe configurations and OCT settings for all groups.

Table 17. I/O Standards and Termination Values for Intel Agilex Devices

I/O Standard Valid Input Terminations (Ω) Valid OutputTerminations (Ω)

RZQ (Ω)

SSTL-12 50, 60 34, 40 240

1.2-V POD 50, 60 34, 40 240

Related Information

I/O Termination in Intel Agilex Devices

2.4.1. Input Buffer Reference Voltage (VREF)

The POD I/O standard allows configurable VREF. By default, the externally providedVREF is used and using an internal VREF requires the following .qsf assignments:

set_instance_assignment -name VREF_MODE <mode> -to <pin_name>

The VREF settings are at the lane level, so all pins using a lane must have the sameVREF settings including general-purpose I/Os (GPIO).

Note: Calibrated VREF mode is not supported in Intel Quartus Prime v20.3.

Table 18. VREF_MODE Description

VREF Mode Description

EXTERNAL Use the external VREF. This is the default.

VCCIO_45 Use internal VREF generated using static VREF code. VREF is 45% of VCCIO









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Figure 15. VREF

Input Buffer

+

-Vref

R

R

VCCIO

Internal VREF

6 bits binary weighted resistors dividor

6 bits Static VREF Code6 bits calibrated VREF code from Avalon memory-mapped bus

VREF Calibration Block

+

-

VCCIO

Rt

External VREF

Resistor Ladder

2.4.2. On-Chip Termination (OCT)

PHY Lite for Parallel Interfaces Intel Agilex FPGA IP provides valid OCT settings foreach group (refer to I/O Standards on page 29). These settings are written to the .qipof the instance during generation. If you select an I/O standard that supports OCT inthe General tab, you can use the OCT blocks provided in the Intel Agilex devices.

You can instantiate the OCT block in one of two ways:

• Using RZQ_GROUP assignment in the assignment editor, or

• Manual insertion of OCT block

2.4.2.1. RZQ_GROUP Assignment

The RZQ_GROUP assignment creates the OCT Intel FPGA IP without modifying the RTL.The Fitter searches for the rzq pin name in the netlist. If the pin does not exist, theFitter creates the pin name along with the OCT Intel FPGA IP and its correspondingconnections. This allows you to create a group of pins to be calibrated by an existingor non-existing OCT and the Fitter ensures the legality of the design. You mustassociate the terminated pins of the PHY Lite for Parallel Interfaces Intel Agilex FPGAIP instance with an RZQ pin at the system level manually.




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Use the following steps to set RZQ pin locations for the IP:

1. Generate the IP or instantiate the IP into your project.

2. You can view the available RZQ pins location in the Pin Planner. Go to PinPlanner Tasks OCT Pins and double click the RZQ. The available RZQ pinsare display in the pin grid diagram.

3. You can modify the qsf in your project to change the default RZQ location usingthe following command:

set_location_assignment <rzq_capable_pin_location> –to <user_defined_rzq_pin_name>

4. Use the following command to associate the terminated pins of the IP with theRZQ pin:

set_instance_assignment -name RZQ_GROUP <rzq_pin_name> -to <phylite_strobe_pin>

set_instance_assignment -name RZQ_GROUP <rzq_pin_name> -to <phylite_data_pin[*]>

where * represents all the data pins within the same group.

This is an example of a qsf file with modified RZQ pin location assignments:

set_location_assignment PIN_AH3 -to octrzqset_instance_assignment -name IO_STANDARD "1.5 V" -to octrzqset_instance_assignment -name RZQ_GROUP OCTRZQ -to group_0_io_interface_conduit_end_io_strobe_ioset_instance_assignment -name RZQ_GROUP OCTRZQ -to group_0_io_interface_conduit_end_io_data_io[*]

5. Compile the project.

6. To verify that the Intel Quartus Prime has successfully created and assigned theRZQ pin to the correct location, go to Pin Planner Node Name and look for<user_defined_rzq_pin_name> with the assigned pin location in the list.

2.5. Design Guidelines

2.5.1. Guidelines: Group Pin Placement

Follow these guidelines to place the PHY Lite for Parallel Interfaces Intel Agilex FPGAIP group pins.

1. All groups in a PHY Lite for Parallel Interfaces Intel Agilex FPGA IP must be placedacross a contiguous set of lanes. The number of lanes depends on the number ofpins used by the group. Refer to the Intel Agilex Input DQS Clock Tree for moreinformation about the number lanes used per pin width.

2. A PHY Lite for Parallel Interfaces Intel Agilex FPGA IP must fit within one I/O sub-bank and must not span across multiple I/O sub-banks. One I/O sub-bank cansupport only one IP instance.

3. Two groups within a PHY Lite for Parallel Interfaces Intel Agilex FPGA IP cannotshare an I/O lane.

4. When there are multiple groups within an IP instance, the pins must be set toeither bidirectional or unidirectional (can be a mix of input and output groups). Donot mix bidirectional and unidirectional pin types in the same IP instance.




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5. If an input group uses ×36 DQS/strobe tree, another group must be set as anoutput group to utilize the remainder I/O lane in the same I/O sub-bank.

6. If a group is set to bidirectional pin type and uses the ×36 DQS/strobe tree, noother groups are allowed to be in the same IP.

7. Control signals are shared across all groups within an IP instance.

8. Pins that are not used in an I/O sub-bank cannot be used as GPIO pins.

9. You must calibrate the I/Os within the same I/O lane using the same OCTcalibration block. You can associate the terminated pins of the PHY Lite for ParallelInterfaces Intel Agilex FPGA IP instance with an RZQ pin through the RZQ_GROUPassignment.

10. You can place the data pin locations either automatically or manually in the PinPlacement tab. You must enter your desired Physical Sub-Bank ID. Refer todiagrams in the Intel Agilex I/O Sub-bank Interconnects topic for the physical sub-bank ID for pin placement.

11. The PHY Lite for Parallel Interfaces Intel Agilex FPGA IP must be placed at theQuartus-IP Generation stage because the pin placements are not available usingQSF Assignments.

Table 19. Pin Index Mapping

I/O Bank Pin Index I/O Sub-bank Pin Index Lane Sub-bank Location

0-11 0-11 (pins 4 and 5 arereserved for strobes)

0 Bottom


1


2


3


0 Top


1


2


3

For more information about strobe and clock pin indexes, refer to the device pin-outfiles.




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Automatic and Manual Pin Placement

Follow these guidelines for automatic and manual pin placements:

1. Go to the Pin Placement tab.

2. To identify the sub-bank:

• Default value = 0.

• Use only bonded sub-banks. The bonded sub-banks are unshaded in theExample of Pin Placement for a Single Group diagram.

• This example uses sub-bank ID =1 that is located at Bank 3A.

Figure 16. Example of Pin Placement for a Single GroupThis example uses the Intel Agilex AGF022 and AGF027 devices, package R25A.

0 2 4 6 9 11

1 3 5 7 8 10

3. Each sub-bank has 48 pins.

4. In automatic mode, by default, all pins inside a group are placed in a tightlypacked manner.

5. In manual mode, you can customize the pin placement within the sub-bankaccording to your requirement.

• By default, all data pins are contiguous in sequential order.

• For example, for a pin width of 8, data pins are assigned to Pin 0, 1, 2, and 3in Lane 1 and Lane 2.

• You can choose to specify the placements manually, by providing a comma-separated list of pin locations, one for each data pin in Pin Placement Settings.

• The comma-separated list of pin locations is based on the index within an I/Osub-bank. Refer to the Pin Index Mapping table.




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Figure 17. Example Settings for Automatic and Manual Pin Placement

Related Information

• Intel Agilex I/O Sub-bank Interconnects on page 8Provides the physical sub-bank ID for pin placement.

• Pin-Out Files for Intel FPGA DevicesFor pin index and I/O bank references, refer to the specific device pin-out file.

• Intel Agilex Input DQS/Strobe Tree on page 10

2.5.2. Reference Clock

You are recommended to source the reference clock to the PHY Lite for ParallelInterfaces Intel Agilex FPGA IP from a dedicated clock pin. Use the clock pin in the I/Osub-bank with the following command:

set_location_assignment <PIN_NUMBER> -to <pll_ref_clock_signal_name>

2.5.3. Reset

You can source the reset to the PHY Lite for Parallel Interfaces Intel Agilex FPGA IPfrom an external pin or from the core. If you source the reset from an external pin,you must configure the I/O standard of the reset signal in the .qsf file with thefollowing command:

set_location_assignment <PIN_NUMBER> -to <signal_name>

2.6. Design Example

The PHY Lite for Parallel Interfaces Intel Agilex FPGA IP is able to generate a designexample that matches the same configuration chosen for the IP. The design example isa simple design that does not target any specific application; however you can use thedesign example as a reference on how to instantiate the IP and what behavior toexpect in a simulation.

You can generate a design example by clicking Generating Example Design in theIP Parameter Editor.




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Note: The PHY Lite for Parallel Interfaces Intel Agilex FPGA IP supports only simulationdesign example for variant without dynamic reconfiguration.

Note: The .qsys files are for internal use during design example generation only. You shouldnot edit the files.

2.6.1. Generate the Design Example


The software generates a user defined directory in which the design example filesreside.

There are two variants of design example available for PHY Lite for Parallel InterfacesIntel Agilex FPGA IP:

• Design example for variant without dynamic reconfiguration

• Design example for variant with dynamic reconfiguration

Table 20. PHY Lite for Parallel Interfaces Intel Agilex FPGA IP Design Example Variants

Design Example Variant Design File Description

DynamicReconfiguration

On ed_synth.qsys (synthesisonly)

Consists of PHY Lite for Parallel Interfaces IPinstance with Calibration IP.

ed_sim.qsys (simulation only) Consists of PHY Lite for Parallel Interfaces IPinstance with Calibration IP, IOSSM Tester, TesterCore, and Tester I/O.

Off ed_synth.qsys (synthesisonly)

Consists of PHY Lite for Parallel Interfaces IPinstance.

ed_sim.qsys (simulation only) Consists of PHY Lite for Parallel Interfaces IPinstance with Tester Core and Tester I/O.

2.6.1.1. Design Example without Dynamic Reconfiguration

When the Enable dynamic reconfiguration option is not selected, the Intel QuartusPrime software generates a design example of PHY Lite for Parallel Interfaces IPwithout a dynamic reconfiguration module. This design example consists of simulationand synthesis design files.

2.6.1.1.1. Generate the Synthesis Design Example

The make_qii_design.tcl generates a synthesizable hardware design example andan Intel Quartus Prime project, ready for compilation.

To generate synthesizable design example, run the following script at the end of IPgeneration:

quartus_sh -t make_qii_design.tcl

To specify an exact device to use, run the following script:

quartus_sh -t make_qii_design.tcl [device_name]

This script generates a qii directory containing a project called ed_synth.qpf. Youcan open and compile this project using the Intel Quartus Prime software.




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2.6.1.1.2. Generate the Simulation Design Example

The make_sim_design.tcl generates a simulation design example and tool-specificscripts to compile and elaborate the necessary files.

To generate the design example for a Verilog or a mixed-language simulator, run thefollowing script at the end of IP generation:

quartus_sh -t make_sim_design.tcl VERILOG

To generate the design example for a VHDL-only simulator, run the following script:

quartus_sh -t make_sim_design.tcl VHDL

This script generates a sim directory containing one subdirectory for each supportedsimulation tools. Each subdirectory contains the specific scripts to run simulation usingthe corresponding tool.

The simulation design example provides a generic example of the core and I/Oconnectivity for your IP configuration. Functionally, the simulation triggers read andwrite operations over each group in your configured IP. The following diagram shows asimple one group PHY Lite for Parallel Interfaces Intel Agilex FPGA IP instantiation inthe testbench.

Figure 18. High-Level View of the Simulation Design Example with One Group

data

strobedata DRAM clockCore clock

PHY Lite DUTCore clockRead/Write

enable

Tester core Tester ioPHY Lite Tester

2.6.1.2. Dynamic Reconfiguration Design Examples

When you select the Use dynamic reconfiguration option and click GenerateExample Design, the Intel Quartus Prime software generates the dynamicreconfiguration simulation and synthesis-based examples.

2.6.1.2.1. Generate the Synthesis Design Example

The make_qii_design.tcl generates a synthesizable hardware design example andan Intel Quartus Prime project, ready for compilation.




36






This script generates a qii directory containing a project called ed_synth.qpf. Youcan open and compile this project using the Intel Quartus Prime software.

The synthesis design example provides an example of the core and I/O connectivityfor your IP configuration with Calibration IP as the interface for the Avalon memory-mapped calibration addresses. The connection of Calibration IP to PHY Lite for ParallelInterfaces IP is limited to one calibration IP per row.

Figure 19. Connection of Calibration IP to PHY Lite for Parallel Interfaces IPThis figure shows an example of multiple (five in this example) PHY Lite for Parallel Interfaces IPs within oneI/O row. Thus, only one calibration IP is needed to connect all five PHY Lite for Parallel Interfaces IPs to theCalibration IP.

Calibration IP

User Control/Data Bus I/O

Calibration Bus

PHY Lite


The make_sim_design.tcl generates a simulation design example and tool specificscripts to compile and elaborate the necessary files.








37


This script generates a sim directory containing one subdirectory for each supportedsimulation tools. Each subdirectory contains the specific scripts to run simulation usingthe corresponding tool.

The simulation design example provides an example of the core and I/O connectivityfor your IP configuration with Calibration IP as the interface for the Avalon memory-mapped calibration addresses. The addresses of all the configurable registers aresaved in the addr_map.vh file. The IOSSM Tester block sends a simple sequence(write/read to a delay register) as a sample. Functionally, the simulation triggers readand write operations over each group in your configured IP. The following diagramsshow a simple one group PHY Lite for Parallel Interfaces Intel Agilex FPGA IPinstantiation in the testbench.

Figure 20. Dynamic Reconfiguration Simulation Design Example

IOSSMTester

TesterCore

TesterI/O

Tester

I/OsUser Control/Data Bus PHY Lite

Calibration IPCalibration Bus




38


Figure 21. Write Operation Using Dynamic Reconfiguration

Provides Stimulus for Tx Path

Checks Data for Tx Path

IOSSMTester

TesterCore

TesterI/O

Tester



Read and Write to One Output Delay Register

Traffic

Figure 22. Read Operation Using Dynamic Reconfiguration

Check Data to Core for Rx Path

Provides Stimulus for Rx Path

IOSSMTester

TesterCore

TesterI/O

Tester



Read and Write to One Output Delay Register

Traffic




39


3. PHY Lite for Parallel Interfaces Intel Stratix 10 FPGA IP







Table 21. PHY Lite for Parallel Interfaces Intel Stratix 10 FPGA IP Release Information

Item Description

IP Version 19.3.0



Related Information



The PHY Lite for Parallel Interfaces Intel Stratix 10 FPGA IP utilizes the I/O subsystemin the Intel Stratix 10 devices. The I/O subsystem is located in the I/O columns ofeach Intel FPGA devices. For Intel Stratix 10 devices, each column consists of I/Obanks and IOSSM. The number of I/O banks varies according to device packages.Each bank is a group of 48 I/O pins, organized into four I/O lanes with 12 pins foreach lane. Each I/O lane contains the DDR-PHY input and output path logic for 12 I/Osas well as a DQS logic block. All four lanes in a bank can be combined to form a singledata/strobe group or up to four groups in the same interface. Under certainconditions, two groups from different interfaces can also be supported in the samebank. Refer to the Guidelines: Group Pin Placement for more information about theguidelines to implement multiple interfaces in the same bank.


Send Feedback








Important: All Intel Stratix 10 devices have separate LVDS I/O and 3 V I/O banks. The IntelStratix 10 GX 10M variant has denser LVDS I/O banks with a slightly different I/Obank structure compared to other Intel Stratix 10 variants. The PHY Lite for ParallelInterfaces IP utilizes only the LVDS I/O banks.

Figure 23. Intel Stratix 10 I/O Bank StructureThis figure shows an example of I/O banks in one Intel Stratix 10 device. The I/O banks availability andlocations vary among Intel Stratix 10 devices.

SDM Shared LVDS I/O

HPS Shared LVDS I/O

3 V I/O

3.3 V I/O in 1SG040HF35 and 1SX040HF35 onlyLVDS I/O in all other Intel Stratix 10 FPGAs

LVDS I/O

2N2M2L2K2J2I2H2G2F2E2D2C2B2A

3N3M3L3K3J3I3H3G3F3E3D3C3B3ASDM

6A

6B

6C

7A

7B

7C

2AU12BU12CU12FU12GU12HU121U12JU12KU12LU12MU12NU1

SDM_U1 3LU23KU23JU23IU23HU23GU23FU23EU23DU23CU23BU23AU2

2NU22MU22LU22KU22JU22IU22HU22GU22FU22CU22BU22AU2SDM_U2

U2U1

U12

U10

U20

U22

3AU13BU13CU13DU13EU13FU13GU13HU13IU13JU13KU13LU1

Intel® Stratix® 10 GX 10M FPGA

Other Intel Stratix 10 FPGAs

I/O Lane

I/O Lane

I/O Center

I/O PLL

Hard MemoryController

andPHY Sequencer

I/O DLL

I/O DLL

Clock

Net

work

OCTI/O VR

I/O Lane

LVDS I/O Buffer PairLVDS I/O Buffer PairLVDS I/O Buffer PairLVDS I/O Buffer PairLVDS I/O Buffer PairLVDS I/O Buffer Pair




SERDES & DPASERDES & DPASERDES & DPASERDES & DPASERDES & DPASERDES & DPA




I/O Lane

I/O DLL

I/O DLL

1

1

AA

AA

ZZ

ZZ

99

99

Pin Naming Orientation

Pin Naming Orientation

Pin N

aming

Orie

ntat

ion

Pin N

aming

Orie

ntat

ion

Related Information


• I/O Bank Architecture in Intel Stratix 10 DevicesFor more information about Intel Stratix 10 I/O bank architecture.

• KDB link: Why does the PHY Lite for Parallel Interfaces Intel Stratix 10 FPGA IPcannot be assigned to Bank 3A or 3D when using the Intel Stratix 10 10 1ST040*device?

• Constraining Multiple PHY Lite for Parallel Interfaces to One I/O Bank on page 84




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3.2.1. Top Level Interfaces

The PHY Lite for Parallel Interfaces IP consists of the following ports:




• Avalon memory-mapped configuration bus (available only when DynamicReconfiguration feature is enabled)

Figure 24. Top-Level InterfaceThis figure shows the top-level diagram of the PHY Lite for Parallel Interfaces Intel Stratix 10 FPGA IP interface.

PLLI/O Lane

I/O Lane

Tile Control

I/O Lane


phy_clkphy_clk_phs

core_clk_out



Group

ref_clk



Legend




Intel FPGA Device


Related Information

• Output Path on page 43For more information about the IP output path.

• Input Path on page 46For more information about the IP input path.

• Signals on page 72For more information about the IP data, control, and I/O interfaces.

3.2.2. Clocks

The PHY Lite for Parallel Interfaces Intel Stratix 10 FPGA IP uses a reference clock thatis sourced from a dedicated clock pin to the PLL inside the IP. This PLL provides fourclock domains for the output and input paths.




42


Table 22. PHY Lite for Parallel Interfaces Intel Stratix 10 FPGA IP Clock Domains






Table 23. PHY Lite for Parallel Interfaces Intel Stratix 10 FPGA IP Supported InterfaceFrequencyUse the Timing Analyzer to perform timing closure to ensure your design fulfilled all timing constraints with thesupported frequencies indicated in the table. Full, half, and quarter core clock rate refers to the ratio of thecore clock and interface clock. For example, an interface clock frequency of 800 MHz has full core clock rate of800 MHz, half core clock rate of 400 MHz, and quarter core clock rate of 200 MHz.

Core ClockRate



Full 100 333 100 300 100 233

Half 100 667 100 600 100 467

Quarter 100 1200 100 1200 100 933

3.2.2.1. Clock Frequency Relationships

The following equations describe the relationships between the clock domainsavailable in the PHY Lite for Parallel Interfaces IP core.



3.2.3. Output Path



Block Description


Interpolator Works with the FIFO block to generate the desired output delay. You can dynamically configurethe delay through the Avalon memory-mapped interface. For more information, refer toDynamic Reconfiguration section.





43


Figure 25. Output PathThis figure shows the output path for the PHY Lite for Parallel Interfaces IP.

Write FIFO data_io/data_out

Interpolator

interpolator_clk

data_from_coreoe_from_core

phy_clk

VCO clock

strobe_out_instrobe_out_en strobe_out/strobe_io

PHY Lite for Parallel Interfaces IP CoreTo external interfaceFrom Intel FPGA core

Data path


(1)

(1)

(1)

(2)


Legend

(1)

The following figures show the waveform diagrams for the output path. The delaysshown in the waveforms are just estimation based on simulations and these values aredifferent with different core clock rate and VCO multiplier.

Figure 26. Output Path Write Latency 0This simulation is based on the following PHY Lite for Parallel Interfaces IP configurations:

• Interface Frequency: 1000 MHz

• VCO Multiplier Factor: 1

• User logic clock rate: Quarter rateIntrinsic Delay Write Latency = 0

Indicates the latency from the time the IP issues a write command to the time the external memory device receives the command.

OUTPUT_STROBE_PHASE = 90Signals from core logic to external memory device




44





• User logic clock rate: Quarter rate

Intrinsic Delay Write Latency = 2


Number of clock cycles set in Write latency parameter in Parameter Editor

Signals from core logic to external memory device

OUTPUT_STROBE_PHASE = 90

Related Information

• Output Path Signals on page 73For more information about the IP output path signals.

• Dynamic Reconfiguration on page 49

• How to estimate Intel Arria 10/Intel Stratix 10 PHY Lite Input and Output PathLatency

How-to video on estimating PHY Lite for Parallel Interfaces IP input and outputpath latency in Intel Arria 10 and Intel Stratix 10 devices.

3.2.3.1. Output Path Data Alignment

The data_from_core and oe_from_core signals are arranged in time slices, whichare broken down into the individual pins in the group. The first time slice is on theLSBs of the buses, which matches the Intel FPGA PHY interface (AFI) bus ordering ofthe External Memory Interfaces IP.





Related Information


• AFI 3.0 Specification




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3.2.4. Input Path



Path Description

Data Path Receives data from external device to the FPGA core logic.The data path consists of a PVT compensated delay chain, a DDIO and a read FIFO.• PVT compensated delay chain—Allows per-bit deskew. You can only control the PVT compensated

delay chain over Avalon memory-mapped interface. For more information, refer to the DynamicReconfiguration topic.

• DDIO and read FIFO—Responsible for deserialization with a factor of up to 8 (in DDR quarter-rate).The transfer between the DDIO and the read FIFO is a zero-cycle transfer.

Signals used in this path are:• data_in, data_in_n (input)—Input data from external device. data_in_n is used when data

configuration is set to Differential.• data_io, data_io_n (bidirectional)—Input and output data from/to external device. data_io_n is

used when data configuration is set to Differential.• data_to_core (output)—Output data to the Intel FPGA core.• phy_clk—This is an internal clock signal that provides clock to the blocks used in this path.The IP supports SDR input by sending data on single clock cycle from the external device.



example, center aligning edge-aligned inputs).Signals used in this path are:• strobe_in, strobe_in_n(input)—Input strobe from external device. strobe_in_n is used when

strobe configuration is set to Differential or Complimentary.• strobe_io, strobe_io_n(bidirectional)—Input and output strobe from/to external device.

strobe_io_n is used when strobe configuration is set to Differential or Complimentary.• dqs_clean(output)—This internal signal is the refined version of strobe_in signal.• dqs(input)—This internal signal is an input strobe to DDIO and Read FIFO in the data path, after




the read enable on the Read FIFO, and one for the strobe enable. These delays are calculated atgeneration time based on the read latency that you provide. Individual control is not necessary, but ifyou are modifying these delays you can do so individually using dynamic reconfiguration.

• DQS_EN FIFO and interpolator—Used for the strobe enable delay, the DQS_EN FIFO and interpolatorare identical to the Write FIFO and interpolator circuitry in the output path. The DQS_EN FIFO andinterpolator are configured to match the output delay for a group with no additional output delay(Write latency = 0). During dynamic reconfiguration, the DQS_EN FIFO and interpolator can be usedfor fine grained control of the strobe enable signal. Both of these delays are controlled by the Readlatency parameter for the group.

Signals used in this path are:• rdata_valid(output)—This signal determines which data are valid when reading from Read FIFO.

This signal is delayed by the Read latency value set in the parameter editor.• rdata_en(input)—This signal represents the number of expected words to read from the external

device.• dqs_enable_in(input)—This is an internal signal that provides dqs delay value to the pstamble_reg

module to process a refined dqs signal.continued...




46


Path Description

• dqs_enable_out(output)— This is an internal strobe with the delayed value specified by thedqs_enable_in signal.

• phy_clk—This is an internal clock for VFIFO and Read FIFO modules.• phy_clk_phs—This is an internal clock for the interpolator.• interpolator_clk—This is an internal clock for DQS_EN FIFO module.



data_to_core data_in

phy_clk

strobe_in

dqs

Delay Chain (PVT)


DQS_EN FIFO

Interpolator

interpolator_clk

dqs_enable_out

phy_clk_phs

VFIFO

read_enable

dqs_enable_inrdata_en

phy_clk

rdata_valid

data_io

strobe_iostrobe_in_n

6

1 2

34

5 56

n n = sequence number. This represent read operationsequence.

To Intel FPGA core PHY Lite for Parallel Interfaces IP Core To external interface

Data path

Strobe path


Control signal

data_in_n

data_io_n

strobe_io_n

Legend:

Internal signals

(1)

(1)

(1)

(1)

(1)

(1)

(1)(1)

(1)

(1)

(2)



(3)




47




Operation







The following figures show the waveform diagrams for the input path. The delaysshown in the waveforms are just estimation based on simulations and these values aredifferent with different core clock rate and VCO multiplier.

Figure 30. Input Path Read Latency 7This simulation is based on the following PHY Lite for Parallel Interfaces IP configurations:




Intrinsic Delay Read Latency =7 PHY Lite for Parallel Interfaces Internal Delay

CAPTURE_PHASE_SHIFT = 90

Debug signals are inside the lane wrapper. Only available for waveform debugging.


Measured from rdata_en assertionto mem_rd assertion, sampling on the rising edge of mem_clk.

Number of clock cycles set through Read latency parameter in Parameter Editor

Latency between read data received to rdata_valid assertion.

Related Information


• Input Path Signals on page 74For more information about the IP input path signals.




48


• How to estimate Intel Arria 10/Intel Stratix 10 PHY Lite Input and Output PathLatency

How-to video on estimating PHY Lite for Parallel Interfaces IP input and outputpath latency in Intel Arria 10 and Intel Stratix 10 devices.

3.2.4.1. Input Path Data Alignment

The bus ordering of data_to_core, rdata_en, and rdata_valid is identical to theordering of the output path. That is, the LSBs of the bus hold the first time slice ofdata received.

The rdata_valid delay is always set by the IP to match the rdata_en alignment.For example, quarter-rate delays are multiples of four external memory clock cycles(one quarter rate clock cycle).

Figure 31. Example Input (Quarter Rate DDR) - AlignedThe waveform shows an example of aligned reads on the input path of the PHY Lite for Parallel Interfaces IP. Atthe first rising edge of the core_clk_out signal, the group_0_rdata_en bus shows data of 4'hf, whichrepresents all incoming data are aligned. The group_0_rdata_valid bus shows the data of 4'hf, whichrepresents all incoming data are valid. Therefore, the incoming read data on the group_0_data_to_core busmatches the data seen on the group_0_data_io bus.

Reading from an unaligned memory address is called unaligned reads. Unalignedreads will result in unaligned rdata_valid and data_to_core with data andvalid signals packed to the LSBs. This request causes the IP to do two or more readoperations.

Figure 32. Example Input (Quarter Rate DDR) - UnalignedThe waveform shows an example of unaligned reads on the input path of the PHY Lite for Parallel Interfaces IP.

The data from an unaligned read operation comes in two phases. At the first rising edge of the core_clk_outsignal, the group_0_rdata_en bus shows value of 4'he, which shows there are 6 bytes of incoming data fromgroup_0_data_io bus. On the subsequent clock cycle, the group_0_rdata_en bus shows value of 4'h1,which shows there are 2 bytes of incoming data from group_0_data_io bus.

The valid data are transfer to the IP through the group_0_data_to_core bus. At first rising edge of thecore_clk_out signal, group_0_rdata_valid bus shows a value of 4'h7, which represents the first 6 bytesof the data from the group_0_data_to_core bus are valid and the last 2 bytes are invalid. On thesubsequent clock cycle, group_0_rdata_valid bus shows the value of 4'h1, which shows the last 2 bytes ofthe data from the group_0_data_to_core bus are valid.


Because of the asynchronous nature of the PHY, you must perform calibration toachieve timing closure at a high frequency. At a high level, calibration involvesreconfiguring input and output delays in the PHY to align data and strobes. With thePHY Lite for Parallel Interfaces Intel Stratix 10 FPGA IP, you can perform the




49




calibration by using dynamic reconfiguration feature. The dynamic reconfigurationfeature allows you to modify these delays by writing to a set of control registers usingan Avalon memory-mapped interface.

Important: When the dynamic reconfiguration feature is enabled in Intel Stratix 10 devices, themaximum Avalon memory-mapped interface speed is 167 MHz.

Related Information

• Calibrated VREF Settings on page 79

• Timing Closure: Dynamic Reconfiguration on page 87

3.2.5.1. RTL Connectivity

The PHY Lite for Parallel Interfaces IP exposes the Avalon memory-mapped masterand Avalon memory-mapped slave interfaces when you enable the dynamicreconfiguration feature. If the generated IP is the only PHY Lite for Parallel InterfacesIP (with dynamic reconfiguration) or External Memory Interface IP in the I/O column,connect only the Avalon memory-mapped slave interface with a master in the core.Otherwise, connect Avalon memory-mapped master and slave interfaces as describedin the following section.

3.2.5.1.1. Daisy Chain

The I/O column provides a single physical Avalon memory-mapped interface. All IPs inthe I/O column that require Avalon memory-mapped interface access the samephysical Avalon memory-mapped interface. The system-level RTL for the columnreflects this resource limitation by using a daisy chain to connect all dynamicallyreconfigurable IPs in an I/O column.

The PHY Lite for Parallel Interfaces Intel Stratix 10 FPGA IP exposes a 31-bit Avalonmemory-mapped address, followed by a 4-bit interface ID. These bits are onlyrequired for the daisy chain arbitration in RTL simulation, so they are not synthesizedduring compilation. If only one interface is addressed from the IP, it is sufficient toconnect these bits as the interface’s ID.

Important: When using multiple PHY Lite for Parallel Interfaces IPs, you are required to specifythe IP that is directly connected to the Avalon memory-mapped bus master, using theFirst PHYLite Instance in the Avalon Chain parameter. Do not select theparameter if there is an External Memory Interface IP selected as the first instance inthe chain, available in the same column.




50


Figure 33. Logical RTL View to Physical Column PlacementThis figure shows an example of a daisy chain consisting of the External Memory Interface and PHY Lite forParallel Interfaces Intel Stratix 10 FPGA IP before and after placement.

Notice that all core controllers must go through the arbitration logic that you createdin the core logic to connect to an interface on the daisy chain. The end of the daisychain should have its master output interface tied to 0.

Note: The Fitter rearranges the Avalon address pins during compilation, therefore use thepostfit netlist for proper simulation of the merged I/O column instead of prefit netlist.

3.2.5.2. Address Lookup

If you do not set the pin locations in the .qsf file, the lane addresses and pinplacement to an interface changes every time you compile your design in IntelQuartus Prime software. However, the PHY Lite for Parallel Interfaces Intel Stratix 10FPGA IP is always generated as if the IP core is the only IP in a column, with laneaddresses starting from 0. You need to determine the lane and pin addresses in orderto dynamically reconfigure the calibration settings in the IP.




51


Figure 34. Lane and Pin Placement Dependent AddressesThis figure shows two examples of a placed group with two lanes, 16 data pins and a differential strobe.

Lane Address 0

Lane Address 1

PHY Lite for Parallel Interfaces Intel FPGA IP

strobe_iostrobe_io_ndata_io[0]data_io[1]data_io[2]data_io[3]data_io[4]data_io[5]data_io[6]data_io[7]data_io[8]data_io[9]

data_io[10]data_io[11]data_io[12]data_io[13]data_io[14]data_io[15]

Example 1

Lane Address 8

Lane Address 9


strobe_iostrobe_io_n

data_io[0]

data_io[1]

data_io[2]

data_io[3]

data_io[4]

data_io[5]

data_io[6]

data_io[7]

data_io[8]

data_io[9]

data_io[10]data_io[11]

data_io[12]


data_io[15]

Example 2

To provide a unified way to look up reconfigurable feature addresses for a specificinterface both before and after placement, the address information is stored inmemory in the I/O column. This memory is addressable over the same Avalonmemory-mapped interface used for feature reconfiguration.

You can cache lookups 1 to 4 (8-bytes of information) to have pin and lanetranslations in one look-up.

Table 27. Memory Lookup ComponentsThis table lists the two main components of the memory lookup.

Component Description

Global parameter table Stores pointers to the individual interface parameter tables. The global parameter tablelists all interfaces in the column (both the External Memory Interfaces and PHY Lite forParallel Interfaces Intel Stratix 10 FPGA IPs).

Set of individual interfaceparameter tables

Contain interface specific information. This is where pin-level and lane-level address look-ups are performed.




52


Figure 35. Memory Overview in Intel Stratix 10 Devices

Group 0 Pin 1 Group 0 Pin 0

num_lanes[1:0],num_pins[5:0]

Needed for pin address lookups

Needed for simplifying strobe feature logic address lookups

One per Interface

num_lanes[1:0] starts counting at 0. For example, 0 = 1 lane, 1 = 2 lanes, 2 = 3 lanes, 3 = 4 lanes

Lane address table information: Group X Lane Y = lane_addr[7:0]

Pin address table information: Group X Pin Y = lane_addr[7:0],0xF,pin[3:0] for data and lane_addr[7:0],0xE,pin[3:0] for strobe

B

C

D

D

C

B

Number of Groups

Number of Groups

1’b0,id[3:0],27’h5000000 + pt_ptr1’b0,id[3:0],27’h5000000 + pt_ptr 28’d4

Parameter Table (PHY Lite Specific) 1’b0,id[3:0],27’h5000000 + pt_ptr +

18’h0,group_offset[5:2],2’b00 + lane_ptr[15:0],pin_ptr[15:0]

1’b0,id[3:0],27’h5000000 + lane_ptr + lane_num

Lane Address Table (PHY Lite Specific)

Group 0 Lane 0

1’b0,id[3:0],27’h5000000 + pin_ptr + 17’h0,pin_num[5:0],1’b0

Pin Address Table(PHY Lite Specific)

32-bits (4 Byte Addresses)

1’b0,id[3:0],27’h5000000

Global Parameter Table(One per column, same as EMIF)

1’b0,id[3:0],27’h5000000 + 28’h24 4’b1000,id[3:0], pt_ptr[23:0]

PT_VER[15:0],IP_VER[15:0]Number of Groups

4'h8,id[3:0],8'h00,interface_table_ptr[15:0]A

The MSB of the interface pointer entry in the global parameter table is 1 for PHY Lite interfaces.

A

1

2

3

4

5

6

Address Offset

1’b0,id[3:0],27’h5000000 + pt_ptr 28’d8

21’d0,num_grps,2’b00 + 28h’C

group_offset = grp_num -1

lane_offset[31:16],pin_offset[15:0]

Below are the steps to determine the lane and pin addresses from the lookup tables(the sequence corresponds to the sequence in the Memory Overview in Intel Stratix10 Devices topic):

Table 28. Parameter Table Lookup Operation SequenceThe base address for PHY Lite for Parallel Interfaces Intel Stratix 10 FPGA IP is 27'h5000000.

Legend inMemory

Overview inIntel Stratix 10

Devices

Description

1 Search for Interface Parameter Table in Global Parameter Table (cache once per interface)• 1'b0,id3:0],27'h5000000 + 28'h24 to 1'b0,id3:0],27'h5000000 + 28'h3C

• 1 to 11 look-ups

2 Retrieve number of groups in the interface (cache once per interface)• 1'b0,id[3:0],27'h5000000 + 12'h0,pt_ptr[15:0] + 28'h4

• You can skip this sequence if the number of groups is saved in the core during compilation (forexample, hard coded in RTL logic)

3 Retrieve group information (cache once per group)• 1'b0,id[3:0],27'h5000000 + 12'h0,pt_ptr[15:0] + 28'h8 + grp_num

• Not always necessary

4 Retrieve Lane/Pin Address Offsets for group (cache once per group)• 1'b0,id[3:0],27'h5000000 + 12'h0,pt_ptr[15:0] +

18'h0,group_offset[5:2],2'b00 + 21'd0, grp_num, 2'b00 + 28'hC

5 Perform lane/pin address translation (cache once per pin)

continued...




53


Legend inMemory

Overview inIntel Stratix 10

Devices

Description

• 1'b0,id[3:0],27'h5000000 + 12'h000,lane_ptr[15:0] + lane_num

• 1'b0,id[3:0],27'h5000000 + 12'h000,pin_ptr[15:0] + 17'h0,pin_num[5:0],1'b0

6 Read/Write Avalon Calibration Bus• 1'b0,id[3:0],27'h5000000 + read_from_step_4 + intra_lane_addr

Related Information

Memory Overview in Intel Stratix 10 Devices on page 53

3.2.5.2.1. Strobes

The first pins listed in the pin address lookup table are the strobes. They are alsoidentified by bits[7:4] = 0xE. For separate strobes, the input strobe pin placementalways take precedence. For differential and complementary strobes, the positive pinis the lower index.

Note: You can modify the output phase of differential strobes by writing to either the positiveor negative pin. Only one write is necessary. This is also the case for output-onlycomplementary strobes.

3.2.5.2.2. Parameter Table Example

These figures show examples of designs containing two PHY Lite for Parallel InterfacesIntel Stratix 10 FPGA IPs, each with one bidirectional group composed of 4 data bitsand one strobe. Both interfaces are in the same I/O column and therefore their tablesmust be merged.




54


Figure 36. Parameter Table Example for Intel Stratix 10 DevicesPHY Lite for Parallel Interfaces IP core 0 PHY Lite for Parallel Interfaces IP core 1Addr Data

Merged Column Parameter TableAddr Data Addr Data

00000002 00000002 0000000200000001 00000001 0000000100000001 00000001 0000000100000008 00000008 00000008001312D0 001312D0 001312D00000007C 0000007C 0000007C00000000 00000000 0000000000000000 00000000 000000000000001E 0000001E 0000001E8000005C 8100005C 8000005C00000000 00000000 8100007C00000000 00000000 0000000000000000 00000000 0000000000000000 00000000 0000000000000000 00000000 0000000000000000 00000000 0000000000000000 00000000 0000000000000000 00000000 0000000000000000 00000000 0000000000000000 00000000 0000000000000000 00000000 0000000000000000 00000000 0000000000000000 00000000 0000000000014440 00014440 0001444000000001 00000001 00000001

500000050000045000008500000C500001050000145000018500001C500002050000245000028500002C500003050000345000038500003C500004050000445000048500004C500005050000545000058500005C50000605000064 00000005 000000055000068

00000005006C0070 006C0070 006C0070

500006C 00000000 00000000 000000005000070 23F123E0 32F132E0 23FA23E45000074 23F323F2 32F332F2 23F623F35000078 000023F4 000032F4 000023F7

000144400000000100000005008C00900000000032F332E432FA32F6000032F7

500007C500008050000845000088500008C500009050000945000098

Pin pointer

1 group with 5 pins and 1 lane in the interface

Lane pointer

Interface pointer

strobe_io = lane 0x23,pin 0data_io [ 0 ] = lane 0x23, pin 1data_io [ 1 ] = lane 0x23, pin 2data_io [ 2 ] = lane 0x23, pin 3data_io [ 3 ] = lane 0x23, pin 4

Number of groupGroup 0 – 5 pins, 1 lane

Interface pointer

PHY Lite for Parallel


PHY Lite for Parallel Interfaces IP core 1

Interfaces IP core 0



500000050000045000008500000C500001050000145000018500001C500002050000245000028500002C500003050000345000038500003C500004050000445000048500004C500005050000545000058500005C500006050000645000068500006C500007050000745000078

500000050000045000008500000C500001050000145000018500001C500002050000245000028500002C500003050000345000038500003C500004050000445000048500004C500005050000545000058500005C500006050000645000068500006C500007050000745000078

Important: There is no guarantee of the ordering of the interface parameter tables in the mergedtable. You must perform a search to locate a specific interface parameter.

For more information about the contents of the parameter table, refer to the AddressLookup topic.

Related Information

Address Lookup on page 51



There are two sets of control registers that store the reconfiguration feature settings:

• Control/Status registers (CSR) - you can only read the values of these registers.The values are set through the IP parameters. The CSR registers contain thedefault setting in the IP.

• Avalon Memory-Mapped registers - you can read and write to these registers usingAvalon interface. The time for the the PHY Lite for Parallel Interfaces delays tochange after writing a new value to the registers via the Avalon bus is dependenton the user's configuration. For example, it takes approximately 50 VCO clockcycles for the output delay to change value. Perform an RTL simulation to show anaccurate timing which correlates to the hardware operation.




55


3.2.5.3.1. PHY Lite for Parallel Interfaces Intel Stratix 10 FPGA IP Control RegistersAddresses

The following tables show the register bits to construct the control register addressesfor each feature.

Table 29. Control Register Address for Pin Output Delay Feature

Bit Description Avalon MM Register CSR Register

Value Access Type Value AccessType

[30:27] Specify the PHY Lite forParallel Interfaces IPinterface ID.

Depending on theInterface ID

parameter in theParameter Editor.

RW Depending on theInterface ID


RO

[26:24] Specify the Avaloncontroller calibration busbase address.

3'h3 RW 3'h3 RO

[23:21] Reserved 3'h0 RW 3'h0 RO

[20:13] Specify the lane addressof an interface. This valueis depending on theresource fitting processduring compilation.

You can query thisin the Parameter

Table LookupOperation Sequenceas described in the

Address Lookuptopic.

RW You can query thisin the Parameter



RO

[12:8] Specify the address forthe physical location of apin within a lane.



Address Lookuptopic or based on

your pin assignmentsetting in the .qsf

file.



Address Lookuptopic or based on

your pin assignmentsetting in the .qsf

file.

RO

[7:0] Reserved 8'hD0 RW 8'hE8 RO

Table 30. Address Register for Pin Input Delay Feature






RW N/A RO


3'h3 RW N/A RO

[23:21] Reserved 3'h0 RW N/A RO



Table LookupOperation Sequence

RW N/A RO

continued...




56




as described in theAddress Lookup

topic.

[12:9] Reserved 4'hC RW N/A RO

[8:7] Select DQ pin sets toaccess.

• 2'h1: DQ 0 toDQ 5

• 2'h2: DQ 6 toDQ11

RW N/A RO

[6:4] Select the specific DQ pinto access.

• 3'h0: DQ 0 andDQ 6




• 3'h4: DQ 4 andDQ 10

• 3'h5: DQ 5 andDQ 11

RW N/A RO


Table 31. Address Register for Strobe Input Delay Feature






RW N/A RO


3'h3 RW N/A RO






RW N/A RO

[12:0] Reserved 13'h18E0 RW N/A RO




57


Table 32. Address Register for Strobe Enable Phase Feature








RO


3'h3 RW 3'h3 RO









RO

[12:0] Reserved 13'h18F0 RW 13'h1998 RO

Table 33. Address Register for Strobe Enable Delay Feature








RO


3'h3 RW 3'h3 RO









RO

[12:0] Reserved 13'h1808 RW 13'h19A8 RO




58


Table 34. Address Register for Read Valid Delay Feature








RO


3'h3 RW 3'h3 RO









RO

[12:0] Reserved 13'h180C RW 13'h19A4 RO

Related Information


3.2.5.3.2. Control Registers Description

When you generate a read operation to the control registers addresses, the Avaloninterface returns a set of values from the control registers. The following tables showthe definition of the bits for each control register.

Table 35. Control Register Description


Pin Output Delay [31:13] Reserved (6)

[12:0] Phase valueStrobe minimum setting: Refer to the Output andStrobe Enable Minimum and Maximum PhaseSettings topic.Strobe maximum setting: Refer to the Output andStrobe Enable Minimum and Maximum PhaseSettings topic.Incremental Delay: 1/128th VCO clock periodThe CSR value for DQS is set through the OutputStrobe Phase parameter during IP instantiation.Note: The pin output delay switches from the CSR

register value to the Avalon register valueafter the first Avalon write. It is only reset tothe CSR register value on a reset of theinterface.

Pin Input Delay [31:13] Reserved (6)

continued...

(6) Reserved bit ranges must be zero




59



[12] Enable bit to select access to Avalon register or CSRregister.0 = Delay value is 0. CSR register is not available forthis feature.1 = Select delay value from Avalon register

[11:9] Reserved (6)

[8:0] Delay valueMinimum Setting: 0Maximum Setting: 511 VCO clock periodsIncremental Delay: 1/256th VCO clock period

Strobe Input Delay [31:13] Reserved (6)

[12] Enable bit to select access to Avalon register or CSRregister.0 = Delay value is 0. CSR register is not available forthis feature.1 = Select delay value from Avalon registerModifying these values must be done on all lanes in agroup.

[11:10] Reserved(6)

[9:0] Delay valueMinimum Setting: 0Maximum Setting: 1023 VCO clock periodsIncremental Delay: 1/256th VCO clock periodModifying these values must be done on all lanes in agroup.

Strobe Enable Phase [31:16] Reserved (6)

[15] Enable bit to select access to Avalon register or CSRregister.0 = Select delay value from CSR register. The CSRvalue is set through the Capture Strobe PhaseShift parameter during IP instantiation.1 = Select delay value from Avalon registerModifying these values must be done on all lanes in agroup.

[14:13] Reserved(6)

[12:0] Bit [12:0]: Phase valueMinimum Setting: Refer to the Output and StrobeEnable Minimum and Maximum Phase Settings topic.Maximum Setting: Refer to the Output and StrobeEnable Minimum and Maximum Phase Settings topic.Incremental Delay: 1/128th VCO clock periodModifying these values must be done on all lanes in agroup.

Strobe Enable Delay [31:16] Reserved(6)

[15] Enable bit to select access to Avalon register or CSRregister.0 = Select delay value from CSR register1 = Select delay value from Avalon registerModifying these values must be done on all lanes in agroup.

[14:6] Reserved(6)

continued...




60



[5:0] Delay valueMinimum Setting: 0 external clock cyclesMaximum Setting: 63 external memory clock cyclesIncremental Delay: 1 external memory clock cycleModifying these values must be done on all lanes in agroup.

Read Valid Delay [31:16] Reserved(6)


[14:7] Reserved


Important: For more information about performing various clocking and delay calculations,depending on the interface frequency and rate, refer to PHYLite_delay_calculations.xlsx.

Related Information

Output and Strobe Enable Minimum and Maximum Phase Settings on page 63

Example of Accessing Dynamic Reconfiguration Control Registers using Parameter Table

The example shows the steps to access Pin Output Delay CSR control register for astrobe pin with the following PHY Lite for Parallel Interfaces IP settings in Intel Stratix10 devices:

• Number of groups: 2. The group index is automatically set to 0x00.

• Interface ID: 0x00

• Pin width: 4

• Strobe configuration: Single ended

• Avalon controller calibration bus base address: 0x3000000

After the project compilation, the interface ID, lane address and pin addresses arestored in the parameter table.




61

http://www.intel.com/content/dam/altera-www/global/en_US/others/literature/ug/phylite_delay_calculations.xlsx


PHY Lite for Parallel Inter faces IP core 0Addr Data

00000002000000010000000100000008001312D00000007C00000000000000000000001E8000005C000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001444000000002

00000400800C01001401801C02002402802C03003403803C04004404804C05005405805C060064 00000505068 0070007406C 0071007e070 0000494b074 4bf64be4078 4bf74bf9

Pointer to Pin address

Lane number [7:6]: 00 (1 lane)Pins number [5:0]: 0101 (5 pins)

strobe_io = lane 0x4b, pin address: 4data_io = lane 0x4b, pin address: 6data_io = lane 0x4b, pin address: 9data_io = lane 0x4b, pin address: 7data_io = lane 0x4b, pin address: 2

PHY Lite Interface ID Pointer to interfaces

Number of groups:2

Lane address for group 0 = 0x4bLane address for group 1=0x49

Pointer to Lane address

49e44bf207C080 49f949f6

49f349f8084

strobe_io = lane 0x49, pin address: 4data_io = lane 0x49, pin address: 6data_io = lane 0x49, pin address: 9data_io = lane 0x49, pin address: 8data_io = lane 0x49, pin address: 3

The Pin Output Delay CSR control register has the following bit definition:

Bit Description Avalon MM Register Value

[30:27] Specify the PHY Lite for Parallel Interfaces IPinterface ID.

0x00 (Interface ID from parametertable)

[26:24] Specify the Avalon controller calibration bus baseaddress.

0x3

[23:21] Reserved 0x00

continued...




62


Bit Description Avalon MM Register Value

[20:13] Specify the lane address of an interface. This valueis depending on the resource fitting process duringcompilation.

0x4b (Lane address from parametertable)

[12:8] Specify the address for the physical location of a pinwithin a lane.

0x04 (Strobe pin address fromparameter table)

[7:0] Reserved 0xe8

To read the Pin Output Delay CSR control register for a strobe pin, use the command

avl_in_address[30:0] = interface id[30:27], calibration bus address[26:24], Reserved[23:21], lanes address[20:13], pin address[12:8], reserved[7:0]avl_in_address[30:0] = 0x00, 0x3, 0x00, 0x4B, 0x04, 0xE8

3.2.5.4. Calibration Guidelines

The PHY Lite for Parallel Interfaces Intel Stratix 10 FPGA IP allows you to dynamicallyreconfigure the features of the interface. However, performing calibration is anapplication specific process. This section provides some general guidelines forcalibrating Intel Stratix 10 I/O architecture.


The read pointer in the read FIFO buffer gets reset when reads are far apart (80 coreclock cycles). However, the data inside the FIFO is not cleared. Therefore, analternating pattern should be used to find the end to the strobe enable window toavoid reading stale data in the FIFO.

The strobe enable signal turns itself off on the last negative edge of the strobe.Therefore, while finding the enable window, use extra dummy pulses (either extendedstrobe or reads from memory without asserting the rdata_en signal) to clear thestrobe enable.


When dynamically reconfiguring the interpolator phase settings, the values must bekept within the ranges below to ensure proper operation of the circuitry.


VCOMultiplication

FactorCore Rate Minimum Interpolator Phase Maximum Interpolator

Phase

Output Bidirectional Bidirectional withOCT Enabled

1 Full 0x080 0x100 0x100 0xA80

Half 0x080 0x100 0x100 0xBC0

Quarter 0x080 0x100 0x100 0xA00

2 Full 0x080 0x100 0x180 0x1400

Half 0x080 0x100 0x180 0x1400

Quarter 0x080 0x100 0x180 0x1400

continued...




63


VCOMultiplication


Phase


4 Full 0x080 0x100 0x280 0x1FFF

Half 0x080 0x100 0x280 0x1FFF


8 Full 0x080 0x100 0x480 0x1FFF

Half 0x080 0x100 0x480 0x1FFF


For more information about performing various clocking and delay calculations,depending on the interface frequency and rate, refer to PHYLite_delay_calculations.xlsx.


You can instantiate the PHY Lite for Parallel Interfaces Intel Stratix 10 FPGA IP from IPCatalog in Intel Quartus Prime software. Intel provides an integrated parameter editorthat allows you to customize this IP to support a wide variety of applications.


Related Information





Table 37. PHY Lite for Parallel Interfaces Intel Stratix 10 FPGA IP Parameter Settings


Description

Parameter



Clocks


533.0 MHz External memory clock frequency.

continued...




64







Description

Note: To achieve timing closure at 534 MHzand above, use dynamic reconfigurationto calibrate the interface. Compile yourdesign with Intel Quartus Prime withaccurate board skew information for finaltiming analysis.



PLL reference clock frequency Dependent ondesired memoryclock frequency

133.25 MHz PLL reference clock frequency. You must feed aclock of this frequency to the PLL referenceclock input of the memory interface.Note: There is no minimum range, but the

maximum output frequency is 1600 MHz,limited by the clock network. Theminimum range for the ref_clk signalis 10 MHz but the maximum isdependent on the speed grade.



Clock rate of user logic Full, Half, Quarter Quarter Determines the clock frequency of user logic inrelation to the memory clock frequency. Forexample, if the memory clock sent from theFPGA to the memory device is toggling at 800MHz, a "Quarter rate" interface means that theuser logic in the FPGA runs at 200 MHz.

Specify additional outputclocks based on existing PLL

On, Off Off Exposes additional output clocks from theexisting PLL.

Output ClocksNote: These parameters are available only if the Specify additional output clocks based on existing PLL parameter

is turned on

Number of additional clocks 0 to 4 0 Specifies the number of additional clocks to beexposed.

outclk[4:0] (Reserved) — — PLL output clocks with the flag (Reserved) in theQSYS GUI are reserved for PHY Lite for ParallelInterfaces Intel Stratix 10 FPGA IP internalfunctionality.

Desired Frequency — 133.25 MHz Specifies the output clock frequency of thecorresponding output clock port, outclk[], inMHz. The minimum and maximum valuesdepend on the device used. The PLL only readsthe numerals in the first six decimal places.

Actual Frequency — 133.25 MHz Allows you to select the actual output clockfrequency from a list of achievable frequencies.

Phase shift units ps or degrees ps Specifies the phase shift unit for thecorresponding output clock port, outclk[], inpicoseconds (ps) or degrees.

Phase shift — 469.0 ps Specifies the requested value for the phaseshift. The default value is 0 ps.

continued...




65



Description

Actual phase shift — 469.0 ps Allows you to select the actual phase shift froma list of achievable phase shift values. Thedefault value is the closest achievable phaseshift to the desired phase shift.

Desired duty cycle 0.0–100.0 50.0 % Specifies the requested value for the duty cycle.

Actual duty cycle — 50.0 % Allows you to select the actual duty cycle from alist of achievable duty cycle values. The defaultvalue is the closest achievable duty cycle to thedesired duty cycle.


Use dynamic reconfiguration On, Off Off Exposes an Avalon memory-mapped interface,allowing you to control the configuration of thePHY Lite for Parallel Interfaces Intel Stratix 10FPGA IP settings.

First PHYLite Instance in theAvalon Chain

On, Off On Select this parameter if this IP instance is thefirst instance in the Avalon chain, connected tothe master.This parameter is only available when you selectUse dynamic reconfiguration .Important: Do not select this parameter if

there is an External MemoryInterface IP selected as the firstinstance in the chain, available inthe same column.

Interface ID — 0 The ID used to identify this interface in the I/Ocolumn over the Avalon memory-mapped bus.

I/O Settings

I/O standard SSTL-12SSTL-125SSTL-135SSTL-15

SSTL-15 Class ISSTL-15 Class IISSTL-18 Class ISSTL-18 Class II1.2-V-HSTL Class

I1.2-V-HSTL Class

II1.5-V-HSTL Class

I1.5-V-HSTL Class

II1.8-V-HSTL Class

I1.8-V-HSTL Class

II1.2-V POD

1.2-V1.5-V1.8-VNone

SSTL-15 ClassI

Specifies the I/O standard of the interface'sstrobe and data pins written to the .qip file ofthe IP instance. When you choose None, theI/O standard is unspecified in the generated IP.


Single-ended, Single-ended Specify the reference clock I/O configuration.

continued...




66



Description

LVDS with on-chip termination,LVDS without on-chip termination

General Settings

Fast simulation model On, Off Off Turn on this option to reduce PHY Lite forParallel Interfaces Intel Stratix 10 FPGA IPsimulation time.Note: This option is preliminarily supported in

Intel Quartus Prime v18.1.

Group <x> - these parameters are set on a per group basis

Group <x> Parameter Settings

Copy parameters from anothergroup

On, Off Off Select this option when you want to copy theparameter settings from another group.Set Number of groups to more than 1 toenable this option.

Group 1 - 17 1 Choose the group index that you want as theparameter settings source. The changes madeto the source is updated automatically to all thetarget groups.You can only choose the group index which theparameter settings are not copied from anothergroup.Set Number of groups to more than 1 toenable this option.

Group <x> Pin SettingsNote: These parameters are disabled when Copy parameters from another group is enabled.



Pin width 1 to 48 9 Number of pins in this data/strobe group.A data width up to 48 is achievable if no strobeis used in the group. The number of strobes iscontrolled by the Use output strobe, Strobeconfiguration and Use separate capturestrobe parameters.


Group <x> Input Path SettingsNote: These parameters are disabled when Copy parameters from another group is enabled.


cycles

7 Expected read latency of the external device inmemory clock cycles.For example, a design with an external clockfrequency of 533 MHz in half-rate has a validread latency range of 5 to 63 external interfaceclock cycles.Refer to the Read Latency topic for minimumread latency settings based on FPGA core clockrate.

Swap capture strobe polarity On, Off Off Internally swap the negative and positivecapture strobe input pins. This feature is onlyavailable for complementary strobeconfigurations.

continued...




67



Description



Group <x> Output Path SettingsNote: These parameters are disabled when Copy parameters from another group is enabled.

Write latency 0 to 3 (maximumvalue is

dependent on therate)

0 Additional delay added to the output data inmemory clock cycles.Refer to the Write Latency topic for write latencysettings based on FPGA core clock rate.

Use output strobe On, Off On Use an output strobe.



Group <x> General Data SettingsNote: These parameters are disabled when Copy parameters from another group is enabled.

Data configuration Single ended Single ended Selects the type of data. Single ended data typeuses one pin. Differential data type uses 2 pins.PHY Lite for Parallel Interfaces Intel Stratix 10FPGA IP does not support differential data pins.Refer to the I/O Standards topic for a list ofsupported I/O standards.


Strobe configuration Single ended,Differential,

Complementary

Single ended Select the type of strobe. A single ended strobeuses one pin, which reduces the maximumpossible number of data pins in the group to 47.Differential/complementary strobe types use 2pins, which reduces the maximum possiblenumber of data pins in the group to 46.Note: The differential strobe configuration uses

a differential input buffer, whichproduces a single clock for the captureDDIO and read FIFO. Thecomplementary strobe configurationuses two single-ended input buffers andclocks the data into the capture DDIOand read FIFO using both clocks (asrequired by protocols such as QDRII).The output path functionality is thesame.

Refer to the I/O Standards topic for a list ofsupported I/O standards.

Use separate strobes On, Off Off Separate the bidirectional strobe into input andoutput strobe pins. Use separate strobes is onlyavailable for a bidirectional data group with theoutput strobe enabled.

Group <x> OCT SettingsNote: These parameters are disabled when Copy parameters from another group is enabled.

OCT enable size 0 - 15 (IntelStratix 10devices)

1 Specifies the delay between the OCT enablesignal assertion and the dqs_enable signalassertion. You must set a value that is largeenough to ensure that the OCT is turn on beforesampling input data.

continued...




68



Description

Expose termination ports On, Off Off Turn on to expose the series and paralleltermination ports to connect separate OCTblock.To enable this option, turn off Use Default OCTValues parameter and select a value for InputOCT Value or Output OCT Value parameters.

Use Default OCT Values — Use default OCT values based on the I/Ostandard parameter setting.

Input OCT Value No termination,<n> ohm with

calibration

Notermination

Specifies the group's data and strobe inputtermination values to be written to the .qip ofthe IP instance. The list of legal values isdependent on the I/O standard parametersetting. Refer to the I/O Standards topic.This option is available when the Use DefaultOCT Values option is disabled.

Output OCT Value No termination,<n> ohm with

calibration, <n>with no

calibration

Notermination

Specifies the group's data and strobe inputtermination values to be written to the .qip ofthe IP instance. The list of legal values isdependent on the I/O standard parametersetting. Refer to the I/O Standards topicsupported termination values.This option is available when the Use DefaultOCT Values option is disabled.

Group <x> Timing SettingsNote: These parameters are disabled when Copy parameters from another group is enabled.

Generate Input DelayConstraints for this group

On, Off On Instructs SDC to generate set_input_delayconstraints for this group.

Input Strobe Setup DelayConstraint

Constraint in ns 0.03 ns Specifies the group's input setup delayconstraint against the input strobe.

Input Strobe Hold DelayConstraint

Constraint in ns 0.03 ns Specifies the group's input hold delay constraintagainst the input strobe.

Inter Symbol Interference ofthe Read Channel

Constraint in ns 0.09 ns Specifies the Inter Symbol Interference valuefor DQS signal of read channel.Specify a positive value to decrease the setupand hold slack by half of the entered value.

Generate Output DelayConstraints for this group

On, Off On Instructs SDC to generate set_output_delayconstraints for this group.

Output Strobe Setup DelayConstraint

Constraint in ns 0.03 ns Specifies the group's output setup delayconstraint against the input strobe.

Output Strobe Hold DelayConstraint

Constraint in ns 0.03 ns Specifies the group's output hold delayconstraint against the input strobe.

Inter Symbol Interference ofthe Write Channel

Constraint in ns 0.09 ns Specifies the Inter Symbol Interference valuefor DQS signal of write channel.Specify a positive value to decrease the setupand hold slack by half of the entered value.

Group <x> Dynamic Reconfiguration Timing SettingsNote: These parameters are disabled when Copy parameters from another group is enabled.

Dynamic Reconfiguration ReadDeskew Algorithm

DQ Per-BitDeskew, DQ

Group Deskew,Custom Deskew

DQ Per-BitDeskew

Specifies the Read Deskew algorithm for TimingAnalyzer to use when performing I/O timinganalysis:

continued...




69



Description

• DQ Per-Bit Deskew: Each DQ pin is adjustedindependently to minimize the skew withinthe DQ bits. DQS signal is adjusted to center-align to the de-skewed DQ bus. Each DQ bitmay have different delay chain settings.

• DQ Group Deskew: DQS signal is adjustedcenter-align to the DQ bus without de-skewing individual DQ bits. All DQ bits withinthe same group has same delay chainsettings.

• Custom Deskew: DQS is aligned based onthe recoverable setup and hold slack youdefined.

You must select Use dynamic reconfigurationoption to enable this parameter.

Setup Slack Recoverable ofCustom Read Deskew

Algorithm

Constraint in ns 0.0 ns Specifies the amount of positive setup slackavailable based on your custom read deskewalgorithm.This parameter is available with the conditions:• Use dynamic reconfiguration is turn on• Pin type is set to Input or Bidirectional

and• Dynamic Reconfiguration Read Deskew

Algorithm is set to Custom Deskew

Hold Slack Recoverable ofCustom Read Deskew

Algorithm

Constraint in ns 0.0 ns Specifies the amount of positive hold slackavailable based on your custom read deskewalgorithm.This parameter is available with the conditions:• Use dynamic reconfiguration is turn on• Pin type is set to Input or Bidirectional



Dynamic ReconfigurationWrite Deskew Algorithm



DQ Per-BitDeskew

Specifies the Write Deskew algorithm for TimingAnalyzer to use when performing I/O timinganalysis:• DQ Per-Bit Deskew: DQS signal is centered to

each individual DQ bits. Each DQ bit mayhave different delay chain settings.

• DQ Group Deskew: DQS signal is centered tothe DQ bus group. All DQ bits within thesame group has same delay chain settings.



Setup Slack Recoverable ofCustom Write Deskew

Algorithm

Constraint in ns 0.0 ns Specifies the amount of positive setup slackavailable based on your custom write deskewalgorithm.This parameter is available with the conditions:

continued...




70



Description

• Use dynamic reconfiguration is turn on• Pin type is set to Output or Bidirectional

and• Dynamic Reconfiguration Write Deskew


Hold Slack Recoverable ofCustom Write Deskew

Algorithm

Constraint in ns 0.0 ns Specifies the amount of positive hold slackavailable based on your custom write deskewalgorithm.This parameter is available with the conditions:• Use dynamic reconfiguration is turn on• Pin type is set to Output or Bidirectional



Related Information

• Read Latency on page 71For more information about the IP read latency values.

• Write Latency on page 72For more information about the IP write latency values.

• I/O Standards on page 76For more information about the supported I/O standards in Intel Agilexdevices.


Table 38. Minimum Read LatencyThis table shows the minimum read latency value supported by PHY Lite for Parallel Interfaces based on thecore clock rate and VCO multiplier factor settings.


Full rate 1 4

2 4

4 3

8 3

Half rate 1 5

2 5

4 4

8 4

Quarter rate 1 7

2 7

4 7

8 7




71



Table 39. Maximum Write LatencyThis shows the maximum write latency value supported by PHY Lite for Parallel Interfaces IP based on the coreclock rate and VCO multiplier factor settings.


Full rate 1 0

2 0

4 0

8 0

Half rate 1 1

2 1

4 1

8 1

Quarter rate 1 3

2 3

4 3

8 2

3.3.2. Signals




ref_clk Input 1 Reference clock for the PLL. The reference clock must besynchronous with strobe_in to ensure the dqs_enable signalis in-sync with strobe_in.

reset_n Input 1 Resets the interface. This signal is asynchronous.

interface_locked Output 1 Interface locked signal from PHY Lite for Parallel Interfaces IntelStratix 10 FPGA IP to core logic. This signal indicates that the PLLand PHY circuitry are locked.Data transfer should starts after the assertion of this signal.

core_clk_out Output 1 Use this core clock in the core-to-periphery transfer of soft logicdata and control signals.The core_clk_out frequency depends on the interfacefrequency and clock rate of user logic parameter.

pll_extra_clock[0..3] Output 4 These are the additional output clock signals generated by PHYLite for Parallel Interfaces Intel Stratix 10 FPGA IP when youenable Specify additional output clocks based on existingPLL parameter.

pll_locked Output 1 This is the locked signal for the additional output clocks generatedby the IP.




72



Table 41. Output Path SignalsOutput path signals are signals that are available when you set the Pin Type parameter to either Output orBidirectional. The <n> in the signal names below represents the group number in the IP.


group_<n>_oe_from_core

Input Quarter-rate: 4 x PIN_WIDTHHalf-rate: 2 x PIN_WIDTHFull-rate: 1 x PIN_WIDTH

Output enable signal from core logic.Synchronous to the core_clk_outoutput from the IP.

group_<n>_data_from_core

Input

Quarter rate-DDR: 8 x PIN_WIDTHHalf-rate DDR: 4 x PIN_WIDTHFull-rate DDR: 2 x PIN_WIDTHQuarter-rate SDR: 4 x PIN_WIDTHHalf-rate SDR: 2 x PIN_WIDTHFull-rate SDR: 1 x PIN_WIDTH

Data signal from core logic.Synchronous to the core_clk_outoutput from the IP.

group_<n>_strobe_out_in

Input Quarter-rate: 8Half-rate: 4Full-rate: 2

Strobe signal from core logic.Synchronous to the core_clk_outoutput from the IP.Note: This path is always DDR.

group_<n>_strobe_out_en


Strobe output enable from core logic.Synchronous to the core_clk_outoutput from the IP.

group_<n>_data_out/group_<n>_data_io


1 to 48 if data configuration is SingleEnded

Data output from PHY Lite for ParallelInterfaces Intel Stratix 10 FPGA IP.Synchronous to thegroup_<n>_strobe_out orgroup_<n>_strobe_io output fromthe IP.If the Pin Type parameter is set toOutput, the group_<n>_data_outsignals are used. If the Pin Typeparameter is set to Bidirectional,the group_<n>_data_io signals areused.Note: PHY Lite for Parallel Interfaces

Intel Stratix 10 FPGA IP doesnot support differential datapins.

group_<n>_strobe_out /group_<n>_strobe_io


1 Positive output strobe fromPHY Litefor Parallel Interfaces Intel Stratix 10FPGA IP. If the Pin Type is set toOutput, thegroup_<n>_strobe_out signal isused. If the Pin Type is set toBidirectional thegroup_<n>_strobe_io signal isused. The Use Separate Strobesparameter forces the use of thegroup_<n>_strobe_out signal witha Bidirectional Pin Type.

group_<n>_strobe_out_n /group_<n>_strobe_io_n


1 Negative output strobe from PHY Litefor Parallel Interfaces Intel Stratix 10FPGA IP.This is used if the StrobeConfiguration is set to Differentialor Complementary.

continued...




73



If the Pin Type is set to Output, thegroup_<n>_strobe_out_n signal isused. If the Pin Type is set toBidirectional, thegroup_<n>_strobe_io_n signal isused. The Use Separate Strobesparameter forces the use of thegroup_<n>_strobe_out_n signalwith a Bidirectional Pin Type.


Table 42. Input Path SignalsInput path signals are signals that are available when you set the Pin Type parameter to Input orBidirectional. The <n> in the signal names below represents the group number in the IP.


group_<n>_data_to_core

Output Quarter-rate DDR: 8 x PIN_WIDTHHalf-rate DDR: 4 x PIN_WIDTHFull-rate DDR: 2 x PIN_WIDTH

Quarter-rate SDR: 4 x PIN_WIDTHHalf-rate SDR: 2 x PIN_WIDTHFull-rate SDR: 1 x PIN_WIDTH

Output data to the core logic. Validon rdata_valid. Synchronous tothe core_clk output from the PHY

Lite for Parallel Interfaces IntelStratix 10 FPGA IP.

group_<n>_rdata_en


This signal represents the number ofexpected words to read from the

external device.This signal is set to high after a readcommand is issued. Synchronous tothe core_clk output from the PHY

Lite for Parallel Interfaces IntelStratix 10 FPGA IP.

When using the IP as a receiver,assert this signal after

interface_locked signal isasserted and strobe_in is stable.


Output Quarter-rate: 4Half-rate: 2Full-rate: 1

This signal determines which data arevalid when reading from Read FIFO.


clock cycles.Synchronous to the core_clk

output from the PHY Lite for ParallelInterfaces Intel Stratix 10 FPGA IP.

group_<n>_data_in/

group_<n>_data_io

Input/Bidirectional


Input and output data from/toexternal device. Synchronous to the

group_<n>_strobe_in orgroup_<n>_strobe_io input. Thefirst data_in must be associated with

positive edge of strobe_in/strobe_io.

If the pin type is set to Input, thedata_in ports are used. If the pintype is set to bidirectional, the

data_io ports are used.

continued...




74



Note: PHY Lite for Parallel InterfacesIntel Stratix 10 FPGA IP doesnot support differential data

pins.

group_<n>_strobe_in/

group_<n>_strobe_io

Input/Bidirectional

1 Input and output strobe from/toexternal device. If the pin type is set

to Input, thegroup_<n>_strobe_in signal is

used. If the pin type is set toBidirectional, the

group_<n>_strobe_io signal isused.

group_<n>_strobe_in_n


Input/Bidirectional


Configuration parameter is set toDifferential or Complementary. If

the pin type is set to Input, thestrobe_in_n signal is used. If thepin type is set to Bidirectional, the

strobe_io_n signal is used.

3.3.2.4. Avalon Configuration Bus Interface Signals

The PHY Lite for Parallel Interfaces Intel Stratix 10 FPGA IP exposes the Avalonmemory-mapped-MM slave and Avalon memory-mapped master interfaces when youperform dynamic reconfiguration. Connect the Avalon memory-mapped slave to eithera master in the core or the master interface of either an PHY Lite for ParallelInterfaces Intel Stratix 10 FPGA IP or the External Memory Interface IP to be placed inthe same column. You can only connect the master interface to the slave interface of aPHY Lite for Parallel Interfaces Intel Stratix 10 FPGA IP or External Memory InterfaceIP to be placed in the same column.

Table 43. Avalon Memory-Mapped Master Interface Signals


avl_clk Input 1 Avalon interface clock.Maximum Avalon memory-mapped interface clock for PHYLite for Parallel Interfaces Intel Stratix 10 FPGA IP is 167

MHz.

avl_reset_n Input 1 Reset input synchronous to avl_clk.

avl_read Input 1 Read request from io_aux. This signal is synchronous to theavl_clk input.

avl_write Input 1 Write request from io_aux. This signal is synchronous to theavl_clk input.

avl_byteenable Input 4 Controls which bytes should be written on avl_writedata.

avl_address Input 31 Address from io_aux. This signal is synchronous to theavl_clk input.

avl_readdata Output 32 Read data to io_aux. This signal is synchronous to theavl_clk input.

continued...




75



avl_writedata Input 32 Write data from io_aux. This signal is synchronous to theavl_clk input.

avl_readdata_valid Output 1 Indicates that read data has returned.

avl_waitrequest Output 1 Stalls upstream logic when it is asserted.

Table 44. Avalon Memory-Mapped Slave Interface Signals


avl_out_clk Output 1 Connect this signal to the input Avalon interface of anotherPHY Lite for Parallel Interfaces Intel Stratix 10 FPGA IP or the

External Memory Interfaces IP.

avl_out_reset_n Output 1 Connect this signal to the input Avalon interface of anotherPHY Lite for Parallel Interfaces Intel Stratix 10 FPGA IP or the

External Memory Interfaces IP.

avl_out_read Output 1 Indicates read transaction.

avl_out_write Output 1 Indicates write transaction.

avl_out_byteenable Output 4 Controls which bytes should be written onavl_out_writedata.

avl_out_writedata Output 32 The data packet associated with the write transaction.

avl_out_address Output 31 Avalon address (in byte granularity). Value is identical toavl_address but with zeroes padded on the LSBs.

avl_out_readdata Input 32 The data packet associated withavl_out_readdata_valid.

avl_out_readdata_valid

Input 1 Indicates that read data has returned.

avl_out_waitrequest Input 1 Stalls upstream logic when it is asserted.

3.3.2.5. Termination Signals

Table 45. Termination SignalsThe termination signals are signals that are available when you enable the Expose termination portsparameter. The <n> in the signal names below represents the group number in the IP.


group_<n>_seriesterminationcontrol

Input 16 Connect this signal to the seriestermination control signal of the OCTIntel FPGA IP to receive seriestermination code to calibrate Rs.

group_<n>_parallelterminationcontrol

Input 16

Connect this signal to the paralleltermination control signal of the OCTIntel FPGA IP to receive paralleltermination code to calibrate Rt.

3.4. I/O Standards

The PHY Lite for Parallel Interfaces Intel Stratix 10 FPGA IP allows you to set I/Ostandards on the pins associated with the generated configuration. The I/O standardcontrols the available strobe configurations and OCT settings for all groups.




76


Table 46. I/O Standards and Termination Values

I/O Standard Valid InputTerminations (Ω)

Valid OutputTerminations

(Ω)

RZQ(Ω)

Differential/Complementary I/OSupport

Important: PHY Lite for Parallel Interfaces IntelStratix 10 FPGA IP does not support

differential data pins.

SSTL-12 60, 120 40, 60,240 240 Yes

SSTL-125 40, 60, 120 34, 40 240 Yes

SSTL-135 40, 60, 120 34, 40 240 Yes

SSTL-15 40, 60, 120 34, 40 240 Yes

SSTL-15 Class I 50 50 100 Yes

SSTL-15 Class II 50 25 100 Yes

SSTL-18 Class I 50 50 100 Yes

SSTL-18 Class II 50 25 100 Yes

1.2-V HSTL Class I 50 50 100 Yes

1.2-V HSTL Class II 50 25 100 Yes





1.2-V POD 34, 40, 48, 60, 80,120, 240

34, 40, 48,60

240 Yes

1.2-V — — — No

1.5-V — — — No

1.8-V — — — No

Related Information

On-Chip I/O Termination in Intel Stratix 10 Devices




Note: The VREF settings are at the lane level, so all pins using a lane must have the sameVREF settings (including GPIOs).




77






CALIBRATED Use internal VREF generated using VREF codes from the Avalon memory-mapped reconfigurationbus.







Figure 37. VREF

Input Buffer

+

-Vref

R

R

VCCIO

Internal VREF




+

-

VCCIO

Rt

External VREF

Resistor Ladder




78


3.4.1.1. Calibrated VREF Settings

Table 48. Calibrated VREF SettingsThis table lists the calibrated VREF settings that you can set over the Avalon memory-mapped calibration bus.This table is applicable to all Intel FPGA devices.

avl_writedata[5:0] % of VCCIO

000000 60.00%

000001 60.64%

000010 61.28%

000011 61.92%

000100 62.56%

000101 63.20%

000110 63.84%

000111 64.48%

001000 65.12%

001001 65.76%

001010 66.40%

001011 67.04%

001100 67.68%

001101 68.32%

001110 68.96%

001111 69.60%

010000 70.24%

010001 70.88%

010010 71.52%

010011 72.16%

010100 72.80%

010101 73.44%

010110 74.08%

010111 74.72%

011000 75.36%

011001 76.00%

011010 76.64%

011011 77.28%

011100 77.92%

011101 78.56%

011110 79.20%

011111 79.84%

continued...




79



100000 80.48%

100001 81.12%

100010 81.76%

100011 82.40%

100100 83.04%

100101 83.68%

100110 84.32%

100111 84.96%

101000 85.60%

101001 86.24%

101010 86.88%

101011 87.52%

101100 88.16%

101101 88.80%

101110 89.44%

101111 90.08%

110000 90.72%

110001 91.36%

110010 92.00%

110011 -> 111111 Reserved

Related Information

Dynamic Reconfiguration on page 49


PHY Lite for Parallel Interfaces Intel Stratix 10 FPGA IP provides valid OCT settings foreach group (refer to the I/O Standards topic). These settings are written to the .qip ofthe instance during generation. If you select an I/O standard that supports OCT in theGeneral tab, you can use the OCT blocks provided in Intel Stratix 10 devices.




Related Information

• I/O Standards on page 76

• KDB link: How can the PHYLite IP RZQ pin location be assigned?





80

https://www.altera.com/support/support-resources/knowledge-base/emif/2017/how-do-i-place-the-phylite-ip-rzq-pin-at-a-user-chosen-pin-locat.html


The RZQ_GROUP assignment creates the OCT Intel FPGA IP without modifying the RTL.The Fitter searches for the rzq pin name in the netlist. If the pin does not exist, theFitter creates the pin name along with the OCT Intel FPGA IP and its correspondingconnections. This allows you to create a group of pins to be calibrated by an existingor non-existing OCT and the Fitter ensures the legality of the design. You mustassociate the terminated pins of the PHY Lite for Parallel Interfaces Intel Stratix 10FPGA IP instance with an RZQ pin at the system level manually.

Use the following steps to set RZQ pin locations for the PHY Lite for Parallel InterfacesIntel Stratix 10 FPGA IP:

1. In the Group <x> OCT Settings tab, disable Use Default OCT Values andExpose termination ports.

Figure 38. Group <x> OCT Settings Parameter Settings






set_instance_assignment -name RZQ_GROUP <rzq_pin_name> -to <altera_phylite_strobe_pin>

set_instance_assignment -name RZQ_GROUP <rzq_pin_name> -to <altera_phylite_data_pin[*]>




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3.4.2.2. Manual Insertion of OCT Block

You may also instantiate the OCT Intel FPGA IP separately in your project and connectthe termination ports to the PHY Lite for Parallel Interfaces Intel Stratix 10 FPGA IP.

1. Expose the PHY Lite for Parallel Interfaces Intel Stratix 10 FPGA IP terminationports by disable Use Default OCT Values.

2. Select the available OCT values in the Input OCT Value parameter. This displaysthe Expose termination ports parameter.

Note: For supported input and output OCT values, refer to the I/O Standardstopic.

3. Select Expose termination ports to expose the termination ports in the IP.

4. Connect the termination ports to a OCT Intel FPGA IP either in power-up or usermode.

Figure 39. RTL View of PHY Lite for Parallel Interfaces Intel Stratix 10 FPGA IPInterfacing with OCT Intel FPGA IP in User Mode

group_0_data_in[3:0]

cal_requestrefclk

rstnoctrzqin0

group_0_strobe_in

calibration_requestclockresetrzqin

oct_test_ip

group_0_data_in[3:0]group_0_parallelterminationcontrol[15:0]

4’h0group_0_rdata_en[3:0]group_0_seriesterminationcontrol[15:0]

phylite_test_ip

group_0_strobe_in32’h0group_1_data_from_core[31:0]

16’h0group_1_oe_from_core[15:0]group_1_parallelterminationcontrol[15:0]

group_1_seriesterminationcontrol[15:0]4’h0group_1_strobe_out_en[3:0]8’h0group_1_strobe_out_en[7:0]

ref_clkreset_n

group_1_data_out[3:0]group_1_strobe_outinterface_locked

oct_0_parallel_termination_control[15:0]

oct_0_series_termination_control[15:0]

u1

u0

Related Information

I/O Standards on page 76



Follow these guidelines to place the PHY Lite for Parallel Interfaces Intel Stratix 10FPGA IP group pins.




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1. All groups in a PHY Lite for Parallel Interfaces Intel Stratix 10 FPGA IP must beplaced across a contiguous set of lanes. The number of lanes depends on thenumber of pins used by the group.

2. Two groups, from either the same or different PHY Lite for Parallel Interfaces IntelStratix 10 FPGA IP, cannot share an I/O lane.

3. For PHY Lite for Parallel Interfaces Intel Stratix 10 FPGA IP instance that spansmore than one I/O bank, all groups in the interface must be placed across acontiguous set of banks within an I/O column. The number of I/O banks requireddepends on the memory interface width.

4. Pins that are not used in an I/O bank are available as general purpose I/O (GPIO)pins.

5. To constrain groups from separate PHY Lite for Parallel Interfaces Intel Stratix 10FPGA IP instances into the same I/O bank, the instances must share the samereference clock and reset sources, the same external memory frequencies, andthe same voltage settings.

6. A reference clock network can only span across maximum of 6 I/O banks.

7. You cannot share the OCT termination block across the I/O column. You canassociate the terminated pins of the PHY Lite for Parallel Interfaces Intel Stratix 10FPGA IP instance with an RZQ pin through RZQ_GROUP assignment.

Table 49. Group Pin PlacementPHY Lite for Parallel Interfaces Intel Stratix 10 FPGA IP does not support DQS for X4.

Number of Pins in Group Valid DQS Group in a Bank Valid Index in a Bank

1-12 DQS for X8/X9 0-11/12-23/24-35/36-47

13-24 DQS for X16/X18 0-23/24-47

25-48 DQS for X32/X36 0-47

Related Information

Pin-Out Files for Intel FPGA DevicesFor pin index and I/O bank references, refer to the specific device pin-out file.


You are recommended to source the reference clock to the PHY Lite for ParallelInterfaces IP from a dedicated clock pin. Use the clock pin in one of the I/O banksused by the PHY Lite for Parallel Interfaces IP. You must use contiguous I/O banks toimplement multiple interfaces (consisting of a combination of External MemoryInterface and PHY Lite for Parallel Interfaces IPs). If you use the same reference clockfor these interfaces, place the reference clock in any of the contiguous I/O banks.

Note: For Intel Quartus Prime software version 18.1 or later, you may see error warningmessage for design with encrypted IOPLL IP. The auto-generated .sdc files of theIOPLL IP are not supported if you use encryption. You must manually create the .sdcfile using create_clock and create_generated_clock to replace the auto-generated .sdc file in the design for refclk and output clocks.

Related Information

Intel Stratix 10 Clocking and PLL User Guide: IP Core Constraints




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https://www.intel.com/content/www/us/en/programmable/documentation/mcn1440569668630.html#cim1476370979096


3.5.3. Reset

You can source the reset to the PHY Lite for Parallel Interfaces Intel Stratix 10 FPGA IPfrom an external pin or from the core. If you source the reset from an external pin,you must configure the I/O standard of the reset signal in the .qsf file with thefollowing command:

set_location_asignment <PIN_NUMBER> -to <signal_name>

Related Information

• Functional Description on page 40

• KDB Link: Error(14566): The Fitter cannot place 1 periphery component(s) due toconflicts with existing constraints (1 PHYLITE_GROUP(s)).

3.5.4. Constraining Multiple PHY Lite for Parallel Interfaces to One I/OBank

You can instantiate multiple PHY Lite for Parallel Interfaces Intel FPGA IPs within anI/O column. To constrain groups from separate PHY Lite for Parallel Interfaces IPinstances into the same I/O bank, the instances must share the same reference clockand reset sources, the same external memory frequencies and the same voltagesettings.


If you are using the dynamic reconfiguration feature, all interfaces of the ExternalMemory Interfaces and PHY Lite for Parallel Interfaces Intel Stratix 10 FPGA IPs in thesame I/O column must share the reset signal. Multiple IPs requiring Avalon coreaccess require daisy chain connectivity.

Related Information

Daisy Chain on page 50

3.5.6. Timing

The Intel Quartus Prime software generates the required timing constraints to analyzethe timing of the PHY Lite for Parallel Interfaces IP on the all Intel FPGA devices.

3.5.6.1. Timing Components

Table 50. Timing Components

Circuit Category Timing Paths Source Destination Description

Source synchronousand optionallycalibrated (7)

Read Path MemoryDevice

DQ CaptureRegister

Source synchronous timing paths—paths whereclock and data signals are passed from thetransmitting devices to the receiving devices.Optionally calibrated paths—paths with delayelements that are dynamically reconfigurable toachieve timing closure, especially at higherfrequency, and to maximize the timing margins.


Write Path FPGADQ/DQS

MemoryDevice

continued...

(7) Can be optionally calibrated by using dynamic reconfiguration.




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You can calibrate these paths by implementingan algorithm and turning on the optionaldynamic reconfiguration feature. An example ofthe calibrated path is the FPGA to memorydevice write path, in which you can dynamicallyreconfigure the delay elements to, for instance,compensate the skew due to process voltagetemperature variation.

Internal FPGA Core to PHYLite forParallel

Interfaces IPPath

CoreRegisters

Write FIFO The internal FPGA paths are paths in the FPGAfabric. The Timing Analyzer reports thecorresponding timing margins.

Internal FPGA PHY Lite forParallel

Interfaces IPto Core

Read FIFO Core Registers

3.5.6.2. Timing Constraints and Files

To successfully constrain the timing for PHY Lite for Parallel Interfaces IP, the IPgenerates a set of timing files. You can locate these timing files in the<variation_name> directory:

• <variation_name> .sdc

• <variation_name> _ip_parameters.tcl

• <variation_name> _pin_map.tcl

• <variation_name>_parameters.tcl

• <variation_name>_report_timing.tcl

• <variation_name>_report_timing_core.tcl

3.5.6.2.1. <variation_name>.sdc

You can find the location of the <variation_name>.sdc file in the .qip or .qsys,which is generated during the IP generation. The <variation_name> .sdc allows theFitter to optimize timing margins with timing driven compilation and allows the TimingAnalyzer to analyze the timing of your design.

The IP uses <variation_name>.sdc for the following operations:

• Creating clocks on PLL inputs

• Creating generated clocks

• Calling derive_clock_uncertainty

• Creating set_output_delay and set_input_delay constraints to analyze thetiming of the read and write paths

3.5.6.2.2. <variation_name>_parameter.tcl

The <variation_name>_parameters.tcl file is a script that lists the following PHYLite for Parallel Interfaces IP parameters used in the .sdc file and report timingscripts:




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• Jitter

• Simultaneous switching noise

• Calibration uncertainties

3.5.6.2.3. <variation_name>_ip_parameters.tcl

The <variation_name>_ip_parameters.tcl file lists the PHY Lite for ParallelInterfaces IP parameters and is read by the <variation_name>.sdc.

3.5.6.2.4. <variation_name>_pin_map.tcl

The <variation_name>_pin_map.tcl is a TCL library of functions and proceduresthat <variation_name>.sdc uses.

3.5.6.2.5. <variation_name>_report_timing.tcl

The <variation_name>_report_timing.tcl file is a script that contains timinganalysis flow and reports the timing slack for your variation. This script runsautomatically during calibration (during static timing analysis) by sourcing thefollowing files:

• <variation_name>_ip_parameters.tcl


• <variation_name>_pin_map.tcl


You can also run <variation_name>_report_timing.tcl with the Report DDRfunction in the Timing Analyzer. This script runs for every instance of the samevariation.

Note: You can only use the Report DDR function if you enable the dynamic reconfigurationfeature.

3.5.6.2.6. <variation_name>_report_timing_core.tcl

The <variation_name>_report_timing_core.tcl file is a script that<variation_name>_report_timing.tcl uses to calculate the timing slack foryour variation. <variation_name>_report_timing_core.tcl runs automaticallyduring compilation.

3.5.6.3. Timing Analysis

Table 51. Timing AnalysisThis table lists the timing analysis performed in the I/O and FPGA for the PHY Lite for Parallel Interfaces IP.

Location Description

I/O The PHY Lite for Parallel Interfaces IP generation creates the appropriate generated clock settings for theread strobe on the read path and the write strobe of the write path, according to their strobe type(singled-ended, complementary, or differential) and their interface type (SDR or DDR) in the followingformat:

continued...




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• Clock name for read strobe—<pin_name>_IN.• Clock name for the write path—<pin_name> for positive strobe.• Clock name for the write path—<pin_name>_neg for negative strobe.The set_false_path, set_input_delay and set_output_delay constraints are also generated toensure proper timing analysis of the PHY Lite for Parallel Interfaces IP.

FPGA The PHY Lite for Parallel Interfaces IP generation creates the clock settings for the user core clock and theperiphery clock in the following formats:• user core clock—<variation_name>_usr_clk

• periphery clock— <variation_name>_phy_clk*The user core clock is for user core logic and the periphery clock is the clock for the PHY Lite for ParallelInterfaces IP periphery hardware. With these clock settings, the Timing Analyzer analyzes the timing ofthis IP interface transfer and within core transfer correctly.

3.5.6.4. Timing Closure Guidelines

3.5.6.4.1. Timing Closure: Dynamic Reconfiguration

You can dynamically reconfigure the delay elements in the I/O to optimize process,voltage, temperature variations by implementing a calibration algorithm that modifiesthe input and output delays.

Related Information


3.5.6.4.2. Timing Closure: Input Strobe Setup and Hold Delay Constraints

The Input Strobe Setup Delay Constraint and Input Strobe Hold DelayConstraint parameters ensure that an input to the FPGA from the an external devicemeets the internal FPGA setup and hold time requirements. The value of theseconstraints are calculated from various timing parameters such as setup and holdtiming of the external device, board trace delay and clock skew.

The following figure shows the considerations required to determine the Input StrobeSetup Delay Constraint and Input Strobe Hold Delay Constraint values. Theexternal device sends data and clock to the FPGA through interconnect on the board.The FPGA uses the clock signal from the external device to latch input data to theFPGA. The maximum and minimum values of the output clock TCO are values availablein the external device data sheet.

Figure 40. Input Strobe Setup and Hold Delay Constraints Considerations

External Device

Data

ClockPLL

PHY Litefor Parallel Interface

Intel FPGA IP

FPGA

tCO

Data input to FPGA

data_trace (max/min)

Input clock to FPGA

clock_trace (max/min)

Input clock




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The following is the derivation for Input Strobe Setup Delay Constraint and InputStrobe Hold Delay Constraint:

Input strobe setup delay constraint = Maximum board skew + maximum TCO

Input strobe hold delay constraint = Minimum board skew + minimum TCO

where maximum board skew = maximum data trace - minimum clock trace

minimum board skew = minimum data trace - maximum clock trace

maximum TCO = DQS to DQ skew (tDQSQ)

minimum TCO = Data hold skew (tQHS)

Figure 41. Input Data Cycle Timing Diagram

DQ_skew_maxDQ_skew_min

tCL

tCH

DQ_skew_min DQ_skew_max

tDQSQ

t QHtQHS

Data valid window

tCL = Clock cycle low

tCH = Clock cycle hightDQSQ = DQS-DQ skew

t QH = DQ-DQS holdtQHS = Data hold skew

The following is an example of Input Strobe Setup Delay Constraint and InputStrobe Hold Delay Constraint calculations with:

• Input clock frequency = 100 MHz

• Board skew estimation = ± 0.03 ns

• Maximum TCO = 0.6 ns

• Minimum TCO = -0.6 ns

Input Strobe Setup Delay Constraint = 0.03 + 0.6= 0.63 ns

Input Strobe Hold Delay Constraint = -0.03 + (-0.6) = -0.63 ns

Insert these values into the Input Strobe Setup Delay Constraint and InputStrobe Hold Delay Constraint parameters and run timing analysis with the TimingAnalyzer tool. The following is an example of delay result from the Timing Analyzertool.




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Figure 42. Example of Input Strobe Delay Value from Timing Analyzer

iEXT=Input Strobe Delay Constraint + (0.5*Inter Symbol Interference of Read Channel)

3.5.6.4.3. Timing Closure: Output Strobe Setup and Hold Delay Constraints

The Output Strobe Setup Delay Constraint and Output Strobe Hold DelayConstraint ensure that the data output from the FPGA to the external device meetsthe setup and hold requirements of the external device. The value of these constraintsare calculated from various timing parameters such as setup and hold timing of theexternal device, board trace delay and clock skew.

The following figure shows the considerations required to determine the OutputStrobe Setup Delay Constraint and Output Strobe Hold Delay Constraintvalues. These constraints are depending on the clock and data traces, and setup andhold requirements of the external device. With system-centric delays, you can obtainthe setup and hold requirements, clock delay, and data trace delay values for theexternal device through the device data sheet.

Figure 43. Output Strobe Setup and Hold Delay Constraints Considerations

Data

ClockPLL

PHY Lite for Parallel Interface Intel FPGA IP

FPGA

Data output to external device


Output clock to external device


Input clock

External Device

Data

Clock

(tSU ,tH)

The following is the derivation for Output Strobe Setup Delay Constraint andOutput Strobe Hold Delay Constraint:

Output strobe setup delay constraint = Maximum board skew + maximum tSU

Output strobe hold delay constraint = Minimum board skew + minimum tH



maximum tSU = clock setup time




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minimum tH = clock hold time

Figure 44. DDR Output Cycle Timing Diagram

Hold marginSU margin

tSUdq

tSUdq

DQ bit time

The following is an example of Output Strobe Setup Delay Constraint and OutputStrobe Hold Delay Constraint calculations with:



• Maximum tSU = 0.75 ns

• Minimum tH = 0.75 ns

Output Strobe Setup Delay Constraint = 0.03 + 0.75= 0.78 ns

Output Strobe Hold Delay Constraint = -0.03 - 0.75 = -0.78 ns

Insert these values into the Output Strobe Setup Delay Constraint and OutputStrobe Hold Delay Constraint parameters and run timing analysis with the TimingAnalyzer tool. The following is an example of delay result from the Timing Analyzertool.

Figure 45. Example of Output Strobe Delay Value from Timing Analyzer

oEXT= Output Strobe Setup delay constraint + (0.5 * Inter Symbol Interference of the Write Channel)




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3.5.6.4.4. Timing Closure: Non Edge-Aligned Input Data

If the input data is not edge-aligned, use the following equation to calculate the newInput Strobe Setup Delay Constraint and Input Strobe Hold Delay Constraintvalues:

New Input Strobe Setup Delay Constraint Value = Clock to data skew - InputStrobe Phase Shift (nanosecond)

New Input Strobe Hold Delay Constraint Value = Clock to data skew + InputStrobe Phase Shift (nanosecond)

For example, if the memory speed is 800 MHz and the clock to data skew value is 0.1with input data phase shift of 90°:

New Input Strobe Setup Delay Constraint value = 0.1-1.25*(90/360) =-0.2125ns.

New Input Strobe Hold Delay Constraint value = 0.1 + 1.25*(90/360) = 0.4125ns

Important: Ensure that you make the changes in the Input Strobe Setup Delay Constraint andInput Strobe Hold Delay Constraint parameters.

3.5.6.4.5. I/O Timing Violation

It can be difficult to achieve timing closure for I/O paths at high frequency. Use thedynamic reconfiguration feature to calibrate the I/O path.

Related Information


3.5.6.4.6. Internal FPGA Path Timing Violation

If timing violations are reported at the internal FPGA paths (such as<instance_name>_usr_clk or <instance_name>_phy_clk_*), consider thefollowing guidelines:

If setup time violation is reported, lower the clock rate of the user logic from full-rateto half-rate, or from half-rate to quarter-rate. This reduces the frequency requirementof the IP core-to-core data transfer.

If hold time violation is observed, you may increase hold uncertainty value to equal orhigher than the violation amount in the .sdc file. This will provide a more stringentconstraint during design fitting. Following is an example to increase the holduncertainty.

If $::quartus(nameofexecutable) != “quartus_sta”

set_clock_uncertainty -from [<instance_name>_phy_clk_*] -to [<instance_name>_phy_clk_*] -hold 0.3 -add

set_clock_uncertainty -from [<instance_name>_usr_clk] -to [<instance_name>_usr_clk] -hold 0.3 -add

However, increasing the hold uncertainty value may cause setup timing violation atslow corner.




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3.6. Design Example

The PHY Lite for Parallel Interfaces IP is able to generate a design example thatmatches the same configuration chosen for the IP. The design example is a simpledesign that does not target any specific application; however you can use the designexample as a reference on how to instantiate the IP and what behavior to expect in asimulation.





There are two variants of design example available for PHY Lite for Parallel InterfacesIP:

• Variant without dynamic reconfiguration design example

• Variant with dynamic reconfiguration design example

Table 52. PHY Lite for Parallel Interfaces IP Design Example Variants

Design Example Variant Design Files Description

Dynamic Reconfiguration OFF ed_synth.qsys (synthesisonly)

Consists of configurablePHY Lite forParallel Interfaces IP instance.

ed_sim.qsys (simulationonly)

Consists of sim_ctrl, agent, addr/cmdand PHY Lite for Parallel Interfaces IPinstances.Perform read and write transactionverification.

ON ed_sim.qsys (simulationonly)

Consists of sim_ctrl, agent, addr/cmd, cfg_ctrl, avl_ctrl and PHY Litefor Parallel Interfaces IP instances.This design example demonstratesdynamic reconfiguration and usesFSM to perform calibration.


When the Enable dynamic reconfiguration option is not selected, Intel QuartusPrime software generates a design example of PHY Lite for Parallel Interfaces IPwithout a dynamic reconfiguration module.

This design example consists of simulation and synthesis design files.

3.6.1.1.1. Generate the Hardware Design Example

The make_qii_design.tcl generates a synthesizable hardware design examplealong with a Quartus project, ready for compilation.




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This script generates a qii directory containing a project called ed_synth.qpf. Youcan open and compile this project with the Intel Quartus Prime software.


The make_sim_design.tcl generates a simulation design example along with tool-specific scripts to compile and elaborate the necessary files.





This script generates a sim directory containing one subdirectory for each supportedsimulation tools. Each subdirectory contains the specific scripts to run simulation withthe corresponding tool.

The simulation design example provides a generic example of the core and I/Oconnectivity for your IP configuration. Functionally, the simulation iterates over eachgroup in your configured IP and performs basic reads/writes to an associated agent(one per group) in the testbench. A simple one group PHY Lite for Parallel InterfacesIP instantiation in the testbench is used for basic address and command outputs to theagent. A side bus between the sim_ctrl and the agents is used to check that thereads and writes are valid.

Figure 46. High-Level View of the Simulation Design Example with One GroupSide read/write command

Side read/write data

DRAM clockWrite commandRead commandAgent select

data

strobedata

sim_ctrl

DRAM clock

Latency Delays

DRAM clockCore clock

PHY Lite DUT

PHY Lite ADDR/CMD


Read/Write command

Core clockRead/Write

enable


Agent (one per group in DUT)




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When you select the Use dynamic reconfiguration option and click GenerateExample Design, Intel Quartus Prime software generates the dynamicreconfiguration with configuration control module design examples:

3.6.1.2.1. Dynamic Reconfiguration Using Finite State Machine

This design example is a simulation design example that is capable to performdynamic calibration for PHY Lite for Parallel Interfaces Intel Stratix 10 FPGA IP.

Features

• Perform dynamic reconfiguration using Avalon controller

• Read and write transactions monitoring

• Delay values monitoring

Software Requirements

• Intel Quartus Prime software

• Active-HDL, ModelSim* - Intel FPGA Edition, NCsim or VCS Simulator

Functional Description

This design example introduces the cfg_ctrl and avl_ctrl blocks, which work withthe sim_ctrl module to demonstrate the basic functionality of the PHY Lite forParallel Interfaces Intel Stratix 10 FPGA IP Avalon memory-mapped basedreconfiguration. The agent is also modified to insert delays on the data and clocks,which the new modules will compensate for.

NOTE: The cfg_ctrl module performs a simplistic reconfiguration of the interfacethat stops at the first working delay values. The design example only supportsimulation. A robust calibration algorithm should sweep over the entire valid range ofdelays to choose the correct value for the application.




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Figure 47. Dynamic Reconfiguration Using Finite State Machine Design ExampleThis figure shows a high-level view of the simulation design example with one group.

Side read/write command


DRAM clock

Write commandRead commandAgent select

strobeData

sim_ctrl

DRAM clock

Latency Delays


PHY Lite DUT

PHY Lite ADDR/CMD


Read/Write command

Core clock

Read/Write enable



cfg_ctrl avl_ctrlAvalon Memoy-mapped

Bus

Dynamic Reconfiguration Only

Reconfiguration Flow Control

Avalon Memory-mapped Bus

ref_clk_gen reset_gen

ref_clk

ref_clk

reset_n

reset_n

ref_clk

Driver

Strobe

Core clock

Lock

DataLock

Data

Table 53. Design Components Description


ref_clk_gen Generates clock to reset_gen, PHY Lite for Parallel Interfaces Intel Stratix 10FPGA IP ADDR/CMD (ref_clk), and PHY Lite for Parallel Interfaces Intel Stratix 10FPGA IP (ref_clk) blocks.

reset_gen Generates reset to PHY Lite for Parallel Interfaces ADDR/CMD and PHY Lite forParallel Interfaces Intel Stratix 10 FPGA IP blocks.

sim_ctrl • Generates read/write commands to PHY Lite for Parallel Interfaces ADDR/CMDblock.

• Generates side read/write commands and data to Agent block.• Generates strobe and data to Driver block.

Driver Generates strobe and data for each group and to PHY Lite for ParallelInterfaces_Intel Stratix 10 FPGA IP block.

PHY Lite for Parallel InterfacesADDR/CMD

Passing read/write commands and command clock from sim_ctrl to Agent.

Agent FIFO to store data from PHY Lite for Parallel Interfaces DUT and side read/writedata from sim_ctrl block.

cfg_ctrl This is configuration control block which performs read and write delay calibrationbefore test begin.The calibration results is passed to the PHY Lite for Parallel Interfaces IntelStratix 10 FPGA IP through Avalon Controller.Contains 4 FSMs:1. Main FSM – cfg_ctrl state2. Write Strobe FSM – Calibration state for Output Strobe3. Read Strobe FSM – Calibration state for Input Strobe4. Read Enable FSM – Calibration state for Strobe Enable and Input Data

avl_ctrl The Avalon controller is used to perform address translation to store delaysettings from the calibration done by cfg_ctrl block.




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Figure 48. Design Example Functional Flow

a)

b)

c)

d)

Start

Dynamically reconfigure data group's settings

Function name: reconfigure_grp

Reset cfg_ctrl module

Dynamically reconfigure write strobe settingFunction name: reconfigure_grp_write

Repeat step b) and c) until pass

Function name: reconfigure_grp_readDynamically reconfigure read strobe setting

Write data to DUT and read back to verify data is correct

Pin Type?

e) Done

a)

b)c)

d)



Repeat step b) and c) until passe) Done

Simulation ends

Simulation ends

Read from Pin Output Delay CSR registerWrite to DUT and read back

If fail, update Pin Output Delay Avalon register

Read from Strobe PVT Compensated Input Delay CSR register

a)

b)c)d) Repeat step b) and c) until passe) Done

Read from Pin Output Delay CSR registerWrite to DUT and read backIf fail, update Pin Output Delay Avalon register

Write to Agent and read backIf fail, update Strobe PVT Compensated Input Delay Avalon register

Write data to Agent and read back to verify data is correct

Output InputBidirectional

Dynamically reconfigure read enable and input data settings

a)b)

e) Get number of data pinf) Write to Agent and read back

g) If fail, update Pin PVT Compensated Input Delay Avalon register

h) Repeat f) and g) until passi) Done

c) If data[0] is mismatched, update Strobe Enable Phase Avalon register

Function name: reconfigure_grp_read_en_and_dataRead from Strobe Enable Phase CSR registerWrite to Agent and read back

d) Repeat step b) and c) until data[0] is matched




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Generate the Dynamic Reconfiguration with Configuration Control Module Design Example

1. In Intel Quartus Prime software, instantiate PHY Lite for Parallel Interfaces IP core.

2. Customize parameter settings per your requirement and turn on the Usedynamic reconfiguration option.

3. Click Generate Example Design. Specify a directory name to generate thedesign example.

4. To generate Verilog or mixed-language simulation files, go to the design exampledirectory and run the following script in Nios II Command Shell.


5. To generate VHDL simulation files, go to the design example directory and run thefollowing script in Nios II Command Shell.


Run the Dynamic Reconfiguration with Configuration Control Design Example

Follow these steps to compile and simulate the design:

1. Change the working directory to <Example Design>\sim\ed_sim\sim\<Simulator>.

2. Run the simulation script for the simulator of your choice. Refer to the table below.

Simulator Working Directory Steps

Modelsim <Example Design>\sim\ed_sim\sim\mentor

a. do msim_setup.tcl

b. ld_debug

c. Add desired signals into thewaveform window.

d. run -all

VCS <Example Design>\sim\ed_sim\sim\synopsys\vcs

a. sh vcs_setup.sh

VCSMX <Example Design>\sim\ed_sim\sim\synopsys\vcsmx

a. sh vcsmx_setup.sh

NCSim <Example Design>\sim\ed_sim\sim\cadence

a. sh ncsim_setup.sh

Aldec Example Design\sim\ed_sim\sim\aldec

a. do rivierapro_setup.tcl

b. ld_debug


d. run -all




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Figure 49. Sample of Simulation Output




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4. PHY Lite for Parallel Interfaces Intel Arria 10 and IntelCyclone 10 GX FPGA IPs







Table 54. PHY Lite for Parallel Interfaces Intel Arria 10 FPGA IP Release Information

Item Description

IP Version 19.3.0



Table 55. PHY Lite for Parallel Interfaces Intel Cyclone 10 GX FPGA IP ReleaseInformation

Item Description

IP Version 19.1



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The PHY Lite for Parallel Interfaces IP utilizes the I/O subsystem in the Intel Arria 10and Intel Cyclone 10 GX devices. The I/O subsystem is located in the I/O columns ofeach Intel FPGA devices. For Intel Arria 10 and Intel Cyclone 10 GX devices, eachcolumn consists of I/O banks and I/O aux. The number of I/O banks varies accordingto device packages. Each bank is a group of 48 I/O pins, organized into four I/O laneswith 12 pins for each lane. Each I/O lane contains the DDR-PHY input and output pathlogic for 12 I/Os as well as a DQS logic block. All four lanes in a bank can be combinedto form a single data/strobe group or up to four groups in the same interface. Undercertain conditions, two groups from different interfaces can also be supported in thesame bank.

Figure 50. Intel Arria 10 I/O Bank Structure

2L

2K

2J

2I

2H

2G

2F

2A

3H

3G

3F

3E

3D

3C

3B

3A

Trans

ceive

r Bloc

k

Trans

ceive

r Bloc

k

TransceiverBlock

I/OColumn

BankControl

I/OColumn

IndividualI/O Banks



I/O Lane



I/O Lane

I/O Center

I/O PLL Hard Memory Controllerand

PHY Sequencer

I/O DLL I/O CLK

OCT VR



I/O Lane



I/O Lane

4. PHY Lite for Parallel Interfaces Intel Arria 10 and Intel Cyclone 10 GX FPGA IPs



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Figure 51. Intel Cyclone 10 GX I/O Bank Structure

2L

2K

2J

2A

3A

3B

Trans

ceive

r Bloc

k

3 V I/O

LVDS I/O



I/O Lane



I/O Lane

I/O Center

I/O PLL Hard Memory Controllerand

PHY Sequencer

I/O DLL I/O CLK

OCT VR



I/O Lane



I/O Lane

Related Information


• I/O Resources in Intel Arria 10 DevicesFor more information about Intel Arria 10 I/O bank architecture

• I/O Resources in Intel Cyclone 10 GX DevicesFor more information about Intel Cyclone 10 GX I/O bank architecture

• Constraining Multiple PHY Lite for Parallel Interfaces to One I/O Bank on page 145

4.2.1. Top Level Interfaces

The PHY Lite for Parallel Interfaces IP consists of the following ports:




• Avalon memory-mapped configuration bus (available only when DynamicReconfiguration feature is enabled)




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Figure 52. Top-Level InterfaceThis figure shows the top-level diagram of the PHY Lite for Parallel Interfaces IP interface.

PLLI/O Lane

I/O Lane

Tile Control

I/O Lane


phy_clkphy_clk_phs

core_clk_out



Group

ref_clk



Legend




Intel FPGA Device


Related Information

• Output Path on page 105For more information about the output path

• Input Path on page 107For more information about the input path

• Signals on page 131For more information about core data, control, and I/O interfaces signals




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4.2.2. Clocks

The PHY Lite for Parallel Interfaces IP uses a reference clock that is sourced from adedicated clock pin to the PLL inside the IP. This PLL provides four clock domains forthe output and input paths.

Table 56. PHY Lite for Parallel Interfaces IP Clock Domains






Table 57. PHY Lite for Parallel Interfaces Intel Arria 10 FPGA IP Supported InterfaceFrequencyUse the Timing Analyzer to perform timing closure to ensure your design fulfilled all timing constraints with thesupported frequencies indicated in the table. Full, half, and quarter core clock rate refers to the ratio of thecore clock and interface clock. For example, an interface clock frequency of 800 MHz has full core clock rate of800 MHz, half core clock rate of 400 MHz, and quarter core clock rate of 200 MHz.

Core ClockRate



Full 100 333 100 266 100 233

Half 100 667 100 533 100 466

Quarter 100 1200 100 1067 100 933

Table 58. PHY Lite for Parallel Interfaces Intel Cyclone 10 GX FPGA IP SupportedInterface FrequencyUse the Timing Analyzer to perform timing closure to ensure your design fulfilled all timing constraints with thesupported frequencies indicated in the table. Full, half, and quarter core clock rate refers to the ratio of thecore clock and interface clock. For example, an interface clock frequency of 800 MHz has full core clock rate of800 MHz, half core clock rate of 400 MHz, and quarter core clock rate of 200 MHz.

Core Clock Rate Speed Grade –5 (MHz) Speed Grade –6 (MHz)

Min Max Min Max

Full 100 266 100 233

Half 100 533 100 466

Quarter 100 1067 100 933

Related Information

KDB link: Can the Intel® Arria® 10 and Intel Cyclone® 10 GX I/O PLL have a VCOfrequency below the minimum value shown in the device datasheets?

4.2.2.1. Clock Frequency Relationships

The following equations describe the relationships between the clock domainsavailable in the PHY Lite for Parallel Interfaces IP core.




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Related Information

KDB link: Can the Intel® Arria® 10 and Intel Cyclone® 10 GX I/O PLL have a VCOfrequency below the minimum value shown in the device datasheets?





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4.2.3. Output Path



Block Description


Interpolator Works with the FIFO block to generate the desired output delay. You can dynamically configurethe delay through the Avalon memory-mapped interface. For more information, refer toDynamic Reconfiguration section.

Figure 53. Output PathThis figure shows the output path for the PHY Lite for Parallel Interfaces IP.

Write FIFO data_io/data_out

Interpolator

interpolator_clk

data_from_coreoe_from_core

phy_clk

VCO clock

strobe_out_instrobe_out_en strobe_out/strobe_io

PHY Lite for Parallel Interfaces IP CoreTo external interfaceFrom Intel FPGA core

Data path


(1)

(1)

(1)

(2)


Legend

(1)

The following figures show the waveform diagrams for the output path. The delaysshown in the waveforms are just estimation based on simulations and these values aredifferent with different core clock rate and VCO multiplier.




105





• User logic clock rate: Quarter rateIntrinsic Delay Write Latency = 0


OUTPUT_STROBE_PHASE = 90Signals from core logic to external memory device





Intrinsic Delay Write Latency = 2


Number of clock cycles set in Write latency parameter in Parameter Editor


OUTPUT_STROBE_PHASE = 90

Related Information

• Output Path Signals on page 132For more information about output path signals


• How to Estimate Arria 10/Stratix 10 PHY Lite Input and Output Path LatencyHow-to video on estimating PHY Lite Input and Output Path Latency in IntelArria 10 and Intel Stratix 10 devices.




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4.2.3.1. Output Path Data Alignment

The data_from_core and oe_from_core signals are arranged in time slices, whichare broken down into the individual pins in the group. The first time slice is on theLSBs of the buses, which matches the Intel FPGA PHY interface (AFI) bus ordering ofthe External Memory Interfaces IP.





Related Information


• External Memory Interface Handbook Volume 3: Reference Material (AFI 3.0Specification)

4.2.4. Input Path



Path Description

Data Path Receives data from external device to the FPGA core logic.The data path consists of a PVT compensated delay chain, a DDIO and a read FIFO.• PVT compensated delay chain—Allows per-bit deskew. You can only control the PVT compensated

delay chain over Avalon memory-mapped interface. For more information, refer to DynamicReconfiguration.

• DDIO and read FIFO—Responsible for deserialization with a factor of up to 8 (in DDR quarter-rate).The transfer between the DDIO and the read FIFO is a zero-cycle transfer.

Signals used in this path are:• group_data_in (input)—Input data from external device.• group_data_io (bidirectional)—Input and output data from/to external device.• group_data_to_core (output)—Output data to the core logic.• phy_clk—This is an internal clock signal that provides clock to the blocks used in this path.The IP supports SDR input by sending data on single clock cycle from the external device.



example, center aligning edge-aligned inputs).Signals used in this path are:

continued...




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Path Description

• group_strobe_in, group_strobe_in_n (input)—Input strobe from external device.group_strobe_in_n is used when strobe configuration is set to Differential.

• group_strobe_io, group_strobe_io_n (bidirectional)—Input and output strobe from/to externaldevice. strobe_io_n is used when strobe configuration is set to Differential.

• dqs_clean(output)—This internal signal is the refined version of group_strobe_in signal.• dqs (input)—This internal signal is an input strobe to DDIO and Read FIFO in the data path, after




the read enable on the Read FIFO, and one for the strobe enable. These delays are calculated atgeneration time based on the read latency that you provide. Individual control is not necessary, but ifyou are modifying these delays you can do so individually using dynamic reconfiguration.

• DQS_EN FIFO and interpolator—Used for the strobe enable delay, the DQS_EN FIFO and interpolatorare identical to the Write FIFO and interpolator circuitry in the output path. The DQS_EN FIFO andinterpolator are configured to match the output delay for a group with no additional output delay(Write latency = 0). During dynamic reconfiguration, the DQS_EN FIFO and interpolator can be usedfor fine grained control of the strobe enable signal. Both of these delays are controlled by the Readlatency parameter for the group.

Signals used in this path are:• rdata_valid(output)—This signal determines which data are valid when reading from Read FIFO.

This signal is delayed by the Read latency value set in the parameter editor.• group_rdata_en (input)—This signal represents the number of expected words to read from the

external device.• dqs_enable_in (input)—This is an internal signal that provides dqs delay value to the

pstamble_reg module to process a refined dqs signal.• dqs_enable_out (output)— This is an internal strobe with the delayed value specified by the

dqs_enable_in signal.• phy_clk—This is an internal clock for VFIFO and Read FIFO modules.• phy_clk_phs—This is an internal clock for the interpolator.• interpolator_clk—This is an internal clock for DQS_EN FIFO module.




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data_to_core data_in

phy_clk

strobe_in

dqs

Delay Chain (PVT)


DQS_EN FIFO

Interpolator

interpolator_clk

dqs_enable_out

phy_clk_phs

VFIFO

read_enable

dqs_enable_inrdata_en

phy_clk

rdata_valid

data_io

strobe_iostrobe_in_n

6

1 2

34

5 56

n n = sequence number. This represent read operationsequence.

To Intel FPGA core PHY Lite for Parallel Interfaces IP Core To external interface

Data path

Strobe path


Control signal

data_in_n

data_io_n

strobe_io_n

Legend:

Internal signals

(1)

(1)

(1)

(1)

(1)

(1)

(1)(1)

(1)

(1)

(2)



(3)



Operation







The following figures show the waveform diagrams for the input path. The delaysshown in the waveforms are just estimation based on simulations and these values aredifferent with different core clock rate and VCO multiplier.




109


Figure 58. Input Path Read Latency 7This simulation is based on the following PHY Lite for Parallel Interfaces IP configurations:




Intrinsic Delay Read Latency =7 PHY Lite for Parallel Interfaces Internal Delay

CAPTURE_PHASE_SHIFT = 90

Debug signals are inside the lane wrapper. Only available for waveform debugging.


Measured from rdata_en assertionto mem_rd assertion, sampling on the rising edge of mem_clk.

Number of clock cycles set through Read latency parameter in Parameter Editor

Latency between read data received to rdata_valid assertion.

Related Information

• Input Path Signals on page 133For more information about input path signals

• How to Estimate Arria 10/Stratix 10 PHY Lite Input and Output Path LatencyHow-to video on estimating PHY Lite Input and Output Path Latency in IntelArria 10 and Intel Stratix 10 devices.

4.2.4.1. Input Path Data Alignment

The bus ordering of data_to_core, rdata_en, and rdata_valid is identical to theordering of the output path. That is, the LSBs of the bus hold the first time slice ofdata received.

The rdata_valid delay is always set by the IP to match the rdata_en alignment.For example, quarter-rate delays are multiples of four external memory clock cycles(one quarter rate clock cycle).

Figure 59. Example Input (Quarter Rate DDR) - AlignedThe waveform shows an example of aligned reads on the input path of the PHY Lite for Parallel Interfaces IP. Atthe first rising edge of the core_clk_out signal, the group_0_rdata_en bus shows data of 4'hf, whichrepresents all incoming data are aligned. The group_0_rdata_valid bus shows the data of 4'hf, whichrepresents all incoming data are valid. Therefore, the incoming read data on the group_0_data_to_core busmatches the data seen on the group_0_data_io bus.




110



Reading from an unaligned memory address is called unaligned reads. Unalignedreads will result in unaligned rdata_valid and data_to_core with data andvalid signals packed to the LSBs. This request causes the IP to do two or more readoperations.

Figure 60. Example Input (Quarter Rate DDR) - UnalignedThe waveform shows an example of unaligned reads on the input path of the PHY Lite for Parallel Interfaces IP.

The data from an unaligned read operation comes in two phases. At the first rising edge of the core_clk_outsignal, the group_0_rdata_en bus shows value of 4'he, which shows there are 6 bytes of incoming data fromgroup_0_data_io bus. On the subsequent clock cycle, the group_0_rdata_en bus shows value of 4'h1,which shows there are 2 bytes of incoming data from group_0_data_io bus.

The valid data are transfer to the IP through the group_0_data_to_core bus. At first rising edge of thecore_clk_out signal, group_0_rdata_valid bus shows a value of 4'h7, which represents the first 6 bytesof the data from the group_0_data_to_core bus are valid and the last 2 bytes are invalid. On thesubsequent clock cycle, group_0_rdata_valid bus shows the value of 4'h1, which shows the last 2 bytes ofthe data from the group_0_data_to_core bus are valid.


Because of the asynchronous nature of the PHY, you must perform calibration toachieve timing closure at a high frequency. At a high level, calibration involvesreconfiguring input and output delays in the PHY to align data and strobes. With thePHY Lite for Parallel Interfaces IP, you can perform the calibration by using dynamicreconfiguration feature. The dynamic reconfiguration feature allows you to modifythese delays by writing to a set of control registers using an Avalon memory-mappedinterface.

Related Information

• Calibrated VREF Settings on page 139

• Timing Closure: Dynamic Reconfiguration on page 148

• KDB link: Why is the read data value incorrect for the DQS input delay when usingthe Dynamic Reconfiguration mode in the Intel® Arria® 10 PHYLite IP?

4.2.5.1. RTL Connectivity

The PHY Lite for Parallel Interfaces IP exposes the Avalon memory-mapped masterand Avalon memory-mapped slave interfaces when you enable the dynamicreconfiguration feature. If the generated IP is the only PHY Lite for Parallel InterfacesIP (with dynamic reconfiguration) or External Memory Interface IP in the I/O column,connect only the Avalon memory-mapped slave interface with a master in the core.Otherwise, connect Avalon memory-mapped master and slave interfaces as describedin the following section.

4.2.5.1.1. Daisy Chain

The I/O column provides a single physical Avalon memory-mapped interface. All IP inthe I/O column that require Avalon memory-mapped interface access the samephysical Avalon memory-mapped interface. The system-level RTL for the columnreflects this resource limitation by using a daisy chain to connect all dynamicallyreconfigurable IPs in an I/O column.




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For PHY Lite for Parallel Interfaces Intel Arria 10 FPGA IP and PHY Lite for ParallelInterfaces Intel Cyclone 10 GX FPGA IPs, the Avalon memory-mapped address is 28bits where the top 4-bits are the ID of the interface to be addressed in the daisychain. These bits are only required for the daisy chain arbitration in RTL simulation, sothey are not synthesized during compilation. If only one interface is addressed fromthe IP, it is sufficient to connect these bits as the interface’s ID.

Figure 61. Logical RTL View to Physical Column PlacementThis figure shows an example of a daisy chain consisting of the External Memory Interface and PHY Lite forParallel Interfaces IP before and after placement.

Notice that all core controllers must go through the arbitration logic that you createdin the FPGA core logic to connect to an interface on the daisy chain. The end of thedaisy chain should have its master output interface tied to 0.

Note: The Fitter rearranges the Avalon address pins during compilation, therefore use thepostfit netlist for proper simulation of the merged I/O column instead of prefit netlist.

4.2.5.2. Address Lookup

If you do not set the pin locations in the .qsf file, the lane addresses and pinplacement to an interface changes every time you compile your design in IntelQuartus Prime software. However, the PHY Lite for Parallel Interfaces IP is alwaysgenerated as if the IP is the only IP in a column, with lane addresses starting from 0.You need to determine the lane and pin addresses in order to dynamically reconfigurethe calibration settings in the IP core.




112


Figure 62. Lane and Pin Placement Dependent AddressesThis figure shows two examples of a placed group with two lanes, 16 data pins and a differential strobe.

Lane Address 0

Lane Address 1


strobe_iostrobe_io_ndata_io[0]data_io[1]data_io[2]data_io[3]data_io[4]data_io[5]data_io[6]data_io[7]data_io[8]data_io[9]

data_io[10]data_io[11]data_io[12]data_io[13]data_io[14]data_io[15]

Example 1

Lane Address 8

Lane Address 9


strobe_iostrobe_io_n

data_io[0]

data_io[1]

data_io[2]

data_io[3]

data_io[4]

data_io[5]

data_io[6]

data_io[7]

data_io[8]

data_io[9]


data_io[12]


data_io[15]

Example 2

To provide a unified way to look up reconfigurable feature addresses for a specificinterface both before and after placement, the address information is stored inmemory in the I/O column. This memory is addressable over the same Avalonmemory-mapped interface used for feature reconfiguration.

You can cache lookups 1 to 4 (8-bytes of information) to have pin and lanetranslations in one look-up.

Table 62. Memory Lookup ComponentsThis table lists the two main components of the memory lookup.


Global parameter table Stores pointers to the individual interface parameter tables. The global parameter tablelists all interfaces in the column (both the External Memory Interfaces and PHY Lite forParallel Interfaces IP).

Set of individual interfaceparameter tables

Contain interface specific information. This is where pin-level and lane-level address look-ups are performed.




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Figure 63. Memory Overview in Intel Arria 10 and Intel Cyclone 10 GX Devices

Group 0 Pin 1 Group 0 Pin 0

num_lanes[1:0],num_pins[5:0]

Needed for pin address lookups

Needed for simplifying strobe feature logic address lookups

One per Interface

num_lanes[1:0] starts counting at 0. For example, 0 = 1 lane, 1 = 2 lanes, 2 = 3 lanes, 3 = 4 lanes

Lane address table information: Group X Lane Y = lane_addr[7:0]

Pin address table information: Group X Pin Y = lane_addr[7:0],0xF,pin[3:0] for data and lane_addr[7:0],0xE,pin[3:0] for strobe

B

C

D

D

C

B

Number of Groups

Number of Groups

id[3:0],24’h00E000 + pt_ptr

id[3:0],24’h00E000 + pt_ptr 28’d4

Parameter Table (PHY Lite Specific)

id[3:0],24’h00E000 + pt_ptr +22’d0,num_grps[7:2],2’b00 + 28 d8

lane_ptr[15:0],pin_ptr[15:0]

id[3:0],24’h00E000 + lane_ptr

Lane Address Table (PHY Lite Specific)

Group 0 Lane 0

id[3:0],24’h00E000 + pin_ptr

Pin Address Table(PHY Lite Specific)

32-bits (4 Byte Addresses)

id[3:0],24’h00E000

Global Parameter Table(One per column, same as EMIF)

id[3:0],24'00E018 4’b1000,id[3:0], pt_ptr[23:0]

PT_VER[15:0],IP_VER[15:0]Number of Groups

4'h8,id[3:0],8'h00,interface_table_ptr[15:0]A

The MSB of the interface pointer entry in the global parameter table is 1 for PHY Lite interfaces.

A

1

2

3

4

5

6

Below are the steps to determine the lane and pin addresses from the lookup tables(the sequence corresponds to the sequence in the preceding figure. ):

Table 63. Parameter Table Lookup Operation SequenceThe base address for PHY Lite for Parallel Interfaces Intel Arria 10 and PHY Lite for Parallel Interfaces IntelCyclone 10 GX FPGA IP are 24'h00E000.

Legend inMemory

Overview inIntel Arria 10

and IntelCyclone 10 GX

Devices

Description

1 Search for Interface Parameter Table in Global Parameter Table (cache once per interface)• id3:0],24'h00E000 + 28'h18 to id3:0],24'h00E0000 + 28'h2C

• 1 to 11 look-ups

2 Retrieve number of groups in the interface (cache once per interface)• id[3:0],24'h00E000 + 4'h0,pt_ptr[23:0] + 4'h4

• You can skip this sequence if the number of groups is saved in the core during compilation (forexample, hard coded in RTL logic)

3 Retrieve group information (cache once per group)• id[3:0],24'h00E000 + 4'h0,pt_ptr[23:0] + 24'h4 + grp_num

• Not always necessary

continued...




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Legend inMemory

Overview inIntel Arria 10

and IntelCyclone 10 GX

Devices

Description

4 Retrieve Lane/Pin Address Offsets for group (cache once per group)• id[3:0],24'h00E000 + pt_ptr + 22'd0,num_grps[7:2],2'b00 + 28'd8

5 Perform lane/pin address translation (cache once per pin)• id[3:0],24'h00E000 + 12'h000,lane_ptr[15:0] + lane_num

• id[3:0],24'h00E000 + 12'h000,pin_ptr[15:0] + 17'h0,pin_num[5:0], 1'b0

6 Read/Write Avalon Calibration Bus• id[3:0],24'h800000 + read_from_step_4 + intra_lane_addr

4.2.5.2.1. Strobes

The first pins listed in the pin address lookup table are the strobes. They are alsoidentified by bits[7:4] = 0xE. For separate strobes, the input strobe pin placementalways take precedence. For differential and complementary strobes, the positive pinis the lower index.

Note: You can modify the output phase of differential strobes by writing to either the positiveor negative pin. Only one write is necessary. This is also the case for output-onlycomplementary strobes.

4.2.5.2.2. Parameter Table Example

These figures show examples of designs containing two PHY Lite for Parallel InterfacesIP, each with one bidirectional group composed of 4 data bits and one strobe. Bothinterfaces are in the same I/O column and therefore their tables must be merged.

Figure 64. Parameter Table Example for Intel Arria 10 and Intel Cyclone 10 GX DevicesPHY Lite for Parallel Interfaces IP core 0 PHY Lite for Parallel Interfaces IP core 1Addr Data

Merged Column Parameter TableAddr Data Addr Data

00000001 00000001 0000000100000001 00000001 0000000100000001 00000001 0000000100000008 00000008 000000080003D090 0003D090 0003D090 00000064 00000064 0000008480000044 81000044 8100004400000000 00000000 8000006400000000 00000000 0000000000000000 8100005C 8000005C00000000 00000000 8100007C00000000 00000000 0000000000000000 00000000 0000000000000000 00000000 0000000000000000 00000000 0000000000000000 00000000 0000000000000000 00000000 0000000000013800 00013800 0001380000000001 00000001 00000001

E04C 00000005

E000E004E008E00CE010E014E018E01CE020E024E028E02CE030E034E038E03CE040E044E048

00000005 00000005E050 00540058 00540058 00540058E054 00000000 00000000 00000039E058 00F100E0 00F100E0 39F339E4E05C 00F300F2

E000E004E008E00CE010E014E018E01CE020E024E028E02CE030E034E038E03CE040E044E048E04CE050E054E058

00F300F2 39F739FBE060 000000F4

E05CE060 000000F4 000039FA

000138000000000100000005007400780000003A3AF13AE43AFA3AF900003AF8

E000E004E008E00CE010E014E018E01CE020E024E028E02CE030E034E038E03CE040E044E048E04CE050E054E058E05CE060E064E068E06CE070E074E078E07CE080

Pin pointer

1 group with 5 pins and 1 lane in the interface

Lane pointer

Interface pointer


Number of groupGroup 0 – 5 pins, 1 lane

PHY Lite for Parallel

PHY Lite


for Parallel Interfaces IP core 1


Interfaces IP core 0

strobe_io = lane 0x3A, pin 4data_io [ 0 ] = lane 0x3A, pin 1data_io [ 1 ] = lane 0x3A, pin 9data_io [ 2 ] = lane 0x3A, pin 10data_io [ 3 ] = lane 0x3A, pin 8




115


Important: There is no guarantee of the ordering of the interface parameter tables in the mergedtable. You must perform a search to locate a specific interface parameter.

For more information about the contents of the parameter table, refer to the AddressLookup topic.

Related Information




There are two sets of control registers that store the reconfiguration feature settings:

• Control/Status registers (CSR) - you can only read the values of these registers.The values are set through the IP parameters. The CSR registers contain thedefault setting in the IP.

• Avalon Memory-Mapped registers - you can read and write to these registers usingAvalon interface. The time for the the PHY Lite for Parallel Interfaces delays tochange after writing a new value to the registers via the Avalon bus is dependenton the user's configuration. For example, it takes approximately 50 VCO clockcycles for the output delay to change value. Perform an RTL simulation to show anaccurate timing which correlates to the hardware operation.

4.2.5.3.1. PHY Lite for Parallel Interfaces Intel Arria 10 FPGA IP and PHY Lite for ParallelInterfaces Intel Cyclone 10 GX IPs Address Registers

The following tables show the register bits to construct the control register addressesfor each feature.

Table 64. Address Register for Pin Output Delay Feature


Value Access Type Value Access Type







RO


3'h4 RW 3'h4 RO

[20:13] Specify the lane address ofan interface. This value isdepending on the resourcefitting process duringcompilation.

You can query this inthe Parameter TableLookup Operation

RW You can query this inthe Parameter TableLookup Operation

RO

continued...




116




Sequence asdescribed in the

Address Lookup topic.



[12:8] Specify the address for thephysical location of a pinwithin a lane.



Address Lookup topicor based on your pinassignment setting in

the .qsf file.



Address Lookup topicor based on your pinassignment setting in

the .qsf file.

RO

[7:0] Reserved 8'hD0 RW 8'hE8 RO

Table 65. Address Register for Pin Input Delay Feature







RW N/A RO


3'h4 RW N/A RO





RW N/A RO

[12:9] Reserved 4'hC RW N/A RO

[8:7] Select DQ pin sets toaccess.

• 2'h1: DQ 0 to DQ5

• 2'h2: DQ 6 toDQ11

RW N/A RO

[6:4] Select the specific DQ pin toaccess.





• 3'h4: DQ 4 andDQ 10

• 3'h5: DQ 5 andDQ 11

RW N/A RO





117


Table 66. Address Register for Strobe Input Delay Feature







RW N/A RO


3'h4 RW N/A RO





RW N/A RO

[12:0] Reserved 13'18E0 RW N/A RO

Table 67. Address Register for Strobe Enable Phase Feature









RO


3'h4 RW 3'h4 RO








RO

[12:0] Reserved 13h'18F0 RW 13'h1998 RO

Table 68. Address Register for Strobe Enable Delay Feature









RO

continued...




118





3'h4 RW 3'h4 RO








RO

[12:0] Reserved 13'h1808 RW 13'h19A8 RO

Table 69. Address Register for Read Valid Delay Feature







RW Dependingon the

InterfaceID

parameter inthe

ParameterEditor.

RO

[23:21] Specify the Avalon controllercalibration bus base address.

3'h4 RW 3'h4 RO



Sequence asdescribed in theAddress Lookup

topic.

RW You canquery this in

theParameter

Table LookupOperation

Sequence asdescribed inthe Address

Lookuptopic.

RO

[12:0] Reserved 13'h180C RW 13'h19A4 RO

Related Information


4.2.5.3.2. Control Registers Description

When you generate a read operation to the control registers addresses, the Avaloninterface returns a set of values from the control registers. The following tables showthe definition of the bits for each control register.




119


Table 70. Control Register Description


Pin Output Delay [31:13] Reserved (9)

[12:0] Phase valueStrobe minimum setting: Refer to the Output andStrobe Enable Minimum and Maximum PhaseSettings topic.Strobe maximum setting: Refer to the Output andStrobe Enable Minimum and Maximum PhaseSettings topic.Incremental Delay: 1/128th VCO clock periodThe CSR value for DQS is set through the OutputStrobe Phase parameter during IP instantiation.Note: The pin output delay switches from the CSR

register value to the Avalon register valueafter the first Avalon write. It is only reset tothe CSR register value on a reset of theinterface.

Pin Input Delay [31:13] Reserved (9)

[12] Enable bit to select access to Avalon register or CSRregister.0 = Delay value is 0. CSR register is not available forthis feature.1 = Select delay value from Avalon register

[11:9] Reserved (9)

[8:0] Delay valueMinimum Setting: 0Maximum Setting: 511 VCO clock periodsIncremental Delay: 1/256th VCO clock period

Strobe Input Delay [31:13] Reserved (9)

[12] Enable bit to select access to Avalon register or CSRregister.0 = Delay value is 0. CSR register is not available forthis feature.1 = Select delay value from Avalon registerModifying these values must be done on all lanes in agroup.

[11:10] Reserved(9)

[9:0] Delay valueMinimum Setting: 0Maximum Setting: 1023 VCO clock periodsIncremental Delay: 1/256th VCO clock periodModifying these values must be done on all lanes in agroup.

Strobe Enable Phase [31:16] Reserved (9)

[15] Enable bit to select access to Avalon register or CSRregister.0 = Select delay value from CSR register. The CSRvalue is set through the Capture Strobe PhaseShift parameter during IP instantiation.

continued...

(9) Reserved bit ranges must be zero




120



1 = Select delay value from Avalon registerModifying these values must be done on all lanes in agroup.

[14:13] Reserved(9)

[12:0] Bit [12:0]: Phase valueMinimum Setting: Refer to the Output and StrobeEnable Minimum and Maximum Phase Settings topic.Maximum Setting: Refer to the Output and StrobeEnable Minimum and Maximum Phase Settings topic.Incremental Delay: 1/128th VCO clock periodModifying these values must be done on all lanes in agroup.

Strobe Enable Delay [31:16] Reserved(9)


[14:6] Reserved(9)


Read Valid Delay [31:16] Reserved(9)


[14:7] Reserved


Important: For more information about performing various clocking and delay calculations,depending on the interface frequency and rate, refer to PHYLite_delay_calculations.xlsx.

Related Information

Output and Strobe Enable Minimum and Maximum Phase Settings on page 123




121



4.2.5.4. Calibration Guidelines

The PHY Lite for Parallel Interfaces IP allows you to dynamically reconfigure thefeatures of the interface. However, performing calibration is an application specificprocess. This section provides some general guidelines for calibrating the Intel Arria10, and Intel Cyclone 10 GX I/O architecture.


The read pointer in the read FIFO buffer gets reset when reads are far apart (80 coreclock cycles). However, the data inside the FIFO is not cleared. Therefore, analternating pattern should be used to find the end to the strobe enable window toavoid reading stale data in the FIFO.

The strobe enable signal turns itself off on the last negative edge of the strobe.Therefore, while finding the enable window, use extra dummy pulses (either extendedstrobe or reads from memory without asserting the rdata_en signal) to clear thestrobe enable.




122



When dynamically reconfiguring the interpolator phase settings, the values must bekept within the ranges below to ensure proper operation of the circuitry.


VCOMultiplication


Phase


1 Full 0x080 0x100 0x100 0xA80

Half 0x080 0x100 0x100 0xBC0

Quarter 0x080 0x100 0x100 0xA00

2 Full 0x080 0x100 0x180 0x1400

Half 0x080 0x100 0x180 0x1400

Quarter 0x080 0x100 0x180 0x1400

4 Full 0x080 0x100 0x280 0x1FFF

Half 0x080 0x100 0x280 0x1FFF


8 Full 0x080 0x100 0x480 0x1FFF

Half 0x080 0x100 0x480 0x1FFF


For more information about performing various clocking and delay calculations,depending on the interface frequency and rate, refer to PHYLite_delay_calculations.xlsx.


You can instantiate the PHY Lite for Parallel Interfaces IP from IP Catalog in IntelQuartus Prime software. Intel provides an integrated parameter editor that allows youto customize this IP to support a wide variety of applications.


Related Information







123







Table 72. PHY Lite for Parallel Interfaces IP Parameter Settings


Description

Parameter



Clocks


533.0 MHz External memory clock frequency.Note: To achieve timing closure at 534 MHz

and above, use dynamic reconfigurationto calibrate the interface. Compile yourdesign with Intel Quartus Prime withaccurate board skew information for finaltiming analysis.



PLL reference clock frequency Dependent ondesired memoryclock frequency

133.25 MHz PLL reference clock frequency. You must feed aclock of this frequency to the PLL referenceclock input of the memory interface.Note: There is no minimum range, but the

maximum output frequency is 1600 MHz,limited by the clock network. Theminimum range for the ref_clk signalis 10 MHz but the maximum isdependent on the speed grade.



Clock rate of user logic Full, Half, Quarter Quarter Determines the clock frequency of user logic inrelation to the memory clock frequency. Forexample, if the memory clock sent from theFPGA to the memory device is toggling at 800MHz, a "Quarter rate" interface means that theuser logic in the FPGA runs at 200 MHz.

Specify additional outputclocks based on existing PLL

On, Off Off Exposes additional output clocks from theexisting PLL.Important: PHY Lite for Parallel Interfaces in

Intel Arria 10 and Intel Cyclone 10GX devices do not support exposingadditional output clocks when VCOfrequency is below 600 MHz.

Output ClocksNote: These parameters are available only if the Specify additional output clocks based on existing PLL parameter

is turned on

Number of additional clocks 0 to 4 0 Specifies the number of additional clocks to beexposed.

continued...




124



Description

Important: PHY Lite for Parallel Interfaces inIntel Arria 10 and Intel Cyclone 10GX devices do not support exposingadditional output clocks when VCOfrequency is below 600 MHz.

outclk[4:0] (Reserved) — — PLL output clocks with the flag (Reserved) in theQSYS GUI are reserved for PHY Lite for ParallelInterfaces IP internal functionality.

Desired Frequency — 133.25 MHz Specifies the output clock frequency of thecorresponding output clock port, outclk[], inMHz. The minimum and maximum valuesdepend on the device used. The PLL only readsthe numerals in the first six decimal places.

Actual Frequency — 133.25 MHz Allows you to select the actual output clockfrequency from a list of achievable frequencies.

Phase shift units ps or degrees ps Specifies the phase shift unit for thecorresponding output clock port, outclk[], inpicoseconds (ps) or degrees.

Phase shift — 469.0 ps Specifies the requested value for the phaseshift. The default value is 0 ps.

Actual phase shift — 469.0 ps Allows you to select the actual phase shift froma list of achievable phase shift values. Thedefault value is the closest achievable phaseshift to the desired phase shift.

Desired duty cycle 0.0–100.0 50.0 % Specifies the requested value for the duty cycle.

Actual duty cycle — 50.0 % Allows you to select the actual duty cycle from alist of achievable duty cycle values. The defaultvalue is the closest achievable duty cycle to thedesired duty cycle.


Use dynamic reconfiguration On, Off Off Exposes an Avalon memory-mapped interface,allowing you to control the configuration of thePHY Lite for Parallel Interfaces IP settings.

Interface ID — 0 The ID used to identify this interface in the I/Ocolumn over the Avalon memory-mapped bus.

I/O Settings

I/O standard SSTL-12SSTL-125SSTL-135SSTL-15

SSTL-15 Class ISSTL-15 Class IISSTL-18 Class ISSTL-18 Class II1.2-V-HSTL Class

I1.2-V-HSTL Class

II1.5-V-HSTL Class

I1.5-V-HSTL Class

II

SSTL-15 ClassI

Specifies the I/O standard of the interface'sstrobe and data pins written to the .qip file ofthe IP instance. When you choose None, theI/O standard is unspecified in the generated IP.

continued...




125



Description

1.8-V-HSTL ClassI

1.8-V-HSTL ClassII

1.2-V POD1.2-V1.5-V1.8-VNone


Single-ended,LVDS with on-

chip termination,LVDS without on-chip termination

Single-ended Specify the reference clock I/O configuration.

General Settings

Fast simulation model On, Off Off Turn on this option to reduce PHY Lite forParallel Interfaces IP simulation time.Note: This option is preliminarily supported in

Intel Quartus Prime v18.1.

Group <x> - these parameters are set on a per group basis

Group <x> Parameter Settings

Copy parameters from anothergroup

On, Off Off Select this option when you want to copy theparameter settings from another group.Set Number of groups to more than 1 toenable this option.

Group 1 - 17 1 Choose the group index that you want as theparameter settings source. The changes madeto the source is updated automatically to all thetarget groups.You can only choose the group index which theparameter settings are not copied from anothergroup.Set Number of groups to more than 1 toenable this option.

Group <x> Pin SettingsNote: These parameters are disabled when Copy parameters from another group is enabled.



Pin width 1 to 48 9 Number of pins in this data/strobe group.A data width up to 48 is achievable if no strobeis used in the group. The number of strobes iscontrolled by the Use output strobe, Strobeconfiguration and Use separate capturestrobe parameters.


Group <x> Input Path SettingsNote: These parameters are disabled when Copy parameters from another group is enabled.


cycles

7 Expected read latency of the external device inmemory clock cycles.

continued...




126



Description

For example, a design with an external clockfrequency of 533 MHz in half-rate has a validread latency range of 5 to 63 external interfaceclock cycles.Refer to the Read Latency topic for minimumread latency settings based on FPGA core clockrate.

Swap capture strobe polarity On, Off Off Internally swap the negative and positivecapture strobe input pins. This feature is onlyavailable for complementary strobeconfigurations.



Group <x> Output Path SettingsNote: These parameters are disabled when Copy parameters from another group is enabled.

Write latency 0 to 3 (maximumvalue is

dependent on therate)

0 Additional delay added to the output data inmemory clock cycles.Refer to the Write Latency topic for write latencysettings based on FPGA core clock rate.

Use output strobe On, Off On Use an output strobe.



Group <x> General Data SettingsNote: These parameters are disabled when Copy parameters from another group is enabled.

Data configuration Single ended,Differential

Single ended Selects the type of data. Single ended data typeuses one pin. Differential data type uses 2 pins.Refer to the I/O Standards topic for a list ofsupported I/O standards.


Strobe configuration Single ended,Differential,

Complementary

Single ended Select the type of strobe. A single ended strobeuses one pin, which reduces the maximumpossible number of data pins in the group to 47.Differential/complementary strobe types use 2pins, which reduces the maximum possiblenumber of data pins in the group to 46.Note: The differential strobe configuration uses

a differential input buffer, whichproduces a single clock for the captureDDIO and read FIFO. Thecomplementary strobe configurationuses two single-ended input buffers andclocks the data into the capture DDIOand read FIFO using both clocks (asrequired by protocols such as QDRII).The output path functionality is thesame.

Refer to the I/O Standards topic for a list ofsupported I/O standards.

Use separate strobes On, Off Off Separate the bidirectional strobe into input andoutput strobe pins. Use separate strobes is onlyavailable for a bidirectional data group with theoutput strobe enabled.

continued...




127



Description

Group <x> OCT SettingsNote: These parameters are disabled when Copy parameters from another group is enabled.

OCT enable size 0 - 4 (Intel Arria10 and Intel

Cyclone 10 GXdevices)

1 Specifies the delay between the OCT enablesignal assertion and the dqs_enable signalassertion. You must set a value that is largeenough to ensure that the OCT is turn on beforesampling input data.Note: For Intel Quartus Prime software version

prior to 17.0, refer to related informationfor known issue.

Expose termination ports On, Off Off Turn on to expose the series and paralleltermination ports to connect separate OCTblock.To enable this option, turn off Use Default OCTValues parameter and select a value for InputOCT Value or Output OCT Value parameters.

Use Default OCT Values — Use default OCT values based on the I/Ostandard parameter setting.

Input OCT Value No termination,<n> ohm with

calibration

Notermination

Specifies the group's data and strobe inputtermination values to be written to the .qip ofthe IP instance. The list of legal values isdependent on the I/O standard parametersetting. Refer to the I/O Standards topic forsupported termination values.This option is available when the Use DefaultOCT Values option is disabled.

Output OCT Value No termination,<n> ohm with

calibration, <n>with no

calibration

Notermination

Specifies the group's data and strobe inputtermination values to be written to the .qip ofthe IP instance. The list of legal values isdependent on the I/O standard parametersetting. Refer to the I/O Standards topic forsupported termination values.This option is available when the Use DefaultOCT Values option is disabled.

Group <x> Timing SettingsNote: These parameters are disabled when Copy parameters from another group is enabled.

Generate Input DelayConstraints for this group

On, Off On Instructs SDC to generate set_input_delayconstraints for this group.

Input Strobe Setup DelayConstraint

Constraint in ns 0.03 ns Specifies the group's input setup delayconstraint against the input strobe.

Input Strobe Hold DelayConstraint

Constraint in ns 0.03 ns Specifies the group's input hold delay constraintagainst the input strobe.

Inter Symbol Interference ofthe Read Channel

Constraint in ns 0.09 ns Specifies the Inter Symbol Interference valuefor DQS signal of read channel.Specify a positive value to decrease the setupand hold slack by half of the entered value.

Generate Output DelayConstraints for this group

On, Off On Instructs SDC to generate set_output_delayconstraints for this group.

Output Strobe Setup DelayConstraint

Constraint in ns 0.03 ns Specifies the group's output setup delayconstraint against the input strobe.

Output Strobe Hold DelayConstraint

Constraint in ns 0.03 ns Specifies the group's output hold delayconstraint against the input strobe.

continued...




128



Description

Inter Symbol Interference ofthe Write Channel

Constraint in ns 0.09 ns Specifies the Inter Symbol Interference valuefor DQS signal of write channel.Specify a positive value to decrease the setupand hold slack by half of the entered value.

Group <x> Dynamic Reconfiguration Timing SettingsNote: These parameters are disabled when Copy parameters from another group is enabled.

Dynamic Reconfiguration ReadDeskew Algorithm



DQ Per-BitDeskew

Specifies the Read Deskew algorithm for TimingAnalyzer to use when performing I/O timinganalysis:• DQ Per-Bit Deskew: Each DQ pin is adjusted

independently to minimize the skew withinthe DQ bits. DQS signal is adjusted to center-align to the de-skewed DQ bus. Each DQ bitmay have different delay chain settings.

• DQ Group Deskew: DQS signal is adjustedcenter-align to the DQ bus without de-skewing individual DQ bits. All DQ bits withinthe same group has same delay chainsettings.



Setup Slack Recoverable ofCustom Read Deskew

Algorithm

Constraint in ns 0.0 ns Specifies the amount of positive setup slackavailable based on your custom read deskewalgorithm.This parameter is available with the conditions:• Use dynamic reconfiguration is turn on• Pin type is set to Input or Bidirectional



Hold Slack Recoverable ofCustom Read Deskew

Algorithm

Constraint in ns 0.0 ns Specifies the amount of positive hold slackavailable based on your custom read deskewalgorithm.This parameter is available with the conditions:• Use dynamic reconfiguration is turn on• Pin type is set to Input or Bidirectional



Dynamic ReconfigurationWrite Deskew Algorithm



DQ Per-BitDeskew

Specifies the Write Deskew algorithm for TimingAnalyzer to use when performing I/O timinganalysis:• DQ Per-Bit Deskew: DQS signal is centered to

each individual DQ bits. Each DQ bit mayhave different delay chain settings.

• DQ Group Deskew: DQS signal is centered tothe DQ bus group. All DQ bits within thesame group has same delay chain settings.


continued...




129



Description


Setup Slack Recoverable ofCustom Write Deskew

Algorithm

Constraint in ns 0.0 ns Specifies the amount of positive setup slackavailable based on your custom write deskewalgorithm.This parameter is available with the conditions:• Use dynamic reconfiguration is turn on• Pin type is set to Output or Bidirectional



Hold Slack Recoverable ofCustom Write Deskew

Algorithm

Constraint in ns 0.0 ns Specifies the amount of positive hold slackavailable based on your custom write deskewalgorithm.This parameter is available with the conditions:• Use dynamic reconfiguration is turn on• Pin type is set to Output or Bidirectional



Related Information

• KDB link: Can the Intel® Arria® 10 and Intel Cyclone® 10 GX I/O PLL have a VCOfrequency below the minimum value shown in the device datasheets?

• KDB link: Unsupported OCT enable size values for Arria 10 Altera PHYLite.Applicable to Quartus Prime software version prior to 17.0.

• Read Latency on page 130

• Write Latency on page 131

• I/O Standards on page 136


Table 73. Minimum Read LatencyThis table shows the minimum read latency value supported by PHY Lite for Parallel Interfaces based on thecore clock rate and VCO multiplier factor settings.


Full rate 1 4

2 4

4 3

8 3

Half rate 1 5

2 5

4 4

8 4

Quarter rate 1 7

continued...




130



https://www.altera.com/support/support-resources/knowledge-base/solutions/rd08172016_561.html



2 7

4 7

8 7


Table 74. Maximum Write LatencyThis shows the maximum write latency value supported by PHY Lite for Parallel Interfaces IP based on the coreclock rate and VCO multiplier factor settings.


Full rate 1 0

2 0

4 0

8 0

Half rate 1 1

2 1

4 1

8 1

Quarter rate 1 3

2 3

4 3

8 2

4.3.2. Signals




ref_clk Input 1 Reference clock for the PLL. The reference clock must besynchronous with strobe_in to ensure the dqs_enable signalis in-sync with strobe_in.

reset_n Input 1 Resets the interface. This signal is asynchronous.

interface_locked Output 1 Interface locked signal from PHY Lite for Parallel Interfaces IP toIntel FPGA core. This signal indicates that the PLL and PHYcircuitry are locked.Data transfer should starts after the assertion of this signal.

core_clk_out Output 1 Use this core clock in the core-to-periphery transfer of soft logicdata and control signals.

continued...




131



The core_clk_out frequency depends on the interfacefrequency and clock rate of user logic parameter.

pll_extra_clock[0..3] Output 4 These are the additional output clock signals generated by PHYLite for Parallel Interfaces IP when you enable Specify additionaloutput clocks based on existing PLL parameter.Important: PHY Lite for Parallel Interfaces in Intel Arria 10 and

Intel Cyclone 10 GX devices do not support exposingadditional output clocks when VCO frequency isbelow 600 MHz.

pll_locked Output 1 This is the locked signal for the additional output clocks generatedby the IP.


Table 76. Output Path SignalsOutput path signals are signals that are available when you set the Pin Type parameter to either Output orBidirectional.


oe_from_core Input Quarter-rate: 4 x PIN_WIDTHHalf-rate: 2 x PIN_WIDTHFull-rate: 1 x PIN_WIDTH

Output enable signal from core logic.Synchronous to the core_clkoutput from the IP.

data_from_core Input

Quarter rate-DDR: 8 x PIN_WIDTHHalf-rate DDR: 4 x PIN_WIDTHFull-rate DDR: 2 x PIN_WIDTHQuarter-rate SDR: 4 x PIN_WIDTHHalf-rate SDR: 2 x PIN_WIDTHFull-rate SDR: 1 x PIN_WIDTH

Data signal from core logic.Synchronous to the core_clkoutput from the IP.

strobe_out_in Input Quarter-rate: 8Half-rate: 4Full-rate: 2

Strobe signal from core logic.Synchronous to the core_clkoutput from the IP.Note: This path is always DDR.

strobe_out_en Input Quarter-rate: 4Half-rate: 2Full-rate: 1

Strobe output enable from core logic.Synchronous to the core_clkoutput from the IP.

data_out/data_io Output/Bidirectional

• 1 to 48 if data configuration isSingle Ended

• 1 to 24 if data configuration isDifferential

Data output from PHY Lite for ParallelInterfaces IP. Synchronous to thestrobe_out or strobe_io outputfrom the IP.If the Pin Type parameter is set toOutput, the data_out signals areused. If the Pin Type parameter isset to Bidirectional, the data_iosignals are used.

data_out_n/data_io_n


1 to 24 Negative data output from PHY Litefor Parallel Interfaces IP is enabledwhen data configuration is set toDifferential. Data is synchronous tothe strobe_out or strobe_iooutput from the IP. If the Pin Type isset to Output, the data_out_n

continued...




132



ports are used. If the pin type is setto Bidirectional, the data_io_nports are used.

strobe_out/strobe_io


1 Positive output strobe from PHY Litefor Parallel Interfaces IP. If the PinType is set to Output, thestrobe_out signal is used. If thePin Type is set to Bidirectional thestrobe_io signal is used. The UseSeparate Strobes parameter forcesthe use of the strobe_out signalwith a Bidirectional Pin Type.

strobe_out_n/strobe_io_n


1 Negative output strobe from PHY Litefor Parallel Interfaces IP.This is used if the StrobeConfiguration is set to Differentialor Complementary.If the Pin Type is set to Output, thestrobe_out_n signal is used. If thePin Type is set to Bidirectional, thestrobe_io_n signal is used. TheUse Separate Strobes parameterforces the use of the strobe_out_nsignal with a Bidirectional PinType.


Table 77. Input Path SignalsInput path signals are signals that are available when you set the Pin Type parameter to Input orBidirectional.


data_to_core Output Quarter-rate DDR: 8 x PIN_WIDTHHalf-rate DDR: 4 x PIN_WIDTHFull-rate DDR: 2 x PIN_WIDTH

Quarter-rate SDR: 4 x PIN_WIDTHHalf-rate SDR: 2 x PIN_WIDTHFull-rate SDR: 1 x PIN_WIDTH

Output data to the core logic. Validon rdata_valid. Synchronous tothe core_clk output from the PHY

Lite for Parallel Interfaces IP.

rdata_en Input Quarter-rate: 4Half-rate: 2Full-rate: 1

This signal represents the number ofexpected words to read from the

external device.This signal is set to high after a readcommand is issued. Synchronous tothe core_clk output from the PHY

Lite for Parallel Interfaces IP.When using the IP as a receiver,

assert this signal afterinterface_locked signal is

asserted and strobe_in is stable.

rdata_valid Output Quarter-rate: 4Half-rate: 2Full-rate: 1

This signal determines which data arevalid when reading from Read FIFO.


clock cycles.

continued...




133



Synchronous to the core_clkoutput from the PHY Lite for Parallel

Interfaces IP.

data_in/

data_io

Input/Bidirectional


1 to 24 if data configuration is Differential

Input and output data from/toexternal device. Synchronous to thestrobe_in or strobe_io input.

The first data_in must be associatedwith positive edge of strobe_in/

strobe_io.If the pin type is set to Input, thedata_in ports are used. If the pintype is set to bidirectional, the

data_io ports are used.

data_in_n/

data_io_n

Input/Bidirectional

1 to 24 Negative data input/output fromexternal device enabled when dataconfiguration is set to Differential.

Data is synchronous to thestrobe_in or strobe_io input. If

the pin type is set to Input, thedata_in_n ports are used. If the pin

type is set to bidirectional, thedata_io_n ports are used.

strobe_in/strobe_io

Input/Bidirectional

1 Input and output strobe from/toexternal device. If the pin type is setto Input, the strobe_in signal is

used. If the pin type is set toBidirectional, the strobe_io signal

is used.

strobe_in_n/strobe_io_n

Input/Bidirectional


Configuration parameter is set toDifferential or Complementary. If

the pin type is set to Input, thestrobe_in_n signal is used. If thepin type is set to Bidirectional, the

strobe_io_n signal is used.




134


4.3.2.4. Avalon Configuration Bus Interface Signals

The PHY Lite for Parallel Interfaces IP exposes the Avalon memory-mapped slave andAvalon memory-mapped master interfaces when you perform dynamicreconfiguration. Connect the Avalon memory-mapped slave to either a master in thecore or the master interface of either an PHY Lite for Parallel Interfaces IP or theExternal Memory Interface IP to be placed in the same column. You can only connectthe master interface to the slave interface of a PHY Lite for Parallel Interfaces IP orExternal Memory Interface IP to be placed in the same column.

Table 78. Avalon Memory-mapped Master Interface Signals


avl_clk Input 1 Avalon interface clock.

avl_reset_n Input 1 Reset input synchronous to avl_clk.

avl_read Input 1 Read request from io_aux. This signal is synchronous to theavl_clk input.

avl_write Input 1 Write request from io_aux. This signal is synchronous to theavl_clk input.

avl_byteenable Input 4 Controls which bytes should be written on avl_writedata.

avl_address Input 28 (Intel Arria10 and Intel


Address from io_aux. This signal is synchronous to theavl_clk input.

avl_readdata Output 32 Read data to io_aux. This signal is synchronous to theavl_clk input.

avl_writedata Input 32 Write data from io_aux. This signal is synchronous to theavl_clk input.

avl_readdata_valid Output 1 Indicates that read data has returned.

avl_waitrequest Output 1 Stalls upstream logic when it is asserted.

Table 79. Avalon Memory-mapped Slave Interface Signals


avl_out_clk Output 1 Connect this signal to the input Avalon interface of anotherPHY Lite for Parallel Interfaces IP or the External Memory

Interfaces IP.

avl_out_reset_n Output 1 Connect this signal to the input Avalon interface of anotherPHY Lite for Parallel Interfaces IP or the External Memory

Interfaces FPGA IP.

avl_out_read Output 1 Indicates read transaction.

avl_out_write Output 1 Indicates write transaction.

avl_out_byteenable Output 4 Controls which bytes should be written onavl_out_writedata.

avl_out_writedata Output 32 The data packet associated with the write transaction.

avl_out_address Output 28 (Intel Arria10 and Intel


Avalon address (in byte granularity). Value is identical toavl_address but with zeroes padded on the LSBs.

continued...




135



avl_out_readdata Input 32 The data packet associated withavl_out_readdata_valid.

avl_out_readdata_valid

Input 1 Indicates that read data has returned.

avl_out_waitrequest Input 1 Stalls upstream logic when it is asserted.

Related Information

Dynamic Reconfiguration on page 111For more information about connecting these signals

4.3.2.5. Termination Signals

Table 80. Termination SignalsThe termination signals are signals that are available when you enable the Expose termination portsparameter.


group_seriesterminationcontrol

Input 16 Connect this signal to the seriestermination control signal of the OCTIntel FPGA IP to receive seriestermination code to calibrate Rs.

group_parallelterminationcontrol

Input 16

Connect this signal to the paralleltermination control signal of the OCTIntel FPGA IP to receive paralleltermination code to calibrate Rt.

4.4. I/O Standards

The PHY Lite for Parallel Interfaces IP allows you to set I/O standards on the pinsassociated with the generated configuration. The I/O standard controls the availablestrobe configurations and OCT settings for all groups.

Table 81. I/O Standards and Termination Values for Intel Arria 10 Devices


(10)

Valid OutputCalibrated/

UncalibratedTerminations

(Ω)(10)

RZQ(Ω) (11)


SSTL-12 (12) 60, 120 40, 60 240 Yes

SSTL-125 (12) 60, 120 34, 40 240 Yes

SSTL-135 (12) 60, 120 34, 40 240 Yes

SSTL-15 (12) 60, 120 34, 40 240 Yes

continued...

(10) 0 is equivalent to no termination.

(11) RZQ pin is not required for uncalibrated output terminations.

(12) Use this I/O standard if input termination is required with interface frequency more than 533MHz.




136



(10)



(Ω)(10)

RZQ(Ω) (11)


SSTL-15 Class I (13) 0, 50 0, 50 100 Yes

SSTL-15 Class II(13) 0, 50 0, 25 100 Yes

SSTL-18 Class I(13) 0, 50 0, 50 100 Yes

SSTL-18 Class II(13) 0, 50 0, 25 100 Yes

1.2-V HSTL Class I(13) 0, 50 0, 50 100 Yes

1.2-V HSTL Class II(13) 0, 50 0, 25 100 Yes

1.5-V HSTL Class I(13) 0, 50 0, 50 100 Yes


1.8-V HSTL Class I(13) 0, 50 0, 50 100 Yes


1.2-V POD 34, 40, 48, 60, 80,120, 240

34, 40, 48,60

240 Yes

1.2-V — — — No

1.5-V — — — No

1.8-V — — — No

Table 82. I/O Standards and Termination Values for Intel Cyclone 10 GX Devices

I/O Standard Valid InputTerminations

(Ω) (10)



(Ω)(10)

RZQ(Ω) (11)


SSTL-12 (14) 60, 120 40, 60 240 Yes

SSTL-125 (14) 60, 120 34, 40 240 Yes

SSTL-135 (14) 60, 120 34, 40 240 Yes

SSTL-15 (14) 60, 120 34, 40 240 Yes

SSTL-15 Class I (15) 0, 50 0, 50 100 Yes

SSTL-15 Class II(15) 0, 50 0, 25 100 Yes

continued...

(10) 0 is equivalent to no termination.

(11) RZQ pin is not required for uncalibrated output terminations.

(13) Use this I/O standard if input termination is required with interface frequency equal or lessthan 533 MHz.

(14) Use this I/O standard if input termination is required with interface frequency more than 533MHz.

(15) Use this I/O standard if input termination is required with interface frequency equal or lessthan 533 MHz.




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I/O Standard Valid InputTerminations

(Ω) (10)



(Ω)(10)

RZQ(Ω) (11)


SSTL-18 Class I(15) 0, 50 0, 50 100 Yes

SSTL-18 Class II(15) 0, 50 0, 25 100 Yes

1.2-V HSTL Class I(15) 0, 50 0, 50 100 Yes


1.5-V HSTL Class I(15) 0, 50 0, 50 100 Yes


1.8-V HSTL Class I(15) 0, 50 0, 50 100 Yes


1.2-V POD 34, 40, 48, 60, 80,120, 240

34, 40, 48,60

240 Yes

1.2-V — — — No

1.5-V — — — No

1.8-V — — — No

Related Information

• On-Chip I/O Termination in Intel Arria 10 Devices

• On-Chip I/O Termination in Intel Cyclone 10 GX Devices

• KDB link: Selected input mode termination value for data bus is not valid. Pleaseselect a value of 50 ohm or higher.

Input termination limitation for PHY Lite for Parallel Interfaces IP.




Note: The VREF settings are at the lane level, so all pins using a lane must have the sameVREF settings (including GPIOs).




CALIBRATED Use internal VREF generated using VREF codes from the Avalon memory-mapped reconfigurationbus.




continued...




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https://www.intel.com/content/altera-www/global/en_us/index/support/support-resources/knowledge-base/emif/2016/why-do-i-see-_selected-input-mode-termination-value-for-data-bus.html

https://www.intel.com/content/altera-www/global/en_us/index/support/support-resources/knowledge-base/emif/2016/why-do-i-see-_selected-input-mode-termination-value-for-data-bus.html






Figure 65. VREF

Input Buffer

+

-Vref

R

R

VCCIO

Internal VREF




+

-

VCCIO

Rt

External VREF

Resistor Ladder

4.4.1.1. Calibrated VREF Settings

Table 84. Calibrated VREF SettingsThis table lists the calibrated VREF settings that you can set over the Avalon memory-mapped calibration bus.This table is applicable to all Intel FPGA devices.


000000 60.00%

000001 60.64%

000010 61.28%

000011 61.92%

000100 62.56%

000101 63.20%

continued...




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000110 63.84%

000111 64.48%

001000 65.12%

001001 65.76%

001010 66.40%

001011 67.04%

001100 67.68%

001101 68.32%

001110 68.96%

001111 69.60%

010000 70.24%

010001 70.88%

010010 71.52%

010011 72.16%

010100 72.80%

010101 73.44%

010110 74.08%

010111 74.72%

011000 75.36%

011001 76.00%

011010 76.64%

011011 77.28%

011100 77.92%

011101 78.56%

011110 79.20%

011111 79.84%

100000 80.48%

100001 81.12%

100010 81.76%

100011 82.40%

100100 83.04%

100101 83.68%

100110 84.32%

100111 84.96%

101000 85.60%

101001 86.24%

continued...




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101010 86.88%

101011 87.52%

101100 88.16%

101101 88.80%

101110 89.44%

101111 90.08%

110000 90.72%

110001 91.36%

110010 92.00%

110011 -> 111111 Reserved

Related Information



PHY Lite for Parallel Interfaces IP provides valid OCT settings for each group (refer tothe I/O Standards topic for supported termination values). These settings are writtento the .qip of the instance during generation. If you select an I/O standard thatsupports OCT in the General tab, you can use the OCT blocks provided in the IntelArria 10 and Intel Cyclone 10 GX devices.




Related Information



The RZQ_GROUP assignment creates the OCT Intel FPGA IP without modifying the RTL.The Fitter searches for the rzq pin name in the netlist. If the pin does not exist, theFitter creates the pin name along with the OCT Intel FPGA IP and its correspondingconnections. This allows you to create a group of pins to be calibrated by an existingor non-existing OCT and the Fitter ensures the legality of the design. You mustassociate the terminated pins of the PHY Lite for Parallel Interfaces IP instance with anRZQ pin at the system level manually.

Use the following steps to set RZQ pin locations for the PHY Lite for Parallel InterfacesIP:

1. In the Group <x> OCT Settings tab, disable Use Default OCT Values andExpose termination ports.




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Figure 66. Group <x> OCT Settings Parameter Settings






set_instance_assignment -name RZQ_GROUP <rzq_pin_name> -to <altera_phylite_strobe_pin>

set_instance_assignment -name RZQ_GROUP <rzq_pin_name> -to <altera_phylite_data_pin[*]>









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4.4.2.2. Manual Insertion of OCT Block

You may also instantiate the OCT Intel FPGA IP separately in your project and connectthe termination ports to the PHY Lite for Parallel Interfaces.

1. Expose the PHY Lite for Parallel Interfaces termination ports by disable UseDefault OCT Values.

2. Select the available OCT values in the Input OCT Value parameter. This displaysthe Expose termination ports parameter.

Note: For supported input and output OCT values, refer to the I/O Standardstopic.

3. Select Expose termination ports to expose the termination ports in the IP.

4. Connect the termination ports to a OCT Intel FPGA IP either in power-up or usermode.

Figure 67. RTL View of PHY Lite for Parallel Interfaces IP Interfacing with OCT IntelFPGA IP in User Mode

group_0_data_in[3:0]

cal_requestrefclk

rstnoctrzqin0

group_0_strobe_in

calibration_requestclockresetrzqin

oct_test_ip

group_0_data_in[3:0]group_0_parallelterminationcontrol[15:0]

4’h0group_0_rdata_en[3:0]group_0_seriesterminationcontrol[15:0]

phylite_test_ip

group_0_strobe_in32’h0group_1_data_from_core[31:0]

16’h0group_1_oe_from_core[15:0]group_1_parallelterminationcontrol[15:0]

group_1_seriesterminationcontrol[15:0]4’h0group_1_strobe_out_en[3:0]8’h0group_1_strobe_out_en[7:0]

ref_clkreset_n

group_1_data_out[3:0]group_1_strobe_outinterface_locked

oct_0_parallel_termination_control[15:0]

oct_0_series_termination_control[15:0]

u1

u0

Related Information





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Follow these guidelines to place the PHY Lite for Parallel Interfaces IP group pins.

1. All groups in a PHY Lite for Parallel Interfaces IP must be placed across acontiguous set of lanes. The number of lanes depends on the number of pins usedby the group.

2. Two groups, from either the same or different PHY Lite for Parallel Interfaces IP,cannot share an I/O lane.

3. For PHY Lite for Parallel Interfaces IP instance that spans more than one I/O bank,all groups in the interface must be placed across a contiguous set of banks withinan I/O column. The number of I/O banks required depends on the memoryinterface width.

4. Pins that are not used in an I/O bank are available as general purpose I/O (GPIO)pins.

5. To constrain groups from separate PHY Lite for Parallel Interfaces IP instances intothe same I/O bank, the instances must share the same reference clock and resetsources, the same external memory frequencies, and the same voltage settings.

6. A reference clock network can only span across maximum of 6 I/O banks.

7. You cannot share the OCT termination block across the I/O column. You canassociate the terminated pins of the PHY Lite for Parallel Interfaces IP instancewith an RZQ pin through RZQ_GROUP assignment.

Table 85. Group Pin PlacementPHY Lite for Parallel Interfaces IP does not support DQS for X4.

Number of Pins in Group Valid DQS Group in a Bank Valid Index in a Bank

1-12 DQS for X8/X9 0-11/12-23/24-35/36-47

13-24 DQS for X16/X18 0-23/24-47

25-48 DQS for X32/X36 0-47

Related Information

Pin-Out Files for Intel FPGA DevicesFor specific DQS group numbers refer to the specific device pin-out file


You are recommended to source the reference clock to the PHY Lite for ParallelInterfaces IP from a dedicated clock pin. Use the clock pin in one of the I/O banksused by the PHY Lite for Parallel Interfaces IP. You must use contiguous I/O banks toimplement multiple interfaces (consisting of a combination of External MemoryInterface and PHY Lite for Parallel Interfaces IP). If you use the same reference clockfor these interfaces, place the reference clock in any of the contiguous I/O banks.




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Note: For Intel Quartus Prime software version 18.1 or later, you may see error warningmessage for design with encrypted IOPLL IP. The auto-generated .sdc files of theIOPLL IP are not supported if you use encryption. You must manually create the .sdcfile using create_clock and create_generated_clock to replace the auto-generated .sdc file in the design for refclk and output clocks.

Related Information

• Guideline: I/O Standards Supported for I/O PLL Reference Clock Input Pin

• Clock Networks and PLLs in Intel Arria 10 Devices - PLL CascadingFor more information about PLL cascading in Intel Arria 10 devices.

4.5.3. Reset

You can source the reset to the PHY Lite for Parallel Interfaces IP from an external pinor from the core. If you source the reset from an external pin, you must configure theI/O standard of the reset signal in the .qsf file with the following command:

set_location_asignment <PIN_NUMBER> -to <signal_name>

4.5.4. Constraining Multiple PHY Lite for Parallel Interfaces to One I/OBank

You can instantiate multiple PHY Lite for Parallel Interfaces Intel FPGA IPs within anI/O column. To constrain groups from separate PHY Lite for Parallel Interfaces IPinstances into the same I/O bank, the instances must share the same reference clockand reset sources, the same external memory frequencies and the same voltagesettings.

Related Information


• KDB link: Error(14566): The Fitter cannot place 1 periphery component(s) due toconflicts with existing constraints (1 PHYLITE_GROUP(s)).


If you are using the dynamic reconfiguration feature, all interfaces of the ExternalMemory Interfaces and PHY Lite for Parallel Interfaces IP cores in the same I/Ocolumn must share the reset signal. Multiple IP cores requiring Avalon core accessrequire daisy chain connectivity.

Related Information

• Daisy Chain on page 111Describes the daisy chain connectivity

• KDB link: Why is the read data value incorrect for the DQS input delay when usingthe Dynamic Reconfiguration mode in the Intel® Arria® 10 PHYLite IP?

4.5.6. Timing

The Intel Quartus Prime software generates the required timing constraints to analyzethe timing of the PHY Lite for Parallel Interfaces IP on the all Intel FPGA devices.




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4.5.6.1. Timing Components

Table 86. Timing Components



Read Path MemoryDevice

DQ CaptureRegister

Source synchronous timing paths—paths whereclock and data signals are passed from thetransmitting devices to the receiving devices.Optionally calibrated paths—paths with delayelements that are dynamically reconfigurable toachieve timing closure, especially at higherfrequency, and to maximize the timing margins.You can calibrate these paths by implementingan algorithm and turning on the optionaldynamic reconfiguration feature. An example ofthe calibrated path is the FPGA to memorydevice write path, in which you can dynamicallyreconfigure the delay elements to, for instance,compensate the skew due to process voltagetemperature variation.


Write Path FPGADQ/DQS

MemoryDevice

Internal FPGA Core to PHYLite forParallel

Interfaces IPPath

CoreRegisters

Write FIFO The internal FPGA paths are paths in the FPGAfabric. The Timing Analyzer reports thecorresponding timing margins.

Internal FPGA PHY Lite forParallel

Interfaces IPto Core

Read FIFO Core Registers

4.5.6.2. Timing Constraints and Files

To successfully constrain the timing for PHY Lite for Parallel Interfaces IP, the IPgenerates a set of timing files. You can locate these timing files in the<variation_name> directory:

• <variation_name> .sdc

• <variation_name> _ip_parameters.tcl

• <variation_name> _pin_map.tcl


• <variation_name>_report_timing.tcl


4.5.6.2.1. <variation_name>.sdc

You can find the location of the <variation_name>.sdc file in the .qip or .qsys,which is generated during the IP generation. The <variation_name> .sdc allows theFitter to optimize timing margins with timing driven compilation and allows the TimingAnalyzer to analyze the timing of your design.

(16) Can be optionally calibrated by using dynamic reconfiguration.




146


The IP uses <variation_name>.sdc for the following operations:

• Creating clocks on PLL inputs

• Creating generated clocks

• Calling derive_clock_uncertainty

• Creating set_output_delay and set_input_delay constraints to analyze thetiming of the read and write paths

4.5.6.2.2. <variation_name>_parameter.tcl

The <variation_name>_parameters.tcl file is a script that lists the following PHYLite for Parallel Interfaces IP parameters used in the .sdc file and report timingscripts:

• Jitter

• Simultaneous switching noise

• Calibration uncertainties

4.5.6.2.3. <variation_name>_ip_parameters.tcl

The <variation_name>_ip_parameters.tcl file lists the PHY Lite for ParallelInterfaces IP parameters and is read by the <variation_name>.sdc.

4.5.6.2.4. <variation_name>_pin_map.tcl

The <variation_name>_pin_map.tcl is a TCL library of functions and proceduresthat <variation_name>.sdc uses.

4.5.6.2.5. <variation_name>_report_timing.tcl

The <variation_name>_report_timing.tcl file is a script that contains timinganalysis flow and reports the timing slack for your variation. This script runsautomatically during calibration (during static timing analysis) by sourcing thefollowing files:

• <variation_name>_ip_parameters.tcl


• <variation_name>_pin_map.tcl


You can also run <variation_name>_report_timing.tcl with the Report DDRfunction in the Timing Analyzer. This script runs for every instance of the samevariation.

Note: You can only use the Report DDR function if you enable the dynamic reconfigurationfeature.

4.5.6.2.6. <variation_name>_report_timing_core.tcl

The <variation_name>_report_timing_core.tcl file is a script that<variation_name>_report_timing.tcl uses to calculate the timing slack foryour variation. <variation_name>_report_timing_core.tcl runs automaticallyduring compilation.




147


4.5.6.3. Timing Analysis

Table 87. Timing AnalysisThis table lists the timing analysis performed in the I/O and FPGA for the PHY Lite for Parallel Interfaces IP.


I/O The PHY Lite for Parallel Interfaces IP generation creates the appropriate generated clock settings for theread strobe on the read path and the write strobe of the write path, according to their strobe type(singled-ended, complementary, or differential) and their interface type (SDR or DDR) in the followingformat:• Clock name for read strobe—<pin_name>_IN.• Clock name for the write path—<pin_name> for positive strobe.• Clock name for the write path—<pin_name>_neg for negative strobe.The set_false_path, set_input_delay and set_output_delay constraints are also generated toensure proper timing analysis of the PHY Lite for Parallel Interfaces IP.

FPGA The PHY Lite for Parallel Interfaces IP generation creates the clock settings for the user core clock and theperiphery clock in the following formats:• user core clock—<variation_name>_usr_clk

• periphery clock— <variation_name>_phy_clk*The user core clock is for user core logic and the periphery clock is the clock for the PHY Lite for ParallelInterfaces IP periphery hardware. With these clock settings, the Timing Analyzer analyzes the timing ofthis IP interface transfer and within core transfer correctly.

4.5.6.4. Timing Closure Guidelines

4.5.6.4.1. Timing Closure: Dynamic Reconfiguration

You can dynamically reconfigure the delay elements in the I/O to optimize process,voltage, temperature variations by implementing a calibration algorithm that modifiesthe input and output delays.

Related Information


4.5.6.4.2. Timing Closure: Input Strobe Setup and Hold Delay Constraints

The Input Strobe Setup Delay Constraint and Input Strobe Hold DelayConstraint parameters ensure that an input to the FPGA from the an external devicemeets the internal FPGA setup and hold time requirements. The value of theseconstraints are calculated from various timing parameters such as setup and holdtiming of the external device, board trace delay and clock skew.

The following figure shows the considerations required to determine the Input StrobeSetup Delay Constraint and Input Strobe Hold Delay Constraint values. Theexternal device sends data and clock to the FPGA through interconnect on the board.The FPGA uses the clock signal from the external device to latch input data to theFPGA. The maximum and minimum values of the output clock TCO are values availablein the external device data sheet.




148


Figure 68. Input Strobe Setup and Hold Delay Constraints Considerations

External Device

Data

ClockPLL

PHY Litefor Parallel Interface

Intel FPGA IP

FPGA

tCO

Data input to FPGA


Input clock to FPGA


Input clock

The following is the derivation for Input Strobe Setup Delay Constraint and InputStrobe Hold Delay Constraint:

Input strobe setup delay constraint = Maximum board skew + maximum TCO

Input strobe hold delay constraint = Minimum board skew + minimum TCO



maximum TCO = DQS to DQ skew (tDQSQ)

minimum TCO = Data hold skew (tQHS)

Figure 69. Input Data Cycle Timing Diagram

DQ_skew_maxDQ_skew_min

tCL

tCH

DQ_skew_min DQ_skew_max

tDQSQ

t QHtQHS

Data valid window

tCL = Clock cycle low

tCH = Clock cycle hightDQSQ = DQS-DQ skew

t QH = DQ-DQS holdtQHS = Data hold skew

The following is an example of Input Strobe Setup Delay Constraint and InputStrobe Hold Delay Constraint calculations with:



• Maximum TCO = 0.6 ns

• Minimum TCO = -0.6 ns




149


Input Strobe Setup Delay Constraint = 0.03 + 0.6= 0.63 ns

Input Strobe Hold Delay Constraint = -0.03 + (-0.6) = -0.63 ns

Insert these values into the Input Strobe Setup Delay Constraint and InputStrobe Hold Delay Constraint parameters and run timing analysis with the TimingAnalyzer tool. The following is an example of delay result from the Timing Analyzertool.

Figure 70. Example of Input Strobe Delay Value from Timing Analyzer

iEXT=Input Strobe Delay Constraint + (0.5*Inter Symbol Interference of Read Channel)

4.5.6.4.3. Timing Closure: Output Strobe Setup and Hold Delay Constraints

The Output Strobe Setup Delay Constraint and Output Strobe Hold DelayConstraint ensure that the data output from the FPGA to the external device meetsthe setup and hold requirements of the external device. The value of these constraintsare calculated from various timing parameters such as setup and hold timing of theexternal device, board trace delay and clock skew.

The following figure shows the considerations required to determine the OutputStrobe Setup Delay Constraint and Output Strobe Hold Delay Constraintvalues. These constraints are depending on the clock and data traces, and setup andhold requirements of the external device. With system-centric delays, you can obtainthe setup and hold requirements, clock delay, and data trace delay values for theexternal device through the device data sheet.

Figure 71. Output Strobe Setup and Hold Delay Constraints Considerations

Data

ClockPLL

PHY Lite for Parallel Interface Intel FPGA IP

FPGA

Data output to external device


Output clock to external device


Input clock

External Device

Data

Clock

(tSU ,tH)

The following is the derivation for Output Strobe Setup Delay Constraint andOutput Strobe Hold Delay Constraint:

Output strobe setup delay constraint = Maximum board skew + maximum tSU




150


Output strobe hold delay constraint = Minimum board skew + minimum tH



maximum tSU = clock setup time

minimum tH = clock hold time

Figure 72. DDR Output Cycle Timing Diagram

Hold marginSU margin

tSUdq

tSUdq

DQ bit time

The following is an example of Output Strobe Setup Delay Constraint and OutputStrobe Hold Delay Constraint calculations with:



• Maximum tSU = 0.75 ns

• Minimum tH = 0.75 ns

Output Strobe Setup Delay Constraint = 0.03 + 0.75= 0.78 ns

Output Strobe Hold Delay Constraint = -0.03 - 0.75 = -0.78 ns

Insert these values into the Output Strobe Setup Delay Constraint and OutputStrobe Hold Delay Constraint parameters and run timing analysis with the TimingAnalyzer tool. The following is an example of delay result from the Timing Analyzertool.

Figure 73. Example of Output Strobe Delay Value from Timing Analyzer

oEXT= Output Strobe Setup delay constraint + (0.5 * Inter Symbol Interference of the Write Channel)




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4.5.6.4.4. Timing Closure: Non Edge-Aligned Input Data

If the input data is not edge-aligned, use the following equation to calculate the newInput Strobe Setup Delay Constraint and Input Strobe Hold Delay Constraintvalues:

New Input Strobe Setup Delay Constraint Value = Clock to data skew - InputStrobe Phase Shift (nanosecond)

New Input Strobe Hold Delay Constraint Value = Clock to data skew + InputStrobe Phase Shift (nanosecond)

For example, if the memory speed is 800 MHz and the clock to data skew value is 0.1with input data phase shift of 90°:

New Input Strobe Setup Delay Constraint value = 0.1-1.25*(90/360) =-0.2125ns.

New Input Strobe Hold Delay Constraint value = 0.1 + 1.25*(90/360) = 0.4125ns

Important: Ensure that you make the changes in the Input Strobe Setup Delay Constraint andInput Strobe Hold Delay Constraint parameters.

4.5.6.4.5. I/O Timing Violation

It can be difficult to achieve timing closure for I/O paths at high frequency. Use thedynamic reconfiguration feature to calibrate the I/O path.

Related Information

Dynamic Reconfiguration on page 111For more information about using the dynamic reconfiguration feature to calibratethe I/O path

4.5.6.4.6. Internal FPGA Path Timing Violation

If timing violations are reported at the internal FPGA paths (such as<instance_name>_usr_clk or <instance_name>_phy_clk_*), consider thefollowing guidelines:

If setup time violation is reported, lower the clock rate of the user logic from full-rateto half-rate, or from half-rate to quarter-rate. This reduces the frequency requirementof the IP core-to-core data transfer.

If hold time violation is observed, you may increase hold uncertainty value to equal orhigher than the violation amount in the .sdc file. This will provide a more stringentconstraint during design fitting. Following is an example to increase the holduncertainty.

If $::quartus(nameofexecutable) != “quartus_sta”

set_clock_uncertainty -from [<instance_name>_phy_clk_*] -to [<instance_name>_phy_clk_*] -hold 0.3 -add

set_clock_uncertainty -from [<instance_name>_usr_clk] -to [<instance_name>_usr_clk] -hold 0.3 -add




152


However, increasing the hold uncertainty value may cause setup timing violation atslow corner.

4.6. Design Example

The PHY Lite for Parallel Interfaces IP is able to generate a design example thatmatches the same configuration chosen for the IP. The design example is a simpledesign that does not target any specific application; however you can use the designexample as a reference on how to instantiate the IP and what behavior to expect in asimulation.





There are two variants of design example available for PHY Lite for Parallel InterfacesIP:

• Variant without dynamic reconfiguration design example

• Variant with dynamic reconfiguration design example

Table 88. PHY Lite for Parallel Interfaces IP Design Example Variants


Dynamic Reconfiguration OFF ed_synth.qsys (synthesisonly)

Consists of configurable PHY Lite forParallel Interfaces IP instance.


Consists of sim_ctrl, agent, addr/cmdand PHY Lite for Parallel Interfaces IPinstances.Perform read and write transactionverification.

ON ed_synth.qsys (synthesisonly)

Consists of IOAUX and PHY Lite forParallel Interfaces IP instances.You need to instantiate NIOS andAVL_Controller manually or createuser logic to perform addresstranslation.

phylite_debug_kit.qsys(synthesis only)

Consists of NIOS, AVL_Controller, APIfunctions, IOAUX and PHY Lite forParallel Interfaces IP instances.A recommended example design toperform dynamic reconfiguration.This design example does notsupport simulation.


Consists of sim_ctrl, agent, addr/cmd, cfg_ctrl, avl_ctrl and PHY Litefor Parallel Interfaces IP coreinstances.

continued...




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This design example demonstratesdynamic reconfiguration and usesFSM to perform calibration.


When the Enable dynamic reconfiguration option is not selected, Intel QuartusPrime software generates a design example of PHY Lite for Parallel Interfaces IPwithout a dynamic reconfiguration module.

This design example consists of simulation and synthesis design files.

4.6.1.1.1. Generate the Hardware Design Example

The make_qii_design.tcl generates a synthesizable hardware design examplealong with a Quartus project, ready for compilation.





This script generates a qii directory containing a project called ed_synth.qpf. Youcan open and compile this project with the Intel Quartus Prime software.


The make_sim_design.tcl generates a simulation design example along with tool-specific scripts to compile and elaborate the necessary files.





This script generates a sim directory containing one subdirectory for each supportedsimulation tools. Each subdirectory contains the specific scripts to run simulation withthe corresponding tool.

The simulation design example provides a generic example of the core and I/Oconnectivity for your IP configuration. Functionally, the simulation iterates over eachgroup in your configured IP and performs basic reads/writes to an associated agent(one per group) in the testbench. A simple one group PHY Lite for Parallel InterfacesIP instantiation in the testbench is used for basic address and command outputs to theagent. A side bus between the sim_ctrl and the agents is used to check that thereads and writes are valid.




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Figure 74. High-Level View of the Simulation Design Example with One GroupSide read/write command


DRAM clockWrite commandRead commandAgent select

data

strobedata

sim_ctrl

DRAM clock

Latency Delays


PHY Lite DUT

PHY Lite ADDR/CMD


Read/Write command

Core clockRead/Write

enable




When you select the Use dynamic reconfiguration option and click GenerateExample Design, Intel Quartus Prime software generates two design examples:

• Dynamic reconfiguration with debug kit design example.

• Dynamic reconfiguration with configuration control module.

4.6.1.2.1. Dynamic Reconfiguration with Debug Kit

This design example is a simulation design example that is capable to performdynamic calibration for PHY Lite for Parallel Interfaces IP in Intel Arria 10 and IntelCyclone 10 GX devices.

The design example includes:

• A fully configurable PHY Lite for Parallel Interfaces IP

• An Avalon controller to perform address translation

• A NIOS II processor to perform dynamic calibration for PHY Lite for ParallelInterfaces IP

• A set of application program interface (API) to configure delay chains for PHY Litefor Parallel Interfaces IP

Figure 75. Dynamic Reconfiguration with Debug Kit Design Example

Avalon Controller Bus

Avalon Controller Bus

PHY Lite for Parallel Interfaces DUTAVL_CTRLNIOS II





155


Table 89. Dynamic Reconfiguration with Debug Kit Design Example Generated FilesThe example design folders are named differently in Intel Arria 10 and Intel Cyclone 10 GX devices.

• For Intel Arria 10, the example design folder is named as phylite_0_example design.

• For Intel Cyclone 10 GX, the example design folder is named as phylite_c10gx_0_example_design.

Example Design Files Description

<example_design_folder>/readme.txt This file provide simple instructions to generate and use theexample design.

<example_design_folder>/hello_world.c This is the main test program.

<example_design_folder>/phylite_debug_kit.qsys

This is the system design file.

<example_design_folder>/phylite_dynamic_reconfigurations.c

This file contains the set of APIs use in the test program.

<example_design_folder>/phylite_dynamic_reconfiguration.h

This is the header file for the APIs.

<example_design_folder>/phylite_niosii_bridge.v<example_design_folder>/phylite_niosii_bridge_hw.tcl

This is an interconnect module between PHY Lite for ParallelInterfaces IP and NIOS II processor.

<example_design_folder>/issp.tcl This is the In-System Source and Probes module. Use thisfile to reset the system and to probe the status of theinterface_locked signal and dynamic calibration donestatus from NIOS II processor.

Table 90. API Functions in Dynamic Reconfiguration Debug Kit Design Example

API Function Argument Return Value Description

hw_get_num_groups ID Integer Read fromAVL_CTRL_REG_NUM_GROUPS registerfor the specified ID.

hw_get_group_info ID, GROUP_NUM 16'h0000,num_lanes[7:0],num_pins[7:0]

Read from AVL_CTRL_REG_GROUP_INFO register for the specified ID andgroup number.The return values are the number oflanes and number of pins available forthe specified ID and group number.

hw_get_num_lanes ID, GROUP_NUM Integer Read from the AVL_CTRL_REG_GROUP_INFO register for the specified ID andgroup number.The return values are the number oflanes available for the specified ID andgroup number.

hw_get_num_pins ID, GROUP_NUM Integer Read from the AVL_CTRL_REG_GROUP_INFO register for the specified ID andgroup number.The return values are the number ofpins available for the specified ID andgroup number.

hw_get_input_delay ID, GROUP_NUM,PIN_NUM, CSR

Integer Read from the AVL_CTRL_REG_IDELAYregister for the specified ID, groupnumber, and pin ID.Specified CSR to:

continued...




156



• 0 to read from Avalon Controllerregister

• 1 to read from CSR register

hw_get_output_delay ID, GROUP_NUM,PIN_NUM, CSR

Integer Read from the AVL_CTRL_REG_ODELAYregister for the specified ID, groupnumber and pin number.Specified CSR to:• 0 to read from Avalon Controller

register• 1 to read from CSR register

hw_get_strobe_input_delay ID, GROUP_NUM,PIN_NUM, CSR

Integer Read from theAVL_CTRL_REG_DQS_DELAY delayregister for the specified ID, groupnumber and pin number.Specified CSR to:• 0 to read from Avalon Controller


hw_get_strobe_enable_delay ID, GROUP_NUM,PIN_NUM, CSR

Integer Read from theAVL_CTRL_REG_DQS_EN_DELAYregister for the specified ID, groupnumber and pin number.Specified CSR to:• 0 to read from Avalon Controller


hw_get_strobe_enable_phase ID, GROUP_NUM,PIN_NUM, CSR

Integer Read from theAVL_CTRL_REG_DQS_EN_PHASE_SHIFTregister for the specified ID, groupnumber and pin number.Specified CSR to:• 0 to read from Avalon Controller


hw_get_read_valid_enable_delay

ID, GROUP_NUM,PIN_NUM, CSR

Integer Read from theAVL_CTRL_REG_RD_VALID_DELAYregister for the specified ID, groupnumber and pin number.Specified CSR to:• 0 to read from Avalon Controller


hw_set_input_delay ID, GROUP_NUM,PIN_NUM, inputdelay value (integer)

— Write to AVL_CTRL_REG_IDELAY registerfor the specified ID, group number andpin number.Refer to the Control RegistersDescription topic for valid value range.

hw_set_output_delay ID, GROUP_NUM,PIN_NUM, outputdelay value (integer)

— Write to AVL_CTRL_REG_ODELAYregister for the specified ID, groupnumber and pin number.Refer to the Control RegistersDescription topic for valid value range.

continued...




157



hw_set_strobe_input_delay ID, GROUP_NUM,PIN_NUM, strobeinput delay value(integer)

— Write to AVL_CTRL_REG_DQS_DELAYregister for the specified ID, groupnumber and pin number.Refer to the Control RegistersDescription topic for valid value range.

hw_set_strobe_enable_delay ID, GROUP_NUM,PIN_NUM, strobeenable delay value(integer)

— Write toAVL_CTRL_REG_DQS_EN_DELAYregister for the specified ID, groupnumber and pin number.Refer to the Control RegistersDescription topic for valid value range.

hw_set_strobe_enable_phase ID, GROUP_NUM,PIN_NUM, strobeenable phase value(integer)

— Write toAVL_CTRL_REG_DQS_EN_PHASE_SHIFTregister for the specified ID, groupnumber and pin number.Refer to the Control RegistersDescription topic for valid value range.

hw_set_read_valid_enable_delay

ID, GROUP_NUM,PIN_NUM, read validenable delay value(integer)

— Write toAVL_CTRL_REG_RD_VALID_DELAYregister for the specified ID, groupnumber and pin number.Refer to the Control RegistersDescription topic for valid value range.

Related Information

Control Registers Description on page 119




158


Avalon Controller

The example design provides an Avalon controller to simplify the access to thedynamic reconfiguration registers of an interface. The Avalon controller is useful whenthere are multiple groups or instantiation of the PHY Lite for Parallel Interfaces IP. Asingle controller can support multiple interfaces in an I/O column.

Figure 76. Avalon Controller

Avalon Controller

Avalon Memory-Mapped Interface Input(from user logic)

Avalon Memory-Mapped Interface Output(to PHY Lite instance daisy chain)

The input interface is as follows:

avl_in_address[31:0] =8'h00,interface_id[3:0],grp[4:0],pin[5:0],csr[0],register[7:0]

Note: There is no look-up stage here. The Avalon controller automatically looks up andcaches all the necessary data.

Table 91. Avalon Controller RegistersThis table lists the available registers in the Avalon controller. For more information, refer to the ControlRegisters Description topic.

Register[7:0]

Register Name Pin[5:0]

Csr[0] RegisterAccessType

Data onavl_read

data /writedat

a

Description

8'h00 AVL_CTRL_REG_NUM_GROUPS 0 0: Access toAvalon

register.

Avalonregister:

ROCSR

register:N/A

24'h000000,num_grps[7:

0]

Number of groupswithin an interface.

8'h01 AVL_CTRL_REG_GROUP_INFO 0 0: Access toAvalon

register.

Avalonregister:

ROCSR

register:N/A

16'h0000,num_lanes[7:0],num_pins[7:0]

Number of pins withina group.

8'h02 AVL_CTRL_REG_IDELAY 0-47 0: Access toAvalon

register.

Avalonregister:

RWCSR

register:N/A

23'h000000,dq_delay[8:0]

Pin input delay. Usethis register to set pin

PVT compensatedinput delay.

8'h03 AVL_CTRL_REG_ODELAY 0-47 0: Access toAvalon

register.

Avalonregister:

RW

19'h00000,output_delay[1

2:0]

Pin output delay. Usethis register to read

and set the pin outputdelay.

continued...




159


Register[7:0]

Register Name Pin[5:0]

Csr[0] RegisterAccessType

Data onavl_read

data /writedat

a

Description

1: Access toCSR

register.Only read

operation isallowed.

CSRregister:

RO

8'h04 AVL_CTRL_REG_DQS_DELAY 0: DQSA

1: DQSB

(17)

0: Access toAvalon

register.

Avalonregister:

RWCSR

register:N/A

22'h000000,dqs_delay[9:

0]

Strobe input delay ofa pin. Use this

register to set thestrobe PVT

compensated inputdelay.

8'h05 AVL_CTRL_REG_DQS_EN_DELAY 0 0: Access toAvalon

register.1: Access to

CSRregister.

Only readoperation is

allowed.

Avalonregister:

RWCSR

register:RO

26'h0000000,dqs_en_delay[5:0]

Strobe enable inputdelay of a pin. Use

this register to set thestrobe enable delay.

8'h06 AVL_CTRL_REG_DQS_EN_PHASE_SHIFT

0: DQSA

1: DQSB

(17)

0: Access toAvalon


CSRregister.


allowed.

Avalonregister:

RWCSR

register:RO

19'h00000,phase[12:0]

Strobe enable inputphase of a pin. Use

this register to set thestrobe enable phase.

8'h07 AVL_CTRL_REG_RD_VALID_DELAY 0 0: Access toAvalon


CSRregister.


allowed.

Avalonregister:

RWCSR

register:RO

25'h0000000,rd_vld_delay[6:0]

Read val to set theread valid delay.

Note: The example Avalon controller does not currently support VREF reconfiguration.

Related Information


• Control Registers Description on page 119

Example of Accessing Dynamic Reconfiguration Control Registers using Avalon Controller

This example shows the steps to access the dynamic reconfiguration control registersusing Avalon controller with the following PHY Lite for Parallel Interfaces IP settings:

(17) Strobe logic B is only used by the negative pin of complementary strobes




160


• Number of groups: 1. The group index is automatically set to 0x00.

• Interface ID: 0x04

• Pin width: 5

• Strobe configuration: Differential

Below is the Avalon address value to read AVL_CTRL_REG_DQS_DELAY Avalonregister (strobe pin delay) at offset 0x04:

Note: The PHY Lite for Parallel Interfaces IP fixes the strobe pin as pin[0].

avl_in_address[31:0] = 8'h00,interface_id[3:0],grp[4:0],pin[5:0],csr[0],register[7:0] avl_in_address[31:0] = 8'h00,0x04,0x00,0x00,0x00,0x04

Below is the Avalon address value to read AVL_CTRL_REG_IDELAY Avalon register(input data pin) at offset 0x02 for data pin 4. The pin number for data pin 4 is 0x06:

avl_in_address[31:0] = 8'h00,interface_id[3:0],grp[4:0],pin[5:0],csr[0],register[7:0] avl_in_address[31:0] = 8'h00,0x04,0x00,0x06,0x00,0x02

Generate the Dynamic Reconfiguration with Debug Kit Design Example

1. In Intel Quartus Prime, select File New Project Wizard to create a newproject directory and specify phylite_debug_kit as the project name.

2. Select device and instantiate PHY Lite for Parallel Interfaces IP and turn on theUse dynamic reconfiguration option.

3. Click Generate Example Design.

4. In your example design directory, open the phylite_debug_kit.qsys file andclick Generate HDL to generate the .qsys design example files.

5. In Intel Quartus Prime, right click on the design example project and selectSettings.

6. In Files tab, browse to the <generated design example folder/phylite_debug_kit> and add in phylite_debug_kit.qip file into yourproject.

7. Select Start Compilation to compile the design example project.

8. In Intel Quartus Prime, select Tools Nios II Software Build Tool for Eclipse.Create a new workspace when prompted.

9. In Nios II - Eclipse software, select File New Nios II Application and BSPfrom Template.

10. In the Nios II Application and BSP from Template window, selectphylite_debug_kit_sopcinfo file in SOPC Information File nameparameter to load the CPU settings.

11. Specify a project name in the Project name parameter.

12. Select Hello World for the Project Template.

13. Click Finish to generate the project.




161


14. Copy hello_world.c, phylite_dynamic_reconfiguration.c, andphylite_dynamic_reconfiguration.h files from the generated exampledesign folder into your Eclipse project folder. You can refresh the Nios II Eclipsewindow by pressing F5 to make sure these files are added into your Eclipseproject.

15. In the Nios II Eclipse window, click Project Build Project to generate .elffile.

16. Run the following command in Nios II Command Shell to convert the .elf fileinto .hex.

elf2hex --input=<elf_filename>.elf --base=0x40000 --end=0x7ffff --width=32 --output=phylite_debug_kit_inst_mem.hex

17. Copy and add the phylite_debug_kit_inst_mem.hex file into the ed_synthproject folder.

18. Add the following command in the ed_synth.qsf to include thephylite_debug_kit_inst_mem.hex in your project compilation.

set_global_assignment -name MISC_FILEphylite_debug_kit_inst_mem.hex

19. Compile the ed_synth project file to generate .sof file to run the exampledesign on your hardware.

Run the Dynamic Reconfiguration with Debug Kit Design Example

1. Download the phylite_debug_kit.sof file into the FPGA.

2. From the Quartus installation directory, double click on the Nios II CommandShell.bat to launch the Intel Nios® II command shell (command shell A). Repeatthe same step to launch a second command shell (command shell B).

3. In command shell B, use the following command to run Nios II terminalapplication for result printouts.

nios2-terminal --cable=<jtag_cable_num>

4. Use the following command in command shell A to reset the system and start thedynamic reconfiguration application.

quartus_stp -t issp.tcl phylite_debug_kit.qpf

4.6.1.2.2. Dynamic Reconfiguration Using Finite State Machine

This design example provides you a synthesizable system capable to perform dynamiccalibration for PHY Lite for Parallel Interfaces IP core in Intel Arria 10 and Intel Cyclone10 GX devices.

Features

• Perform dynamic reconfiguration using Avalon controller

• Read and write transactions monitoring

• Delay values monitoring




162


Software Requirements

• Intel Quartus Prime software

• Active-HDL, ModelSim - Intel FPGA Edition, NCsim or VCS Simulator

Functional Description

This design example introduces the cfg_ctrl and avl_ctrl blocks, which work withthe sim_ctrl module to demonstrate the basic functionality of the PHY Lite forParallel Interfaces IPs Avalon memory-mapped based reconfiguration. The agent isalso modified to insert delays on the data and clocks, which the new modules willcompensate for.

NOTE: The cfg_ctrl module performs a simplistic reconfiguration of the interfacethat stops at the first working delay values. The design example only supportsimulation. A robust calibration algorithm should sweep over the entire valid range ofdelays to choose the correct value for the application.

Figure 77. Dynamic Reconfiguration Using Finite State Machine Design ExampleThis figure shows a high-level view of the simulation design example with one group.

Side read/write command


DRAM clock

Write commandRead commandAgent select

strobeData

sim_ctrl

DRAM clock

Latency Delays


PHY Lite DUT

PHY Lite ADDR/CMD


Read/Write command

Core clock

Read/Write enable



cfg_ctrl avl_ctrlAvalon Memoy-mapped

Bus

Dynamic Reconfiguration Only

Reconfiguration Flow Control

Avalon Memory-mapped Bus

ref_clk_gen reset_gen

ref_clk

ref_clk

reset_n

reset_n

ref_clk

Driver

Strobe

Core clock

Lock

DataLock

Data

Table 92. Design Components Description


ref_clk_gen Generates clock to reset_gen, PHY Lite for Parallel Interfaces ADDR/CMD(ref_clk), and PHY Lite for Parallel Interfaces DUT (ref_clk) blocks.

reset_gen Generates reset to PHY Lite for Parallel Interfaces ADDR/CMD and PHY Lite forParallel Interfaces DUT blocks.

sim_ctrl • Generates read/write commands to PHY Lite for Parallel Interfaces ADDR/CMDblock.

• Generates side read/write commands and data to Agent block.• Generates strobe and data to Driver block.

continued...




163



Driver Generates strobe and data for each group and to PHY Lite for ParallelInterfaces_DUT block.

PHY Lite for Parallel InterfacesADDR/CMD

Passing read/write commands and command clock from sim_ctrl to Agent.

Agent FIFO to store data from PHY Lite for Parallel Interfaces DUT and side read/writedata from sim_ctrl block.

cfg_ctrl This is configuration control block which performs read and write delay calibrationbefore test begin.The calibration results is passed to the PHY Lite for Parallel Interfaces DUTthrough Avalon Controller.Contains 4 FSMs:1. Main FSM – cfg_ctrl state2. Write Strobe FSM – Calibration state for Output Strobe3. Read Strobe FSM – Calibration state for Input Strobe4. Read Enable FSM – Calibration state for Strobe Enable and Input Data

avl_ctrl The Avalon controller is used to perform address translation to store delaysettings from the calibration done by cfg_ctrl block.




164


Figure 78. Design Example Functional Flow

a)

b)

c)

d)

Start

Dynamically reconfigure data group's settings

Function name: reconfigure_grp

Reset cfg_ctrl module


Repeat step b) and c) until pass

Function name: reconfigure_grp_readDynamically reconfigure read strobe setting


Pin Type?

e) Done

a)

b)c)

d)



Repeat step b) and c) until passe) Done

Simulation ends

Simulation ends

Read from Pin Output Delay CSR registerWrite to DUT and read back

If fail, update Pin Output Delay Avalon register

Read from Strobe PVT Compensated Input Delay CSR register

a)

b)c)d) Repeat step b) and c) until passe) Done

Read from Pin Output Delay CSR registerWrite to DUT and read backIf fail, update Pin Output Delay Avalon register

Write to Agent and read backIf fail, update Strobe PVT Compensated Input Delay Avalon register

Write data to Agent and read back to verify data is correct

Output InputBidirectional

Dynamically reconfigure read enable and input data settings

a)b)

e) Get number of data pinf) Write to Agent and read back

g) If fail, update Pin PVT Compensated Input Delay Avalon register

h) Repeat f) and g) until passi) Done

c) If data[0] is mismatched, update Strobe Enable Phase Avalon register

Function name: reconfigure_grp_read_en_and_dataRead from Strobe Enable Phase CSR registerWrite to Agent and read back

d) Repeat step b) and c) until data[0] is matched

Related Information

Avalon Controller on page 159




165


Generate the Dynamic Reconfiguration with Configuration Control Module Design Example

1. In Intel Quartus Prime software, instantiate PHY Lite for Parallel Interfaces IP core.

2. Customize parameter settings per your requirement and turn on the Usedynamic reconfiguration option.

3. Click Generate Example Design. Specify a directory name to generate thedesign example.

4. To generate Verilog or mixed-language simulation files, go to the design exampledirectory and run the following script in Nios II Command Shell.


5. To generate VHDL simulation files, go to the design example directory and run thefollowing script in Nios II Command Shell.


Run the Dynamic Reconfiguration with Configuration Control Design Example

Follow these steps to compile and simulate the design:

1. Change the working directory to <Example Design>\sim\ed_sim\sim\<Simulator>.

2. Run the simulation script for the simulator of your choice. Refer to the table below.

Simulator Working Directory Steps

Modelsim <Example Design>\sim\ed_sim\sim\mentor

a. do msim_setup.tcl

b. ld_debug


d. run -all

VCS <Example Design>\sim\ed_sim\sim\synopsys\vcs

a. sh vcs_setup.sh

VCSMX <Example Design>\sim\ed_sim\sim\synopsys\vcsmx

a. sh vcsmx_setup.sh

NCSim <Example Design>\sim\ed_sim\sim\cadence

a. sh ncsim_setup.sh

Aldec Example Design\sim\ed_sim\sim\aldec

a. do rivierapro_setup.tcl

b. ld_debug


d. run -all




166


Figure 79. Sample of Simulation Output

4.7. Application Specific Design Example

This design example demonstrates the PHY Lite for Parallel Interfaces IPimplementation for a NAND Flash design in Intel Arria 10 devices.

The following figure shows the RTL view of the design example.




167


Figure 80. RTL Viewer for a NAND Flash Simple Design Based on the PHY Lite for ParallelInterfaces IP

Related Information

PHY Lite for Parallel Interfaces Intel Arria 10 FPGA IP Core NAND FLASH DesignExample

4.7.1. Implementation using the PHY Lite for Parallel Interfaces IP

You can configure the PHY Lite for Parallel Interfaces IP to support multiple groups(maximum 48 I/O pins each).

The following lists the possible implementations:

• Instantiates one PHY Lite for Parallel Interfaces IP with two groups

— Bidirectional type for DQ and DQS signals

— Output type for Addr/Cmd signals

Note: Each group in the PHY Lite for Parallel Interfaces IP can have 48 I/Os, and the IPsupports up to 18 groups.




168

https://www.altera.com/content/dam/altera-www/global/en_US/others/literature/ug/nand_flash_example_18_0.qar



Figure 81. General Tab Settings




169


Figure 82. Group 0 settings (Bidirectional type for DQ and DQS)




170


Figure 83. Group 1 settings (Output type for Addr/Cmd)

Related Information

PHY Lite for Parallel Interfaces Intel Arria 10 FPGA IP Core NAND FLASH DesignExample




171




5. PHY Lite for Parallel Interfaces IP Core User GuideDocument Archives

IP versions are the same as the Intel Quartus Prime Design Suite software versions up to v19.1. From IntelQuartus Prime Design Suite software version 19.2 or later, IP cores have a new IP versioning scheme.If an IP core version is not listed, the user guide for the previous IP core version applies.

Intel Quartus PrimeVersion

User Guide

20.3 Intel FPGA PHYLite for Parallel Interfaces IP Core User Guide






17.0 Altera PHYLite for Parallel Interfaces IP Core User Guide





Send Feedback



https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/archives/ug_altera_phylite-20-3.pdf

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/archives/ug_altera_phylite-20-2.pdf

https://www.altera.com/en_US/pdfs/literature/ug/archives/ug_altera_phylite-19-1.pdf





https://www.altera.com/en_US/pdfs/literature/ug/archives/ug-altera-phylite-16.0.pdf







6. Document Revision History for the PHY Lite for ParallelInterfaces IP User Guide

Document Version Intel QuartusPrime Version

Changes

2021.02.04 20.4 • Updated the PHY Lite for Parallel Interfaces Intel Agilex FPGA IPv20.3.0 as follows:— Updated the I/O resource and added support for dynamically

reconfigurable delay chains using Avalon memory-mapped interfacefor Intel Agilex devices in the Features section.

— Updated the Intel Agilex I/O Sub-bank Interconnects section.• Stated that each sub-bank is labeled with ID number to facilitate

pin placement.• Updated figure titles and added ID numbers in the diagrams.

— Updated the Pins Usable as Read Capture Clock / Strobe Pair table.— Updated the maximum frequency for speed grade –2 and –3 in the

PHY Lite for Parallel Interfaces Intel Agilex FPGA IP SupportedInterface Frequency table.

— Added the Dynamic Reconfiguration section.— Updated the PHY Lite for Parallel Interfaces IP Parameter Settings

table.• Updated values for Clock rate of user logic, Use dynamic

reconfiguration, and Pin width.• Added the Pin Placement section.• Removed the Expose termination ports parameter.• Removed the Group <x> Placement Settings section.

— Removed the Termination Signals and Manual Insertion of OCTBlock sections.

— Updated the steps to set RZQ pin locations in the RZQ_GROUPAssignment section.

— Updated the Guidelines: Group Pin Placement section.• Updated the guidelines for group pin placement.• Updated the Pin Index Mapping table.• Added guidelines and example for automatic and manual pin

placement.• Removed the Example of Occupied Data Pins for a Single Group

Using Automatic Pin Placement and Example of Occupied DataPins for a Single Group Using Manual Pin Placement diagrams.

— Added command codes in the Reference Clock section.— Added the Generate the Design Example section. Included Generate

the Simulation Design Example as a sub section.• Updated the Guidelines: Group Pin Placement sections for the following

IPs:— PHY Lite for Parallel Interfaces Intel Stratix 10 FPGA IP— PHY Lite for Parallel Interfaces Intel Arria 10 FPGA IP— PHY Lite for Parallel Interfaces Intel Cyclone 10 GX FPGA IP


Send Feedback








Changes

2020.11.13 20.3 • Updated the figure showing the I/O bank structure to add the pinnaming orientation.

• Repaired multiple broken links and descriptions throughout thedocument.

2020.10.19 20.3 • Added information about PHY Lite for Parallel Interfaces Intel AgilexFPGA IP v20.3.0 support in Intel Agilex devices.

• Restructured the user guide to separate the information into specificdevices.

2020.06.30 20.2 Updated the Intel Stratix 10 I/O Bank Structure figure showing the I/Obank structure:• Added I/O bank structure for Intel Stratix 10 GX 10M device.• For I/O banks figure of other Intel Stratix 10 devices:

— Marked only bank 3A as SDM shared LVDS I/O.— Marked HPS shared LVDS I/Os.— Added 3 V I/O banks 7A, 7B, and 7C.


IP Version Changes

2020.02.24 19.3 19.1 • Added Why is the read data value incorrect for theDQS input delay when using the DynamicReconfiguration mode in the Intel Arria 10 PHYLiteIP? KDB link to the Dynamic Reconfiguration topic.

• Editorial updates for the Output Path — WriteLatency 2 and Input Path Read Latency 7 figures.

• Updated dqs_enable signals in the Input Pathfigure to match signal names in Blocks in Data,Strobe, and Read Enable Paths table.

• Removed redundant signal description foravl_writedata in the Avalon Memory-MappedMaster Interface Signals table.

• Rebranded Avalon-MM to Avalon Memory-MappedInterface.

2019.12.16 19.3 19.1 • Updated note and related information link onusing .sdc file in encrypted IOPLL Intel FPGA IPinstances in the Reference Clock topic.

continued...

6. Document Revision History for the PHY Lite for Parallel Interfaces IP User Guide



174



IP Version Changes

2019.11.07 19.3 19.1 • Added the following topics:— Release Information— Timing Closure: Input Strobe Setup and Hold

Delay Constraints— Timing Closure: Output Strobe Setup and Hold

Delay Constraints• Added KDB link Why does the PHY Lite for Parallel

Interfaces Intel Stratix 10 FPGA IP cannot beassigned to Bank 3A or 3D when using the IntelStratix 10 1ST040* device? to FunctionalDescription chapter.

• Added KDB link Error(14566): The Fitter cannotplace 1 periphery component(s) due to conflictswith existing constraints (1 PHYLITE_GROUP(s)). toConstraining Multiple PHY Lite for Parallel Interfacesto One I/O Bank chapter.

• Added KDB link Warning: Failed to find atominformation in IOPLL SDC: ERROR: Cannot accessENUM_IOPLL_FEEDBACK data of the encryptedatom node 111916. This operation involves anencrypted atom node. Use the BOOL_ENCRYPTEDtest to avoid such nodes and the error. toReference Clock topic.

2019.04.04 19.1 19.1 • Added Can the Intel Arria 10 and Intel Cyclone 10GX I/O PLL have a VCO frequency below theminimum value shown in the device datasheets?KDB link in Clocks, Clock Frequency Relationships,and Parameter Settings sections.

2019.04.01 19.1 19.1 • Added new parameter Reference clock I/Oconfiguration in PHY Lite for Parallel Interfaces IPCore Parameter Settings table.

• Removed information on manual assignment forreference clock I/O standards in the I/O Standardschapter.

2019.01.09 18.1 18.1 Added estimation time for a delay register value tochange in Reconfiguration Features and RegisterAddressing.

2018.09.21 18.1 18.1 • Clarified the definition for full, half, and quartercore clock rate in PHY Lite for Parallel InterfacesSupported Interface Frequency tables.

• Added legend and updated Input Path figure toshow each path and distinguish internal andexternal signals.

• Updated description for data, strobe, and read andstrobe enable paths in Blocks in Data, Strobe, andRead and Strobe Enable Paths table.

• Updated read operation description in ReadOperation Sequence table.

• Updated Input Path Waveform, Output Path - WriteLatency 0, and Output Path - Write Latency 3figures.

• Updated description in Input Path Signals table.• Added a note to rdata_en signal in Input Path

Signals to describe when user should assert thesignal when using PHY Lite for Parallel Interfaces IPas a receiver.

continued...




175



IP Version Changes

• Clarified that only when External Memory Interfacewith Debug Component IP cores exists in the designwith PHY Lite for Parallel Interfaces, the FirstPHYLite Instance in the Avalon Chainparameter should be disabled.

• Added new parameter Fast simulation model inPHY Lite for Parallel Interfaces table.

• Updated RZQ_GROUP Assignment topic with stepsto manually assign user defined RZQ pin location.

• Added the following topics:— Example of Accessing Dynamic Reconfiguration

Control Registers using Parameter Table— Example of Accessing Dynamic Reconfiguration

Control Registers using Avalon Controller• Removed description on supported devices for

tables with information that supports all devices.• Clarified that PHY Lite for Parallel Interfaces in Intel

Arria 10 and Intel Cyclone 10 GX devices do notsupport exposing additional output clocks if theVCO frequency is lower than 600 MHz in PHY Litefor Parallel Interfaces IP Core Parameter Settingstable.

• Added pll_extra_clock[0..3] andpll_locked signals in Clock and Reset InterfaceSignals table.

• Updated Output Path and Input Path blockdiagrams with parameters that impact the internalmodules.

2018.06.06 18.0 18.0 • Removed For Intel Arria 10 and Intel Cyclone 10 GXdevices, this value is for DQS output strobe. ForIntel Stratix 10 devices, this value is for both DQand DQS output strobe. note from Pin Output Delayfeature in Control Register Description table.

2018.05.07 18.0 18.0 • Changed VCCN voltage supply name to VCCIO.• Renamed Addressing section to Reconfiguration

Features and Register Addressing.• Added Control Register Addresses tables for Intel

Stratix 10, Intel Arria 10, and Intel Cyclone 10 GXdevices.

• Added Control Registers Description table for IntelStratix 10, Intel Arria 10, and Intel Cyclone 10 GXdevices.

• Added How can the PHY Lite IP RZQ pin location beassigned? Knowledge Base Link in On-ChipTermination (OCT) section.

• Added First PHYLite Instance in the AvalonChain parameter to the PHY Lite for ParallelInterfaces IP Core Parameter Settings table.

• Made Example Design Avalon Controller section asa sub-section in Dynamic Reconfiguration withDebug Kit Design Example.

• Updated Avalon Controller Registers table withregister descriptions.

• Renamed Pin Output Phase feature to Pin OutputDelay.

• Updated the minimum interface frequencyrecommended for dynamic reconfiguration to 533MHz in the PHY Lite for Parallel Interfaces IP CoreParameter Settings table.

• Updated all IP names as per Intel rebranding.




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Date Version Changes

November 2017 2017.11.30 • Added information about Intel FPGA PHYLite for Parallel Interfaces in IntelStratix 10 and Intel Cyclone 10 GX devices.

• Added note to Reference Clock on page 144 about using cascaded PLL as areference clock in Intel Arria 10 devices and a link to the KDB.

• Rebranded to Intel FPGA PHYLite for Parallel Interfaces IP core.

June 2017 2017.06.16 • Added a note for the I/O Column for Arria 10 Devices figure.• Updated Top-Level Interface diagram.• Updated OCT section.• Updated Guidelines: Group Pin Placement section.• Updated the reference clock source in the Reference Clock section.• Added Reset section.• Added a note on Report DDR function in

"<variation_name>_report_timing.tcl" section.• Updated Altera PHYLite for Parallel Interfaces IP Core Parameter Settings

table.— Removed Use core PLL reference clock connection parameter.— Added description for outclk (Reserved) parameter.— Updated OCT enable size values and description.— Added new parameter: Expose termination ports.

• Updated the description for ref_clk and interface_locked signals in theClock and Reset Interface Signals table.

• Updated the description for data_in and data_io signals in Input PathSignals table.

• Rebranded as Intel.

February 2017 2017.02.24 • Removed 30 and 40 Ohms termination values for SSTL-125, SSTL-135, andSSTL-15 I/O standards.

• Added a footnote to I/O Standards table recommending to use I/O standardsSSTL-15 Class I, SSTL-15 Class II, SSTL-18 Class I, SSTL-18 Class II, 1.2VHSTL Class I, 1.2V HSTL Class II, 1.5V HSTL Class I, 1.5V HSTL Class II,1.8V HSTL Class I, and 1.8V HSTL Class II for interface frequency equal orless than 533 MHz and if input termination required.

• Added a footnote to I/O Standards table recommending to use I/O standardsSSTL-12, SSTL-125, SSTL-135, and SSTL-15 for interface frequency morethan 533 MHz and if input termination required.

October 2016 2016.10.28 • Added OCT section.• Clarified that output terminations can be calibrated and uncalibrated in I/O

Standards table.• Added footnote to clarify that uncalibrated output terminations do not require

RZQ pin in I/O Standard table.• Clarified ONFI device support is for synchronous mode only.• Updated Altera PHYLite for Parallel Interfaces IP Core supported Interface

Frequency table.• Clarified that reference clock using differential I/O standards support LVDS

input buffer only.• Updated I/O standards table with Valid Input Termination values.• Added new guidelines to Group Pin Placement section.• Updated Avalon Address for following features in the Address Map table:

— Pin PVT Compensated Input Delay— Strobe PVT compensated input delay— Strobe enable phase

• Added Altera PHYLite NAND Flash design example in Application SpecificDesign Example section.

• Removed IP Migration for Arria V, Cyclone V, and Stratix V section.

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May 2016 2016.05.02 • Change External memory clock domain to Interface clock domain.• Removed VCO Frequency Multiplication Factor table.• Updated equation to calculate values for Input Strobe Setup Delay

Constraint and Input Strobe Hold Delay Constraint parameters.• Updated Address Map table with values to enable Avalon address and CSR

address.• Added a note to show the location of the Altera PHYLite for Parallel Interfaces

IP core in IP Catalog.• Updated values for OCT enable size parameter.• Added reference link to I/O Standards table in Data configuration

parameter description.• Added VCO clock frequency parameter in Parameter Settings table.• Updated Minimum Read Latency and Maximum Write Latency tables.• Updated PHYLite_delay_calculations.xlsx file.• Added issp.tcl file description in Dynamic Reconfiguration with Debug Kit

Design Example Generated Files table.• Updated steps to generate Dynamic Reconfiguration with Debug Kit design

example.• Added functional description, simulation steps and result to Dynamic

Reconfiguration with Configuration Control Module Design Example.• Added Altera PHYLite for Parallel Interfaces IP Core Document Archives

section.

December 2015 2015.12.11 • Changed Input Path Waveform figure label from "Intrinsic output delay atcurrent in and out rates and frequency" to "Intrinsic input delay at current inand out rates and frequency".

November 2015 2015.11.02 • Added Altera PHYLite for Parallel Interface IP core uses cases.• Clarified the condition for reference clock restriction in Reference Clock

section.• Added description for <variation_name>_parameter.tcl,

<variation_name>_report_timing.tcl, and<variation_name>_report_parameter_core.tcl files intoTiming Constrains and Files section.

• Provided example timing constraint command for increasing hold timeuncertainty value.

• Added footnote to clarified functionality for DQS A and DQS B signals.• Added new parameters in the Altera PHYLite for Parallel Interfaces IP Core

Parameter Settings table:— Copy parameters from another group— Group— OCT enable size— Inter Symbol Interference of the Read Channel— Inter Symbol Interference of the Write Channel— Group <x> Dynamic Reconfiguration Timing Settings

• Added new dynamic reconfiguration with debug kit hardware example design.• Added Write Latencies table in Parameter Settings.• Updated Read Latencies table.• Changed instances of Quartus II to Quartus Prime.

June 2015 2015.06.12 • Updated Avalon Address R/W from 3'h2 to 3'h4 for all features in AddressMap table.

• Added new parameter Use core PLL reference clock connection and Dataconfiguration in Altera PHYLite for Parallel Interfaces IP Core ParameterSettings table.

• Updated values in VCO Frequency Multiplication Factor table.

January 2015 2015.01.28 Updated related information link to Functional Description for External MemoryInterfaces in Arria 10 Devices.

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December, 2014 2014.12.30 • Updated the name of the IP core from Altera PHYLite for Memory to AlteraPHYLite for Parallel Interfaces.

• Updated the maximum clock frequency from 800 MHz to 1333.333 MHz.• Clarified that to achieve timing closure at 800 MHz and above, you must use

dynamic reconfiguration to calibrate the interface.• Added data_out_n/data_io_n signals to the Output Path Signals table.• Added data_in_n/data_io_n signals to the Input Path Signals table.• Updated data_out/data_io and data_in/data_io signals in the Input

Path Signals and Output Path Signals tables.• Updated Parameter Settings table to include Group <x> Timing Settings

information.• Updated Timing section to include Input Strobe Setup Delay Constrain

and Input Strobe Hold Delay Constrain parameters information.

August, 2014 2014.08.18 • Renamed the term megafunction to IP core.• Added information about output path data alignment, input path data

alignment, OCT, I/O standards, placement restrictions, timing, dynamicreconfiguration.

• Added the PHYLite_delay_calculations.xlsx file.• Replaced ALTERA_PHYLite_nand_flash_example_131a10.qar file with

nand_flash_example_14.0a10.qar file.

November, 2013 2013.11.29 Initial release.




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