phyCORE -TriCORE Development Board Hardware Manual · PHYTEC Messtechnik GmbH 2018 L-730e.A2...

A product of a PHYTEC Technology Holding company

phyCORE-TriCORE Development Board

Hardware Manual

Document No.: L-730e.A2

SBC Prod. No.: KSP-0150-B1

CB PCB No.: 2200.1 SOM PCB No.: 4628.0

Edition: December 2018


PHYTEC Messtechnik GmbH 2018 L-730e.A2

Copyrighted products are not explicitly indicated in this manual. The absence of the trademark (, or ®) and copyright (©) symbols does not imply that a product is not protected. Additionally, registered patents and trademarks are similarly not expressly indicated in this manual. The information in this document has been carefully checked and is considered to be entirely reliable. However, PHYTEC Messtechnik GmbH assumes no responsibility for any inaccuracies. PHYTEC Messtechnik GmbH neither gives any guarantee nor accepts any liability whatsoever for consequential damages resulting from the use of this manual or its associated product. PHYTEC Messtechnik GmbH reserves the right to alter the information contained herein without prior notification and accepts no responsibility for any damages that might result. Additionally, PHYTEC Messtechnik GmbH offers no guarantee nor accepts any liability for damages arising from the improper usage or improper installation of the hardware or software. PHYTEC Messtechnik GmbH further reserves the right to alter the layout and/or design of the hardware without prior notification and accepts no liability for doing so. Copyright 2018 PHYTEC Messtechnik GmbH, D-55129 Mainz. Rights - including those of translation, reprint, broadcast, photomechanical or similar reproduction and storage or processing in computer systems, in whole or in part - are reserved. No reproduction may occur without the express written consent from PHYTEC Messtechnik GmbH.

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2nd Edition December 2018

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Contents

PHYTEC Messtechnik GmbH 2018 L-730e.A2 i

List of Figures ................................................................................................... ii List of Tables ................................................................................................... iii Conventions, Abbreviations and Acronyms ............................................................. iv

Preface ......................................................................................................... vii 1 Introduction .............................................................................................. 1

1.1 Hardware Overview ........................................................................................ 1 1.1.1 Features of the phyCORE-TriCORE Development Board ............................... 1 1.1.2 View of the phyCORE-TriCORE Development Board ..................................... 2

2 Accessing the phyCORE-TriCORE Development Board Features................................ 3

2.1 Overview of the phyCORE-TriCORE Development Board Peripherals .......................... 3 2.1.1 Connectors and Pin Header .................................................................. 3 2.1.2 LEDs ................................................................................................ 4 2.1.3 Switches .......................................................................................... 4

3 Jumpers ................................................................................................... 5

4 Functional Components on the phyCORE-TriCORE Development Board ..................... 9

4.1 Power Connector (X1) .................................................................................... 9 4.2 Activating the Bootstrap Loader ...................................................................... 9 4.3 First Serial Interface (Socket P1A) ................................................................... 11 4.4 Second Serial Interface (Socket P1B) ............................................................... 11 4.5 First CAN Interface (Plug P2A) ........................................................................ 12 4.6 Second CAN Interface (Plug P2B) .................................................................... 14 4.7 RJ45 Ethernet Connector (X7) ........................................................................ 16 4.8 User Programmable LED (D5) ......................................................................... 16 4.9 Pin Assignment of the phyCORE, Expansion Bus and Patch Field ............................ 17 4.10 DS2401 Silicon Serial Number ........................................................................ 26 4.11 Pin Header Connector (X10) ........................................................................... 26 4.12 USB Wiggler (X11) ....................................................................................... 27 4.13 LCD Connector ............................................................................................. 27 4.14 Additional chipselect /extCSx on X4................................................................. 29 4.15 Jumper JP39 for /CS to SRAM BANK2 Connection on the phyCORE-TriCORE Development

Board (only for phyCORE-TC179X and TC399) ..................................................... 30 4.16 JTAG PLD Connector (phyCORE-TC1130 ONLY) .................................................... 30 4.17 USB Connector (X12) .................................................................................... 31

4.17.1 OCDS2 connector only for phyCORE-TC179X ............................................ 31 5 Revision History ....................................................................................... 32

Index ............................................................................................................ 33


ii PHYTEC Messtechnik GmbH 2018 L-730e.A2

List of Figures

Figure 1: View of the phyCORE-TriCORE Development Board .............................................. 2

Figure 2: Typical Jumper Pad Numbering Scheme ........................................................... 5

Figure 3: phyCORE-TriCORE Development Board Jumper Locations ..................................... 6

Figure 4: Default Jumper Settings of the phyCORE-TriCORE Development Board for Standard phyCORE-TC1130 ......................................................................................... 7

Figure 5: Default Jumper Settings of the phyCORE-TriCORE Development Board for Standard phyCORE-TC179X ......................................................................................... 7

Figure 6: Default Jumper Settings of the phyCORE-TriCORE Development Board for Standard phyCORE-TC399 .......................................................................................... 8

Figure 7: Connecting the Supply Voltage at X1 ............................................................... 9

Figure 8: Pin Assignment of the DB-9 Socket P1A as First RS-232(Front View) .................... 11

Figure 9: Pin Assignment of the DB-9 Socket P1A as Second RS-232(Front View) ................ 12

Figure 10: Pin Assignment of the DB-9 Plug P2A (CAN Transceiver on phyCORE-TC1130, Front View) ...................................................................................................... 12

Figure 11: Pin Assignment of the DB-9 Plug P2A (CAN Transceiver on Development Board) ..... 13

Figure 12: Pin Assignment of the DB-9 Plug P2A (CAN Transceiver on Development Board with Galvanic Separation) ................................................................................. 14

Figure 13: Pin Assignment of the DB-9 Plug P2B (CAN Transceiver on phyCORE-TC1130, Front View) ...................................................................................................... 14

Figure 14: Pin Assignment of the DB-9 Plug P2B (CAN Transceiver on Development Board) ..... 15

Figure 15: Pin Assignment of the DB-9 Plug P2B (CAN Transceiver on Development Board with Galvanic Separation) ................................................................................. 16

Figure 16: Pin Assignment Scheme of the Expansion Bus ................................................. 17

Figure 17: Pin Assignment Scheme of the Patch Field ...................................................... 18

Figure 18: Connection of the DS2401 Silicon Serial Number ............................................. 26

Contents

PHYTEC Messtechnik GmbH 2018 L-730e.A2 iii

List of Tables

Table 1: Signal Types used in this Manual .....................................................................v

Table 2: Abbreviations and Acronyms used in this Manual ............................................... vi

Table 3: phyCORE-TriCORE Development Board Connectors and Pin Headers ....................... 3

Table 4: phyCORE-TriCORE Development Board LED Description ....................................... 4

Table 5: phyCORE-TriCORE Development Board Switches Description ................................. 4

Table 6: JP12 Configuration of the Boot Button .......................................................... 10

Table 7: JP20, JP21, JP13 Configuration of Boot via RS-232 .......................................... 10

Table 8: Jumper Configuration for the First RS-232 Interface ......................................... 11

Table 9: Jumper Configuration for the Second RS-232 Interface ...................................... 11

Table 10: Jumper Configuration for CAN Plug P2A Using the CAN Transceiver on the phyCORE-TC1130 or phyCORE-TC179X .......................................................................... 12

Table 11: Jumper Configuration for CAN Plug P2A Using the CAN Transceiver on the Development Board .................................................................................... 13

Table 12: Jumper Configuration for CAN Plug P2A Using the CAN Transceiver on the Development Board with Galvanic Separation .................................................. 13

Table 13: Jumper Configuration for CAN Plug P2B Using the CAN Transceiver on the phyCORE-TC1130, phyCORE-TC179X, and phyCORE-TC399 ................................................ 14

Table 14: Jumper Configuration for CAN Plug P2B Using the CAN Transceiver on the Development Board .................................................................................... 15

Table 15: Jumper Configuration for CAN Plug P2B Using the CAN Transceiver on the Development Board with Galvanic Separation .................................................. 15

Table 16: JP2-6, JP10, JP11 Configuration of the Ethernet Interface ................................. 16

Table 17: Pin Assignment for the phyCORE-TC1130, phyCORE-TC179X and Development Board / Expansion Board ........................................................................................ 19

Table 18: JP1 Jumper Configuration for Silicon Serial Number Chip ................................... 26

Table 19: Jumper Configuration for T6963C LCD-Controller .............................................. 27

Table 20: Jumper Configuration for HD61202, HD44780 LCD-Controller ............................. 28

Table 21: LCD Contrast Configuration .......................................................................... 29

Table 22: Truth-table for generating additional chipselect on X4 of the phyCORE-TriCORE Development Board. ................................................................................... 29

Table 23: Additional chipselect jumper settings for JP38 and JP39 ................................... 30

Table 24: Pin assignemt JTAG_PLD connector for phyCORE- TC1130 ................................... 30

Table 25: TC1130 Jumper Configuration for X12 ............................................................ 31

Table 26: TC11796 Jumper Configuration for X12 ........................................................... 31


iv PHYTEC Messtechnik GmbH 2018 L-730e.A2

Conventions, Abbreviations and Acronyms

This hardware manual describes the phyCORE-TriCORE Development Board Single Board Computer (SBC). The manual specifies the phyCORE-TriCORE Development Board's design and function. Precise specifications for the Infideon Semiconductors microcontrollers can be found in the Infideon Data Sheet and Technical Reference Manuals. Conventions The conventions used in this manual are as follows: Signals that are preceded by an "n", "/", or “#”character (e.g.: nRD, /RD, or #RD), or

that have a dash on top of the signal name (e.g.: RD) are designated as active low signals. That is, their active state is when they are driven low, or are driving low.

A "0" indicates a logic zero or low-level signal, while a "1" represents a logic one or high-level signal.

The hex-numbers given for addresses of I2C devices always represent the 7 MSB of the address byte. The correct value of the LSB which depends on the desired command (read (1), or write (0)) must be added to get the complete address byte. E.g. given address in this manual 0x41 => complete address byte = 0x83 to read from the device and 0x82 to write to the device.

Tables which describe jumper settings show the default position in bold, blue text. Text in blue italic indicates a hyperlink within, or external to the document. Click these

links to quickly jump to the applicable URL, part, chapter, table, or figure. Text in bold italic indicates an interaction by the user, which is defined on the screen. Text in Consolas indicates an input by the user, without a premade text or button to

click on. Text in italic indicates proper names of development tools and corresponding controls

(windows, tabs, commands etc.) used within the development tool, no interaction takes place.

White Text on black background shows the result of any user interaction (command, program execution, etc.)

Preface

PHYTEC Messtechnik GmbH 2018 L-730e.A2 v

Types of Signals Different types of signals are brought out at the phyCORE-Connector. The following table lists the abbreviations used to specify the type of a signal.

Signal Type Description Abbr.

Power Supply voltage input PWR_I

Ref-Voltage Reference voltage output REF_O

Input Digital input I

Output Digital output O

IO Bidirectional input/output I/O

OC-Bidir PU Open collector input/output with pull up OC-BI

OC-Output Open collector output without pull up, requires an external pull up

OC

5V Input PD 5 V tolerant input with pull down 5V_PD

USB IO Differential line pairs 90 Ohm USB level bidirectional input/output

USB_I/O

ETHERNET Input

Differential line pairs 100 Ohm Ethernet level input ETH_I

ETHERNET Output

Differential line pairs 100 Ohm Ethernet level output ETH_O

ETHERNET IO Differential line pairs 100 Ohm Ethernet level bidirectional input/output

ETH_I/O

Table 1: Signal Types used in this Manual


vi PHYTEC Messtechnik GmbH 2018 L-730e.A2

Abbreviations and Acronyms Many acronyms and abbreviations are used throughout this manual. Use the table below to navigate unfamiliar terms used in this document.

Abbreviation Definition A/V Audio/Video BSP Board Support Package (Software delivered with the Development Kit

including an operating system (Windows or Linux) pre-installed on the module and Development Tools)

CB Carrier Board, used in reference to the phyCORE-TriCORE Development Board Development Kit Carrier Board

EMB External memory bus EMI Electromagnetic Interference GPI General purpose input GPIO General purpose input and output GPO General purpose output J Solder jumper, these types of jumpers require solder equipment to

remove and place JP Solderless jumper, these types of jumpers can be removed and placed by

hand with no special tools NC Not Connected NM Not Mounted NS Not Specified PCB Printed circuit board PoE Power over Ethernet PoP Package on Package POR Power-on reset RTC Real-time clock SBC Single Board Computer, used in reference to the phyCORE-TriCORE

Development Board SMT Surface mount technology SOM System on Module, used in reference to the phyCORE-TC1130, phyCORE-

TC179X, or phyCORE-TC399 module Sx User button Sx (e.g. S1, S2) used in reference to the available user

buttons or DIP switches on the CB Sx_y Switch y of DIP switch Sx used in reference to the DIP switch on the

carrier board VSTBY SOM standby voltage input

Table 2: Abbreviations and Acronyms used in this Manual

Preface

PHYTEC Messtechnik GmbH 2018 L-730e.A2 vii

Preface

This Hardware Manual only describes the functions of PHYTEC phyCORE-TriCORE Development Board for the phyCORE-TC1130, phyCORE-TC179X, and phyCORE-TC399 modules. The controllers and modules are not described herein. Precise specifications for Infineon’s TC1130, TC179X or TC399 TriCORE microcontroller series controller can be found in the enclosed microcontroller Data Sheet/User's Manual. If software is included, refer to the documentation for this software. OEM Implementation Implementation of an OEM-able SBC subassembly as the "core" of an embedded design allows for an increased focus on hardware peripherals and firmware without expending resources to "re-invent" microcontroller circuitry. Furthermore, much of the value of the SBC lies in its layout and test. Software Support Production-ready Board Support Packages (BSPs) and Design Services for our hardware will further reduce development time and risk and allows for an increased focus on the product expertise.


viii PHYTEC Messtechnik GmbH 2018 L-730e.A2

Ordering Information

Ordering numbers for phyCORE-TriCORE Development Board Development Kit: KSP-0150-Kit: includes phyCORE-TC179X KSP-0150-Kit-C3: includes phyCORE-TC1793 KSP-0200-Kit: includes phyCORE-TC399 KSP-0150-B1: phyCORE-TriCORE Development Board SBC

Product Specific Information and Technical Support

In order to receive product specific information on all future changes and updates, PHYTEC recommends registering at: http://www.phytec.de/de/support/registrierung.html or http://www.phytec.eu/europe/support/registration.html For technical support and additional information concerning your product, please visit the support section of our website which provides product specific information such as errata sheets, application notes, FAQs, etc. http://www.phytec.de/support/faq/faq-.html or http://www.phytec.eu/support/faq/faq-.html

Other Products and Development Support

PHYTEC supports a variety of 8-/16- and 32-bit controllers in two ways:

(1) as the basis for Rapid Development Kits which serve as a reference and evaluation platform

(2) as insert-ready, fully functional OEM modules, which can be embedded directly into the user’s peripheral hardware design.

Take advantage of PHYTEC products to shorten time-to-market, reduce development costs, and avoid substantial design issues and risks. With this new innovative, full system solution, new ideas can be brought to market in the most timely and cost-efficient manner. For more information go to: http://www.phytec.de/support/ueberblick or http://www.phytec.eu/support/ueberblick

http://www.phytec.de/de/support/registrierung.html

http://www.phytec.eu/europe/support/registration.html

http://www.phytec.de/support/faq/faq-.html

http://www.phytec.eu/support/faq/faq-.html

http://www.phytec.de/support/ueberblick

http://www.phytec.eu/support/ueberblick

Preface

PHYTEC Messtechnik GmbH 2018 L-730e.A2 ix

Declaration of Electro Magnetic Conformity of the PHYTEC phyCORE-TriCORE Development Board PHYTEC Single Board Computers (henceforth products) are designed for installation in electrical appliances, as part of custom applications, or as dedicated Evaluation Boards (i.e. for use as a test and prototype platform for hardware/software development) in laboratory environments.

Caution! PHYTEC products lacking protective enclosures are subject to damage by ESD and, therefore, must only be unpacked, handled or operated in environments in which sufficient precautionary measures have been taken in respect to ESD-dangers. It is also necessary that only appropriately trained personnel (such as electricians, technicians, and engineers) handle and/or operate these products. Moreover, PHYTEC products should not be operated without protection circuitry if connections to the product's pin header rows are longer than 3 m. PHYTEC products fulfill the norms of the European Union’s Directive for Electro Magnetic Conformity only in accordance to the descriptions and rules of usage indicated in this hardware manual (particularly in respect to the pin header row connectors, power connector and serial interface to a host-PC). Implementation of PHYTEC products into target devices, as well as user modifications and extensions of PHYTEC products, is subject to renewed establishment of conformity to, and certification of, Electro Magnetic Directives. Users should ensure conformance following any modifications to the products as well as implementation of the products into target systems.


x PHYTEC Messtechnik GmbH 2018 L-730e.A2

Product Change Management and information in this manual on parts populated on the SOM / SBC

When purchasing a PHYTEC SOM / SBC, you will receive, in addition to our HW and SW offerings, free obsolescence maintenance service for the HW we provide.

Our PCM (Product Change Management) Team of developers is continuously processing all incoming PCN's (Product Change Notifications) from vendors and distributors concerning parts which are used in our products.

Possible impacts to the functionality of our products, due to changes of functionality or obsolesce of a certain part, are constantly being evaluated in order to take the right measures when purchasing or within our HW/SW design.

Our general philosophy here is: We never discontinue a product as long as there is demand for it.

Therefore, we have established a set of methods to fulfill our philosophy:

Avoiding strategies

• Avoid changes by evaluating longevity of parts during design phase. • Ensure availability of equivalent second source parts. • Stay in close contact with part vendors to be aware of roadmap strategies. Change management (in case of functional changes):

• Avoid impacts on product functionality by choosing equivalent replacement parts. • Avoid impacts on product functionality by compensating changes through HW redesign

or backward compatible SW maintenance. • Provide early change notifications concerning functional relevant changes of our

products. Change management (in the rare event of an obsolete and non replaceable part):

• Ensure long term availability by stocking parts through last time buy management according to product forecasts.

• Offer long term frame contract to customers.

Therefore, we refrain from providing detailed part specific information within this manual, which can be subject to continuous changes due to part maintenance for our products.

In order to receive reliable, up to date and detailed information concerning parts used for our product, please contact our support team through the contact information given within this manual.

Preface

PHYTEC Messtechnik GmbH 2018 L-730e.A2 xi


1 PHYTEC Messtechnik GmbH 2018 L-730e.A2

1 Introduction

1.1 Hardware Overview

The phyCORE-TriCORE Development Board for phyCORE-TC1130, phyCORE-TC179X, or phyCORE-TC399 is a low-cost, feature-rich software development platform supporting the Infineon Semiconductors TC1130, TC179x, and TC399 microcontroller. Moreover, due to numerous standard interfaces, the phyCORE-TriCORE Development Board can serve as bedrock for any development application. At the core of the phyCORE-TriCORE Development Board is the phyCORE-TC1130, phyCORE-TC179X, or phyCORE-TC399 System On Module (SOM). These SOMs contain a processor, SRAM, power regulation, supervision, transceivers, and other core functions required to support the TC1130, TC179x, or TC399 processor. Surrounding the SOM is the phyCORE-TriCORE Development Board, adding power input, buttons, connectors, signal breakout, and Ethernet connectivity along with other peripherals. A few things to remember when working with the phyCORE-TriCORE Development Board:

• All of the signals from the SBC module mounted on the Development Board extend to two mating receptacle connectors. A strict 1:1 signal assignment is maintained from the phyCORE-connectors on the module to these expansion connectors. Accordingly, the pin assignment of the expansion bus depends entirely on the pinout of the SBC module mounted on the Development Board.

• The physical layout of the expansion bus is standardized across all applicable PHYTEC Development Boards. This allows us to offer various expansion boards that attach to the Development Board at the expansion bus connectors. These modular expansion boards offer supplemental I/O functions as well as peripheral support devices for specific functions offered by the controller populating the SBC module mounted on the Development Board.

• All controller and on-board signals provided by the SBC module mounted on the Development Board are broken out 1:1 to the expansion board by means of its patch field. The required connections between SBC module / Development Board and the expansion board are made using patch cables included with the expansion board.

1.1.1 Features of the phyCORE-TriCORE Development Board

The phyCORE-TriCORE Development Board supports the following features : • EURO-card standard dimensions (160 mm × 100 mm) • Single 5V power supply input • Dual DB-9 sockets for serial RS-232 interface • Dual DB-9 connectors for CAN interface • GND connector to connect GND signals of a measuring device (such as an oscilloscope) • One phyCORE connector to allow mounting of applicable phyCORE modules

Introduction

PHYTEC Messtechnik GmbH 2018 L-730e.A2 2

• One on-board USB Wiggler connector (USB-mini) • One USB-mini connector for modules USB to UART Bridge • One RJ45 socket for up to 100Mbit TP Ethernet • mating receptacle for expansion board connectivity • connector for graphic LCD ( monochrome LCD) • voltage supply for external devices and subassemblies • provides additional /extCSx Signals generated by addresslines connected to a

demultiplexer

1.1.2 View of the phyCORE-TriCORE Development Board

Figure 1: View of the phyCORE-TriCORE Development Board

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20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

6161 61616161 X10S2S1

1

2

1 2 3

1 2 3

P11

2

3

4

5

6

7

8

9

11

12

13

14

15

16

17

18

19

20 21

22 23

P21

2

3

4

5

6

7

8

9

11

12

13

14

15

16

17

18

19

20 21

22 23

LCD1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

OCDS

2_b

124 36 58 710 912 1114 1316 1518 1720 1922 2124 2326 25



2 Accessing the phyCORE-TriCORE Development Board Features

PHYTEC phyCORE-TriCORE Development Board is fully equipped with all mechanical and electrical components necessary for a speedy and secure start-up.

2.1 Overview of the phyCORE-TriCORE Development Board Peripherals

The phyCORE-TriCORE Development Board is depicted in Figure 1. It features many different interfaces and is equipped with the components as listed in Table 3, Table 4, and Table 5. For a more detailed description of each peripheral, refer to the appropriate chapter listed in the applicable table. Figure 1 highlights the location of each peripheral for easy identification.

2.1.1 Connectors and Pin Header

Table 3 lists all available connectors on the phyCORE-TriCORE Development Board .

Reference Designator

Description See Section

X1 Low voltage socket for power supply 4.1 X2 Mating receptacle for expansion board 4.9

P1 Dual DB-9 sockets for serial RS-232 interface 4.3 4.4

P2 Dual DB-9 connectors for CAN interface 4.5 4.6

TP1 GND connector (for connecting GND signal of measuring devices such as an oscilloscope)

-

X3 phyCORE-Connector enabling mounting of applicable phyCORE modules

4.9

X11 On-board USB Wiggler connector 4.12 X12 USB connector 0 X7 RJ45 socket for 10Mbit TP Ethernet cable 4.7 LCD Connector for dot matrix LCD 4.13 X10 Voltage supply for external devices and subassemblies 4.11

X4 Provides additional / extCSx signals generated by address lines connected to a demultiplexer

4.14

OCDS2 OCDS2 connector for phyCORE-TC179X only 4.17.1

Table 3: phyCORE-TriCORE Development Board Connectors and Pin Headers

Accessing the phyBOARD-TriCORE


Ensure that all module connections do not exceed their expressed maximum voltage or current. Maximum signal input values are indicated in the corresponding controller User's Manual/Data Sheets. As damage from improper connections varies according to use and application, it is the user‘s responsibility to take appropriate safety measures to ensure that the module connections are protected from overloading through connected peripherals.

2.1.2 LEDs

The phyCORE-TriCORE Development Board is populated with 5 LEDs, one of which is user programmable. Figure 1 shows the location of the LEDs. The LED functions are listed in Table 4.

LED Color Description See Section

D2 Green Indication 3V3 is present

D3 Green Indication 5V is present

D5 Red User programmable LED 4.8

D4 Green Shows a working connection with the DAS server on the host PC 4.12

D6 Red Shows the DAS server is disconnected

Table 4: phyCORE-TriCORE Development Board LED Description

2.1.3 Switches

The phyCORE-TriCORE Development Board is populated with two switches, one to boot and another to reset the board. Figure 1 shows the location of the switches. Their functions are listed in Table 5.

Switch Description See Section

S1 Boot Button 4.2

S2 Reset Button

Table 5: phyCORE-TriCORE Development Board Switches Description



3 Jumpers

Peripheral components of the phyCORE-TriCORE Development Board can be connected to the signals of the phyCORE-TC1130, phyCORE-TC179x, or phyCORE-TC399 by setting the applicable jumpers. The Development Board’s peripheral components are configured for use with the phyCORE-TC1130, phyCORE-TC179x, or phyCORE-TC399 by means of insertable jumpers. If no jumpers are set, no signals connect to the DB-9 connectors, the control and display units, and the CAN transceivers. illustrates the numbering of the jumper pads, while Note: Jumpers not listed should not be changed as they are installed with regard to the configuration of the phyCORE-TriCORE Development Board.

Figure 2: Typical Jumper Pad Numbering Scheme

If manual jumper modification is required, please ensure that the board as well as surrounding components and sockets remain undamaged while desoldering. Overheating the board can cause the solder pads to loosen, rendering the module inoperable. If soldered jumpers need to be removed, the use of a desoldering pump, desoldering braid, an infrared desoldering station, desoldering tweezers, hot air rework station or other desoldering method is strongly recommended. Follow the instructions carefully for whatever method of removal is used. Caution! If any modifications to the module are performed, regardless of their nature, the manufacturer guarantee is voided. Figure 3 shows the location of the jumpers on the Development Board.

1357

2468

135

246

13

24

123

12

e.g.:JP28 e.g.:JP23 e.g.:JP24 e.g.:JP23 e.g.:JP17

Jumpers


Figure 3: phyCORE-TriCORE Development Board Jumper Locations

Figure 4, Figure 5, and Figure 6 show the factory default jumper settings for operation of the phyCORE-TriCORE Development Board with the standard phyCORE-TC1130, phyCORE- TC179X, and phyCORE-TC399. Jumper setting for other functional configurations of the phyCORE SOMs mounted on the Development Board are described in Section 4.

11

2

JP13

JP12

JP181 2 3

1 2 3 1

2

JP26

JP21

JP24JP23

JP20

JP14

JP34

JP39

JP27JP19

JP16

JP35

JP22

JP25

JP15

12

34

1

2

3

12

34

12

1

2

3

1

2

3

1

2

3

1

2

12

34

12

12

1

2

3

1 2

12

34

1 2

JP11 2

JP2

JP3

JP30

JP33

JP32

JP29

JP31

JP5JP4

JP7JP8

JP6

1 2

12

1

2

3

12

1

2

3

12

1

2

3

12

12

12

12

12

3 JP111

JP10

12

34

56

78

JP36

12

34

56

78

JP38

JP17

JP28

JP37

JP9

1 2

1 2 3

1 2 3

1 2

1

2



Figure 4: Default Jumper Settings of the phyCORE-TriCORE Development Board for Standard phyCORE-TC1130

Figure 5: Default Jumper Settings of the phyCORE-TriCORE Development Board for Standard phyCORE-TC179X

11

2

JP13

JP12

JP181 2 3

1 2 3 1

2

JP26

JP21

JP24JP23

JP20

JP14

JP34

JP39

JP27JP19

JP16

JP35

JP22

JP25

JP15

12

34

1

2

3

12

34

12

1

2

3

1

2

3

1

2

3

1

2

12

34

12

12

1

2

3

1 2

12

34

1 2

JP11 2

JP2

JP3

JP30

JP33

JP32

JP29

JP31

JP5JP4

JP7JP8

JP6

1 2

12

1

2

3

12

1

2

3

12

1

2

3

12

12

12

12

12

3 JP111

JP10

12

34

56

78

JP36

12

34

56

78

JP38

JP17

JP28

JP37

JP9

1 2

1 2 3

1 2 3

1 2

1

2

11

2

JP13

JP12

JP181 2 3

1 2 3 1

2

JP26

JP21

JP24JP23

JP20

JP14

JP34

JP39

JP27JP19

JP16

JP35

JP22

JP25

JP15

12

34

1

2

3

12

34

12

1

2

3

1

2

3

1

2

3

1

2

12

34

12

12

1

2

3

1 2

12

34

1 2

JP11 2

JP2

JP3

JP30

JP33

JP32

JP29

JP31

JP5JP4

JP7JP8

JP6

1 2

12

1

2

3

12

1

2

3

12

1

2

3

12

12

12

12

12

3 JP111

JP10

12

34

56

78

JP36

12

34

56

78

JP38

JP17

JP28

JP37

JP9

1 2

1 2 3

1 2 3

1 2

1

2

Jumpers


Figure 6: Default Jumper Settings of the phyCORE-TriCORE Development Board for Standard phyCORE-TC399

11

2

JP13

JP12

JP181 2 3

1 2 3 1

2

JP26

JP21

JP24JP23

JP20

JP14

JP34

JP39

JP27JP19

JP16

JP35

JP22

JP25

JP15

12

34

1

2

3

12

34

12

1

2

3

1

2

3

1

2

3

1

2

12

34

12

12

1

2

3

1 2

12

34

1 2

JP11 2

JP2

JP3

JP30

JP33

JP32

JP29

JP31

JP5JP4

JP7JP8

JP6

1 2

12

1

2

3

12

1

2

3

12

1

2

3

12

12

12

12

12

3 JP111

JP10

12

34

56

78

JP36

12

34

56

78

JP38

JP17

JP28

JP37

JP9

1 2

1 2 3

1 2 3

1 2

1

2



4 Functional Components on the phyCORE-TriCORE Development Board

This section describes the functional components of the phyCORE-TriCORE Development Board supported by the phyCORE-TC1130, phyCORE-TC179x, and phyCORE-TC399 appropriate jumper settings to activate these components. Depending on the specific configuration of the phyCORE-TC1130, phyCORE-TC179x, and phyCORE-TC399 module, alternative jumper settings can be used. These jumper settings are different from the factory default settings (shown in Figure 4, Figure 5, and Figure 6) and enable alternative or additional functions on the phyCORE-TriCORE Development Board depending on user needs.

4.1 Power Connector (X1)

Caution! Do not use a laboratory adapter to supply power to the Development Board! Power spikes during power-on could destroy the phyCORE module mounted on the Development Board! Do not change modules or jumper settings while the Development Board is supplied with power! The phyCORE-TriCORE Development Board is available with one power supply connector with a permissible input voltage of +/-5 VDC regulated. The required current load capacity for all power supply solutions depends on the specific configuration of the phyCORE-TC1130, phyCORE-TC179X, and phyCORE-TC399 mounted on the phyCORE-TriCORE Development Board, the particular interfaces enabled while executing software, as well as whether an optional expansion board is connected to the carrier board. An adapter with a minimum supply of 1.5 A is recommended.

Figure 7: Connecting the Supply Voltage at X1

4.2 Activating the Bootstrap Loader

The Infineon Tricore-TC1130, TC179x, and TC399 microcontroller contains an on-chip Bootstrap Loader that provides basic communication and programming functions. The combination of this Bootstrap Loader and the corresponding Flash download software installed on the PC allows for Flash programming with application code via an RS-232 interface.

+5VDC

GND

≥ 1.5 Acenter hole

1.3mm 3.5mm

-- +polarity:

Functional Components


In order to start the on-chip Bootstrap Loader on the phyCORE-TC1130, phyCORE-TC179x, or phyCORE-TC399 the configuration inputs HWCFGx of the microcontroller must provide a certain bit pattern at the time the Reset signal changes from its active to the inactive state. This bit pattern is created by solder jumpers on the module and pass through to the controller with the help of an electronic switch. Applying a low-level signal at pin X1C9 of the phyCORE-TC1130, phyCORE-TC179X, or phyCORE-TC399 (via the Boot input) activates the electronic switch. The phyCORE-TriCORE Development Board provides two different options to activate the on-chip Bootstrap Loader:

1. The Boot button (S1) can be connected to GND via Jumper JP12 which is located next the Boot and Reset buttons at S1 and S2. This configuration enables start-up of the on-chip Bootstrap Loader if the Boot button is pressed during a hardware reset or power-on.

Jumper Setting Description JP12 1 + 2 Boot button (in conjunction with Reset button or connection of the power

supply) starts the Bootstrap Loader on the TC1130 / TC179x / TC399

Table 6: JP12 Configuration of the Boot Button

2. It is also possible to start the Bootstrap Loader via external signals applied to the DB-9 socket P1A. This requires control of the signal transition on the Reset line via pin 7 while a static low-level is applied to pin 4 for the Boot signal.

Jumper Setting Description JP20

1 + 2 Pin 7 (CTS) of the DB-9 socket P1A as RESET signal for the phyCORE-TC1130, phyCORE-TC179x, or phyCORE-TC399

2 + 3 Pin 7 (CTS) of the DB-9 socket P1A as BOOT signal for the phyCORE-TC1130, phyCORE-TC179x, or phyCORE-TC399

open function not used JP21

1 + 2 Pin 4 (DSR) of the DB-9 socket P1A as BOOT signal for the phyCORE-TC1130, phyCORE-TC179x, or phyCORE-TC399

2 + 3 Pin 4 (DSR) of the DB-9 socket P1A as RESET signal for the phyCORE-TC1130, phyCORE-TC179x, or phyCORE-TC399

open function not used JP13

1 + 2 Low-level Boot signal connected with the BOOT input of the phyCORE-TC1130, phyCORE-TC179x, or phyCORE-TC399

2 + 3 Jumper setting generates high-level on Boot input of the phyCORE-TC1130, phyCORE-TC179x, or phyCORE-TC399

open function not used

Table 7: JP20, JP21, JP13 Configuration of Boot via RS-232



Caution: JP20 and JP21 must have the same setting at any time: 1. JP20,JP21 = 1+2 or 2. JP20,JP21 = 2+3

4.3 First Serial Interface (Socket P1A)

Socket P1A is the lower socket of the double DB-9 connector at P1. P1A is connected via jumpers to the first serial interface of the phyCORE-TC1130, phyCORE-TC179x, or phyCORE-TC399.

All Signals from P1A are accessible at connector X9 When connected to a host-PC, the phyCORE-TC1130, phyCORE-TC179x, or phyCORE-TC399 can be rendered in Bootstrap mode via signals applied to the socket P1A (refer to Section 4.2).

Jumper Setting Description JP22 closed Pin 2 of DB-9 socket P1A connected with RS-232 interface signal TxD0 of the

phyCORE-TC1130, phyCORE-TC179x, or phyCORE-TC399 JP23

closed Pin 3 of DB-9 socket P1A connected with RS-232 interface signal RxD0 from the phyCORE-TC1130, phyCORE-TC179x, or phyCORE-TC399

Table 8: Jumper Configuration for the First RS-232 Interface

Pin2: TxD0 Pin 3: RxD0 Pin 5: GND

Figure 8: Pin Assignment of the DB-9 Socket P1A as First RS-232(Front View)

4.4 Second Serial Interface (Socket P1B)

Socket P1B is the upper socket of the double DB-9 connector at P1. P1B is connected via jumpers to the second serial interface of the phyCORE-TC1130, phyCORE-TC179x, or phyCORE-TC399. Handshake signals from P1A are accessible at connector X8 Jumper Setting Description JP15

closed Pin 2 of DB-9 socket P1B connected with RS-232 interface signal TxD1 of the phyCORE-TC1130, phyCORE-TC179x, or phyCORE-TC399

J16 closed Pin 3 of DB-9 socket P1B connected with RS-232 interface signal RxD1 from the phyCORE-TC1130, phyCORE-TC179x, or phyCORE-TC399

Table 9: Jumper Configuration for the Second RS-232 Interface

1234

76

5

89



Pin2: TxD1 Pin 3: RxD1 Pin 5: GND

Figure 9: Pin Assignment of the DB-9 Socket P1A as Second RS-232(Front View)

4.5 First CAN Interface (Plug P2A)

Plug P2A is the lower plug of the double DB-9 connector at P2. P2A is connected to the first CAN interface (CAN0) of the phyCORE-TC1130, phyCORE-TC179x, or phyCORE-TC399 via jumpers. Depending on the configuration of the CAN transceivers and their power supply, the following three configurations are possible:

1. CAN transceiver populating the phyCORE-TC1130, phyCORE-TC179x, or phyCORE-TC399 is enabled and the CAN signals from the module extend directly to plug P2A.

Jumper Setting Description JP25 1 + 2 Pin 7 of DB-9 plug P2A connected with CAN_H0 from on-board transceiver on the

phyCORE-TC1130, phyCORE-TC179x, or phyCORE-TC399 JP24

1 + 2 Pin 2 of DB-9 plug P2A connected with CAN_L0 from on-board transceiver on the phyCORE-TC1130, phyCORE-TC179x, or phyCORE-TC399

JP14 open

No supply voltage to CAN transceiver and opto-coupler on the phyCORE-TriCORE Development Board

JP19 closed GND potential at CAN transceiver and opto-coupler on the phyCORE-TriCORE Development Board

Table 10: Jumper Configuration for CAN Plug P2A Using the CAN Transceiver on the phyCORE-TC1130 or phyCORE-TC179X

Pin 3: GND (Development Board Ground) Pin 7: CAN-H0 (not galvanically separated) Pin 2: CAN-L0 (not galvanically separated) Pin 6: GND (Development Board Ground)

Figure 10: Pin Assignment of the DB-9 Plug P2A (CAN Transceiver on phyCORE-TC1130, Front View)

2. The CAN transceiver populating the phyCORE-TC1130, phyCORE-TC179X, or phyCORE-TC399 is disabled; CAN signals generated by the CAN transceiver (U3) on the Development Board extending to connector P2A without galvanic seperation:

1234

76

5

89

1234

76

5

89



Jumper Setting Description JP25 1 + 3

2 + 4 Pin 7 of DB-9 plug P2A connected with CAN-H0 from CAN transceiver U5 on the Development Board

JP24 1 + 3 2 + 4

Pin 2 of DB-9 plug P2A connected with CAN-L0 from CAN transceiver U5 on the Development Board

JP14 2 + 3 Supply voltage for CAN transceiver and opto-coupler derived from local supply circuitry on the phyCORE-TriCORE Development Board

JP19 closed CAN transceiver and opto-coupler on the Development Board connected with local GND potential

Table 11: Jumper Configuration for CAN Plug P2A Using the CAN Transceiver on the Development Board


Figure 11: Pin Assignment of the DB-9 Plug P2A (CAN Transceiver on Development Board)

3. The CAN transceiver populating the phyCORE-TC1130, phyCORE-TC179X, or phyCORE-

TC399 is disabled; CAN signals generated by the CAN transceiver (U3) on the Development Board extend to connector P2A with galvanic separation. This configuration requires connection of an external CAN supply voltage of 7 to 13 V. The external power supply must be only connected to either P2A or P2B.


2 + 4 Pin 7 of DB-9 plug P2A connected with CAN-H0 from CAN transceiver U5 on the Development Board

JP24 1 + 3 2 + 4

Pin 2 of DB-9 plug P2A connected with CAN-L0 from CAN transceiver U5 on the Development Board

JP14 1 + 2 Supply voltage for CAN transceiver and opto-coupler on the Development Board derived from external source (CAN bus) via on-board voltage regulator

JP19 open CAN transceiver and opto-coupler on the Development Board disconnected from local GND potential

Table 12: Jumper Configuration for CAN Plug P2A Using the CAN Transceiver on the Development Board with Galvanic Separation

1234

76

5

89



Pin 9: VCAN+

Pin 3: VCAN- Pin 7: CAN-H0 (galvanically separated) Pin 2: CAN-L0 (galvanically separated) Pin 6: VCAN-

Figure 12: Pin Assignment of the DB-9 Plug P2A (CAN Transceiver on Development Board with Galvanic Separation)

4.6 Second CAN Interface (Plug P2B)

Plug P2B is the upper plug of the double DB-9 connector at P2. P2B is connected to the second CAN interface (CAN1) of thephyCORE-TC1130, phyCORE-TC179X, or phyCORE-TC399 via jumpers. Depending on the configuration of the CAN transceivers and their power supply, the following three configurations are possible:

1. CAN transceiver populating the phyCORE-TC1130, phyCORE-TC179X, or phyCORE-TC399 is enabled and the CAN signals from the module extend directly to plug P2B.

Jumper Setting Description JP27 1 + 2 Pin 7 of the DB-9 plug P2B is connected to CAN-H1 from on-board transceiver on

the phyCORE module JP26 1 + 2 Pin 2 of the DB-9 plug P2B is connected to CAN-L1 from on-board transceiver on

the phyCORE module JP14

open CAN transceiver and opto-coupler on the Development Board disconnected from supply voltage

JP19 closed No GND potential at CAN transceiver and opto-coupler on the phyCORE-TriCORE Development Board

Table 13: Jumper Configuration for CAN Plug P2B Using the CAN Transceiver on the phyCORE-TC1130, phyCORE-TC179X, and phyCORE-TC399


Figure 13: Pin Assignment of the DB-9 Plug P2B (CAN Transceiver on phyCORE-TC1130, Front View)

2. The CAN transceiver populating the phyCORE-TC1130, phyCORE-TC179X, or phyCORE-TC399 is disabled; CAN signals generated by the CAN transceiver (U4) on the Development Board extending to connector P2B without galvanic separation:

1234

76

5

89

1234

76

5

89




2 + 4 Pin 7 of DB-9 plug P2B connected with CAN-H1 from CAN transceiver U4 on the Development Board

JP26 1 + 3 2 + 4

Pin 2 of DB-9 plug P2B connected with CAN-L1 from CAN transceiver U4 on the Development Board

JP14 2 + 3 Supply voltage for CAN transceiver and opto-coupler derived from local supply circuitry on the phyCORE-TriCORE Development Board

JP19 closed CAN transceiver and opto-coupler on the Development Board connected with local GND potential

Table 14: Jumper Configuration for CAN Plug P2B Using the CAN Transceiver on the Development Board


Figure 14: Pin Assignment of the DB-9 Plug P2B (CAN Transceiver on Development Board)

3. The CAN transceiver populating the phyCORE-TC1130, phyCORE-TC179X, or phyCORE-

TC399is disabled; CAN signals generated by the CAN transceiver (U4) on the Development Board extend to connector P2B with galvanic separation. This configuration requires connection of an external CAN supply voltage of 7 to 13 V. The external power supply must be only connected to either P2A or P2B.


2 + 4 Pin 7 of DB-9 plug P2B connected with CAN-H1 from CAN transceiver U3 on the Development Board

JP26 1 + 3 2 + 4

Pin 2 of DB-9 plug P2B connected with CAN-L1 from CAN transceiver U3 on the Development Board

JP14 1 + 2 Supply voltage for CAN transceiver and opto-coupler on the Development Board derived from external source (CAN bus) via on-board voltage regulator

JP19 open CAN transceiver and opto-coupler on the Development Board disconnected from local GND potential

Table 15: Jumper Configuration for CAN Plug P2B Using the CAN Transceiver on the Development Board with Galvanic Separation

1234

76

5

89



Pin 9: VCAN+

Pin 3: VCAN- Pin 7: CAN-H1 (galvanically separated) Pin 2: CAN-L1 (galvanically separated) Pin 6: VCAN-

Figure 15: Pin Assignment of the DB-9 Plug P2B (CAN Transceiver on Development Board with Galvanic Separation)

4.7 RJ45 Ethernet Connector (X7)

The phyCORE-TriCORE Development Board provides the Ethernet RJ45 jack with integrated magnetic at X7 to enable immediate connection of the phyCORE-TC1130, phyCORE-TC179X, or phyCORE-TC399 to an 10/100 Mbit/s Ethernet network. Two status LEDs for LINK and LAN are provided to display network status. Table 16 shows the jumper settings needed. Jumper Setting Description JP10 1 + 2

3 + 4 5 + 6 7 + 8

The Ethernet transformer module is connected to the Ethernet signals on the phyCORE-TC1130 or phyCORE-TC179X

JP2 open Configuration for phyCORE-TC1130 module closed Configuration for phyCORE-TC179X/ TC399 module

JP3 JP4 open

Configuration for phyCORE-TC179X and phyCORE-TC179X

JP5 JP6

open Configuration for phyCORE-TC1130 module closed Configuration for phyCORE-TC179X/ TC399module

JP11 1+2 2+3

Configuration for phyCORE-TC179X/ TC399 module Configuration for phyCORE-TC1130 module

JP29 closed Connect the Ethernet /SPEED signal to the RJ45 LED JP33 closed Connect the Ethernet /LINK signal to the RJ45 LED

Table 16: JP2-6, JP10, JP11 Configuration of the Ethernet Interface

4.8 User Programmable LED (D5)

The phyCORE-TriCORE Development Board offers a programmable LED at D5 for user implementations. This LED can be connected to port pin P2.11 of the phyCORE-TC1130 ,P8.0 of the phyCORE-TC179X or P10.7 of TC399 which is available via signal GPIO0 (JP18 = closed). A low-level at port pin causes the LED to illuminate, LED D5 remains off when writing a high-level to the appropriate port pin.

1234

76

5

89



4.9 Pin Assignment of the phyCORE, Expansion Bus and Patch Field

As described in Section 1.1, all signals from the phyCORE-TC1130, phyCORE-TC179X, or phyCORE-TC399 extend in a strict 1:1 assignment to the Expansion Bus connector X2 on the Development Board. These signals, in turn, are routed in a similar manner to the patch field on an optional expansion board that mounts to the Development Board at X2. Please note that, depending on the design and size of the expansion board, only a portion of the entire patch field is utilized under certain circumstances. When this is the case, certain signals described in the following section will not be available on the expansion board. However, the pin assignment scheme remains consistent. A two dimensional numbering matrix similar to the one used for the pin layout of the phyCORE-connector is provided to identify signals on the Expansion Bus connector (X2 on the Development Board) as well as the patch field. However, the numbering scheme for Expansion Bus connector and patch field matrices differs from that of the phyCORE-connector, as shown in Figure 16 and Figure 17.

Figure 16: Pin Assignment Scheme of the Expansion Bus

B A

D C

80

1

80

1



Figure 17: Pin Assignment Scheme of the Patch Field

Table 17 shows the pin assignment on the phyCORE-TC1130, phyCORE-TC179X, or phyCORE-TC399, in conjunction with the Expansion Bus (X2) on the Development Board, and the patch field on an expansion board.

A B C D E F

54

1



Signal phyCORE-TC1130

Signal phyCORE-TC179X


phyCORE-TC1130 phyCORE-TC179X phyCORE-TC399

Expansion Bus

Patch Field

xD0 D0

For information on these signals, refer to phyCORE-TC399 Hardware Manual (L-853).

18B 18B 33F xD1 D1 19A 19A 34A xD2 D2 20A 20A 34E xD3 D3 20B 20B 34B xD4 D4 21A 21A 34D xD5 D5 21B 21B 34F xD6 D6 22B 22B 35A xD7 D7 23A 23A 35E xD8 D8 28B 28B 37C xD9 D9 29A 29A 37E xD10 D10 30A 30A 37B xD11 D11 30B 30B 37F xD12 D12 31A 31A 38A xD13 D13 31B 31B 38C xD14 D14 32B 32B 38E xD15 D15 33A 33A 38B xD16 D16 37B 37B 40A xD17 D17 38A 38A 40E xD18 D18 38B 38B 40B xD19 D19 39A 39A 40D xD20 D20 40A 40A 40F xD21 D21 40B 40B 41A xD22 D22 41A 41A 41E xD23 D23 41B 41B 41B xD24 D24 42B 42B 41F xD25 D25 43A 43A 42A xD26 D26 43B 43B 42C xD27 D27 44A 44A 42E xD28 D28 45A 45A 42B xD29 D29 45B 45B 42F xD30 D30 46A 46A 43A xD31 D31 46B 46B 43C xA0 A0 8B 8B 30B xA1 A1 9A 9A 30D xA2 A2 10A 10A 30F xA3 A3 10B 10B 31A xA4 A4 11A 11A 31E

Table 17: Pin Assignment for the phyCORE-TC1130, phyCORE-TC179X and Development Board / Expansion Board







Expansion Bus

Patch Field

xA5 A5


11B 11B 31B xA6 A6 12B 12B 31F xA7 A7 13A 13A 31A xA8 A8 13B 13B 32C xA9 A9 14A 14A 32E xA10 A10 15A 15A 32B xA11 A11 15B 15B 32F xA12 A12 16A 16A 33A xA13 A13 16B 16B 33C xA14 A14 17B 17B 33E xA15 A15 18A 18A 33B xA16 A16 23B 23B 35B xA17 A17 24A 24A 35D xA18 A18 25A 25A 35F xA19 A19 25B 25B 36A xA20 A20 26A 26A 36E xA21 A21 26B 26B 36B xA22 A22 27B 27B 36F xA23 A23 28A 28A 37A P00 P82 / FCLP1A 13C 13C 4F P01 P83 / SON0 13D 13D 5A P03 P84 / FCLN1 14C 14C 5C P02 P85 / SOP1A 15C 15C 5E P04 P86 / SON0 15D 15D 5B P05 /HOLD 35B 35B 39B P06 /HLDA 36A 36A 39D P07 /BREQ 36B 36B 39F P08 P10 2B 2B 28E P09 P11 3A 3A 28B P010 P12 3B 3B 28F P011 /CS1 6B 6B 29F P10 AN9 / P09 74C 74C 25C P11 AN11 / P011 73C 73C 24F P12 AN10 / P010 73D 73D 25A P13 AN12 / P012 72D 72D 24B P14 AN14 / P014 71C 71C 24A P15 AN13 / P013 71D 71D 24E P16 AN16 / P40 70C 70C 23D

Table 17: Pin Assignment for the phyCORE-TC1130, phyCORE-TC179X and Development Board / Expansion Board (cont.)







Expansion Bus

Patch Field

P17 AN15 / P015


70D 70D 23F P18 AN17 / P41 69C 69C 23B P19 AN19 / P43 68C 68C 23A P110 AN18 / P42 68D 68D 23E P111 AN20 / P44 67D 67D 22F P112 AN22 / P46 66C 66C 22B P113 AN21 / P45 66D 66D 22D P114 AN24 / P48 65C 65C 22A P115 AN23 / P47 65D 65D 22E P20 / RxD0_TTL P50 / RxD0_TTL 16D 16D 6A

P21 / TxD0_TTL P51 / TxD0_TTL 17D 17D 6C

P22 / MRST0 MRST0 27D 27D 9B

P23 / MTSR0 MTSR0 28D 28D 10A

P24 / SCLK0 SCLK0 30D 30D 10B

P25 / MRST1 P65 / MRST1 26C 26C 9A

P26 / MTSR1 P64 / MTSR1 28C 28C 9F

P27 / SCLK1 P66 / SCLK1 29C 29C 10C

P28 / RxD1_TTL P52 / RxD1_TTL 19C 19C 6F

P29 / TxD1_TTL P53 / TxD1_TTL 20C 20C 7A

P210 P81 / SOP0A 12D 12D 4B

P211 P80 / FCLP0A 11D 11D 4A

P212 / SDA0 SDA0 32D 32D 11C

P213 / SCL0 SCL0 31C 31C 10F

P214 / SDA1 SDA1 24C 24C 8B

P215 / SCL1 SCL1 25C 25C 8D

P30 P75 50D 50D 17E P31 P76/ AD1EMUX0 51C 51C 17B P32 P77/ AD1EMUX1 51D 51D 17D P33 AN43 52D 52D 17F P34 AN41 / P57 53C 53C 18A P35 AN42 53D 53D 18E P36 AN40 / P98 54C 54C 18B P37 AN38 / P96 55C 55C 18D P38 AN39 / P97 55D 55D 18F P39 AN36 / P94 56C 56C 19A








Expansion Bus

Patch Field

P310 AN37 / P95


56D 56D 19E P311 AN35 / P93 57D 57D 19B P312 AN33 / P91 58C 58C 19F P313 AN34 / P92 58D 58D 20A P314 AN32 / P90 59C 59C 20C P315 AN31 / P415 60C 60C 20E P40 / USBCLK P55 46C 46C 15F P41 / RVCI P56 46D 46D 16A P42 / VPI P70 47D 47D 16C P43 / VMI P71/ AD0EMUX2 48C 48C 16E P44 / VPO P72/ AD0EMUX0 48D 48D 16B P45 / VMO P73/ AD0EMUX1 49C 49C 16F P46 / USBOE P74 50C 50C 17A P47 / /BRKOUT_A /BRKOUT 40C 40C 13D EGPIO0 P23 / SLSO3 80A 80A 54E EGPIO1 P22 / SLSO2 80B 80B 54B EGPIO3 P26 / SLSO6 78A 78A 53B EGPIO2 P24 / SLSO4 79A 79A 54A EGPIO4 P25 / SLSO5 78B 78B 53F EGPIO5 P27 / SLSO7 77B 77B 53E EGPIO6 P29 76A 76A 53A EGPIO7 P28 76B 76B 53C EGPIO8 P211 75A 75A 52B EGPIO9 P210 75B 75B 52F EGPIO11 P214 73A 73A 52A EGPIO10 P212 74A 74A 52E EGPIO12 P213 73B 73B 52C EGPIO13 P215 72B 72B 51F EGPIO14 P31 71A 71A 51E EGPIO15 P30 71B 71B 51B EGPIO16 P33 70A 70A 50F EGPIO17 P32 70B 70B 51A EGPIO18 P34 69A 69A 50D EGPIO19 P36 68A 68A 50E EGPIO20 P35 68B 68B 50B EGPIO21 P37 67B 67B 50A EGPIO22 P39 66A 66A 49D EGPIO23 P38 66B 66B 49F








Expansion Bus

Patch Field

EGPIO24 P311


65A 65A 49E EGPIO25 P310 65B 65B 49B EGPIO26 P312 64A 64A 49A EGPIO27 P314 63A 63A 48B EGPIO28 P313 63B 63B 48F EGPIO29 P315 62B 62B 48E EGPIO30 P14 61A 61A 48A EGPIO31 P13 61B 61B 48C EGPIO32 P16 60A 60A 47B EGPIO33 P15 60B 60B 47F EGPIO34 P17 59A 59A 47E EGPIO35 P18 58A 58A 47A EGPIO36 P19 58B 58B 47C EGPIO37 P110 57B 57B 46F EGPIO38 P111 56A 56A 46E EGPIO39 P112 56B 56B 46B EGPIO40 P113 55A 55A 45F /HDRST /HDRST 10C 10C 3D /PORESET /PORST 11C 11C 4E /NMI /NMI 4A 4A 29A /TRST /TRST 41C 41C 14A TCK TCK 43D 43D 15A TDI TDI 40D 40D 13F TDO TDO 41D 41D 14E TMS TMS 42D 42D 14B TRCLK TRCLK 38C 38C 13A /BRKIN /BRKIN 39C 39C 13B xHWCFG2 AN29 / P413 61D 61D 21A xHWCFG1 AN30 / P414 61C 61C 20F xHWCFG0 VAREF1 60D 60D 20B MII_TXCLK AN25 / P49 64C 64C 21F MII_RXCLK AN26 / P410 63D 63D 21B MII_MDIO AN28 / P412 62D 62D 21C /E_INT 5V_VBUS 30C 30C 10E E_DUPLEX P54 25D 25D 8F E_NWAYEN /SLSI0 26D 26D 9E x/CS3 /CS3 5A 5A 29E x/CS2 /CS2 5B 5B 29B








Expansion Bus

Patch Field

/CSCOMB /CSCOMB


47B 47B 43E x/BC0 /BC0 8A 8A 30E x/BC1 /BC1 33B 33B 38F x/BC2 /BC2 52B 52B 45A x/BC3 /BC3 53B 53B 45B x/RD /RD 7B 7B 30A x/WR /WR 49A 49A 44A xALE /ADV 6A 6A 29D x/BAA /BAA 51B 51B 44F xADV /ADV 50B 50B 44B x/WAIT /WAIT 34A 34A 39A /RESIN /RESIN 10D 10D 3F /BOOT /BOOT 9C 9C 3B FL_VPEN /CS0 35A 35A 39E xMR / W MR / W 48B 48B 43F xBFCLKI BFCLKI 50A 50A 44E xBFCLKO BFCLKO 51A 51A 44D CAN_H0 CAN_H0 21D 21D 7D CAN_L0 CAN_L0 20D 20D 7E CAN_H1 CAN_H1 18C 18C 6E CAN_L1 CAN_L1 18D 18D 6B CAN_H2 CAN_H2 44C 44C 15C CAN_L2 CAN_L2 43C 43C 14F CAN_H3 CAN_H3 45D 45D 15B CAN_L3 CAN_L3 45C 45C 15E RXD0 RXD0 22D 22D 7F TXD0 TXD0 23D 23D 8E RXD1 RXD1 21C 21C 7B TXD1 TXD1 23C 23C 8A ETH_Link LED

ETH_Link LED

33C 33C 11E

ETH_Lan LED

ETH_Lan LED

34C 34C 11F

ETH_RXD- ETH_RXD- 35C 35C 12A ETH_TXD- ETH_TXD- 36C 36C 12B ETH_RXD+ ETH_RXD+ 35D 35D 12E ETH_TXD+ ETH_TXD+ 36D 36D 12D D+ D+ 37D 37D 12F








Expansion Bus Patch Field

D- D-


38D 38D 13E RTC_CLKOUT RTC_CLKOUT 1B 1B 28C /IRTC /IRQRTC 33D 33D 11B Tout NC 8D 8D 3A 3V3_IN 3V3 1C, 2C, 1D, 2D 1C, 2C, 1D, 2D 1A, 1C

1V5_IN NC 4C, 5C

not connected to Expansion Bus 4C,5C,4D, 5D=5V

2A,1B2C,1D

GND

2A, 7A, 12A, 17A, 22A, 27A, 32A, 37A, 42A, 47A, 52A, 57A, 62A, 67A, 72A, 77A, 4B, 9B, 14B, 19B, 24B, 29B, 34B, 39B, 44B, 49B, 54B, 59B, 64B, 69B, 74B, 79B, 3C, 7C, 12C, 17C, 22C, 27C, 32C, 37C, 42C, 47C, 52C, 57C, 62C, 67C, 72C, 3D, 9D, 14D, 19D, 24D, 29D, 34D, 39D, 44D, 49D, 54D, 59D, 64D, 69D,

2A, 7A, 12A, 17A, 22A, 27A, 32A, 37A, 42A, 47A, 52A, 57A, 62A, 67A, 72A, 77A, 4B, 9B, 14B, 19B, 24B, 29B, 34B, 39B, 44B, 49B, 54B, 59B, 64B, 69B, 74B, 79B, 3C, 7C, 12C, 17C, 22C, 27C, 32C, 37C, 42C, 47C, 52C, 57C, 62C, 67C, 72C, 3D, 9D, 14D, 19D, 24D, 29D, 34D, 39D, 44D, 49D, 54D, 59D, 64D, 69D,

3C, 4C, 7C, 8C, 9C,12C, 13C,14C, 17C, 18C, 19C, 22C, 23C, 24C, 27C, 29C, 30C, 31C, 34C, 35C, 36C, 39C, 40C, 41C, 44C, 45C, 46C, 49C, 50C, 51C, 54C, 4D, 5D, 6D, 9D, 10D, 11D, 14D, 15D, 16D, 19D, 20D, 21D, 24D, 25D, 26D, 28D, 31D, 32D, 33D, 36D, 37D, 38D, 41D, 42D, 43D, 46D, 47D, 48D, 51D, 52D, 53D, 1E, 2E, 1F

AGND 77C, 74D, 79D 77C, 74D, 79D GND PLD_TMS LAN_/CS

(W5300) 48A 48A 43B

PLD_TCK /CS_RAM2 53A 53A 45E








Expansion Bus

Patch Field

PLD_TDO P115 For information on these signals, refer to phyCORE-TC399 Hardware Manual (L-853).

54A 54A 45D PLD_TDI P114 55B 55B 46A SPIEEPWP P87 16C 16C 5F ICCEEPWP AN27 / P411 63C 63C 21E NC NC 1A, 6D, 7D 1A, 6D, 7D 28A,

2D,2F


4.10 DS2401 Silicon Serial Number

Communication to a DS2401 Silicon Serial Number can be implemented in various software applications for the definition of a node address or as copy protection in networked applications. The DS2401 is optionally populated on U2 on the Development Board.

The Silicon Serial Number Chip mounted on the phyCORE-TriCORE Development Board can be connected to port pin P2.10 of the TC1130, port pin P8.0 of the TC179X or P10.8 of the TC399. Jumper Setting Description JP1

closed Port pin P2.10 of the TC1130 is used to access the Silicon Serial Number

JP1 closed

Port pin P8.1 of the TC179X is used to access the Silicon Serial Number

JP1 closed

Port pin P10.8 of the TC399 is used to access the Silicon Serial Number

Table 18: JP1 Jumper Configuration for Silicon Serial Number Chip

Figure 18: Connection of the DS2401 Silicon Serial Number

4.11 Pin Header Connector (X10)

Connector X10 supplies 5 VDC at pin 1 and provides the phyCORE-TriCORE Development Board GND potential at pin 2. The maximum current draw depends on the power adapter used.



4.12 USB Wiggler (X11)

The phyCORE-TriCORE Development Board provides the USB jack X11 to enable access to the JTAG of the phyCORE-TC1130, phyCORE-TC179X or phyCORE-TC399 via the DAS Server JTAG over USB Chip. Make sure the Latest DAS released is installed on your PC. Please contact your prefered debug vendor for support of DAS. If DAS is installed on the PC, the driver for the USB Wiggler will automatically be installed after connecting the The phyCORE -TriCORE Development Board with the PC. Two status LEDs for USB Wiggler status are provided: LED D4 (green): LED is ON if a working connection is established with the DAS Server on the PC LED D6 (red): LED is ON when DAS Server is disconnected after being connected Caution: When using USB Wiggler connector X11, make sure there is NO or tristated connection on the JTAG connector of the phyCORE-TC1130 (X2) , phyCORE-TC179X (X1) or phyCORE-TC399 (X1)/DAP1 and the OCDS2 connector phyCORE-TriCORE Development Board is NOT used.

4.13 LCD Connector

The connector LCD on the phyCORE-TriCORE Development Board enable connection of an optional LCD – Display. Signals for the following Display-Controller are provided T6963C (default), HD61202, HD44780. Depending on the used LCD controller the following jumper configuration are required. Jumper Setting Description JP30 2+3 Connect /RD signal of TC1130 or TC179X to Pin5 of LCD connector JP31 2+3 Connect /WR signal of TC1130 or TC179X to Pin6 of LCD connector JP32 1+2 Connect /CS signal of TC1130 or TC179X to Pin6 of LCD connector

Table 19: Jumper Configuration for T6963C LCD-Controller



Jumper Setting Description JP36 1+2 Select /CS3 for LCD select

3+4 Select /CS2 for LCD select / not for phyCORE-TC399 Note the caution on bottom of this page regarding J36

5+6 /CS1 for LCD ( TC179X only) 7+8 /CS0 for LCD ( TC179X only)

open No chipselect is used for display or U18 is used for generation of a chipselect for LCD and Ethernet Chip W5300 (this feature is only possible with the phyCORE-TC179X) Note the caution on bottom of this page regarding J36

JP34 1+2 Connect 5V to Pin22 of LCD connector 2+3 Connect GND to Pin22 of LCD connector

JP35 1+2 Connect 5V to Pin19 of LCD connector 2+3 Connect GND to Pin19 of LCD connector

Table 19: Jumper Configuration for T6963C LCD-Controller (cont.)

Caution: J36 must be left open as long no free chip select is provided by the phyCORE-TC1130, phyCORE-TC179X or phyCORE-TC399 HW-configuration. On standard phyCORE-TC399 -> no CSx is free => JP36 = open On standard phyCORE-TC179X -> only /CS2 is free => JP36 = 3+4 On standard phyCORE-TC1130 -> only /CS2 is free => JP36 = 3+4 When setting JP36, only selection of one /CSx for the LCD is allowed.

Jumper Setting

Description

JP30 1+2 connect (A3 +/CSx) signal of TC1130 or TC179X to Pin5 of LCD connector JP31 1+2 connect (/A+/CSx) signal of TC1130 or TC179X to Pin6 of LCD connector JP32 2+3 connect LCD_EN signal of TC1130 or TC179X to Pin6 of LCD connector JP36 Refer to Caution regarding

1+2 select /CS3 for LCD ( TC179X only) 3+4 select /CS2 for LCD ( TC179X only) 5+6 select /CS1 for LCD

7+8 select /CS0 for LCD

Table 20: Jumper Configuration for HD61202, HD44780 LCD-Controller

Control Signals for the supported LCD-controller are: • Addressline A1 is used for R/W Signal for the HD61202, HD44780 • Addressline A2 is used for C/D Signal for the T6963C and (D/I) for HD61202 and

HD44780 LCD-Controller • Adressline A3 is used for CS_LS Signal for the HD61202 • Adressline /A3 is used für for CS_RS Signal for the HD61202



-5 V negative contrast voltage from U17

5 V contrast voltage from Dev. Board

negative contrast voltage from LCD (default for AC049)

R53= 4k7 R54= 15k R53 = 0R RT4= 5k RT4= 5k RT4 = 5k R59= 0R R56= 0R R56 = 4k7 R58= 0R R58= 0R R58 = 0R

Table 21: LCD Contrast Configuration

Note: Please contact PHYTEC for information on available LCD-Displays for the phyCORE-TriCORE Development Board.

4.14 Additional chipselect /extCSx on X4

This feature can only be used with a phyCORE-TC179X when jumper J24 on the Module is NOT populated. This feature can only be used with a phyCORE-TC399 when jumper J42 (CS2 free) on the Module is NOT populated AND J30-J32=1+2 on phyCORE-TC399 . Caution! J24 is populated per default on the phyCORE-TC179X. J42 is populated per default on the phyCORE-TC399. J30-J32=2+3 on phyCORE-TC399 Connector X4 provides additional chip-select Signals which are generated by /CS3 of the phyCORE-TC179X/phyCORE-TC1130 or /CS2 phyCORE-TC399 and address lines A16,A17,A18 through a decoder/demultiplexer (U18) on the phyCORE-TriCORE Development Board. Table 22 shows the chip-select activation depending on address lines A16-A18 and chipselect /CS3 or /CS2 signals.

/CS3 TC179X /CS2 TC399

A18 A17 A16 Activated chipselect on X4 (active low)

0 0 0 0 Y0 (reserved for W5300) JP37 Only for phyCORE-TC179X (refer to jumper JP37)

0 0 0 1 Y1 (reserved for LCD) JP38 (refer to jumper JP38) 0 0 1 0 /extCSa 0 0 1 1 /extCSb 0 1 0 0 /extCSc 0 1 0 1 /extCSd 0 1 1 0 /extCSe 0 1 1 1 /extCSf 1 X X X No chipselect on X4 is activated

Table 22: Truth-table for generating additional chipselect on X4 of the phyCORE-TriCORE Development Board.



Caution! If using the Additional chipselect feature on X4 with a phyCORE-TC1130, jumper JP37 and JP38 must always be open. See Table 23 for more information.

Jumper Setting Description JP37

open Y0 output of U18 is NOT used for Ethernet-chip W5300 on phyCORE-TC179X. (JP37 must always be open when a phyCORE-TC1130 is used with the phyCORE-Tricore development board)

closed Y0 output of U18 is used for Ethernet-chip W5300 on phyCORE-TC179X (this feature is only for phyCORE-TC179X without )

JP38 open Y1 output of U18 is NOT used for LCD closed Y1 output of U18 is used for LCD

Table 23: Additional chipselect jumper settings for JP38 and JP39

4.15 Jumper JP39 for /CS to SRAM BANK2 Connection on the phyCORE-TriCORE Development Board (only for phyCORE-TC179X and TC399)

Jumper Setting Description JP39 open /CS2 is NOT connected to RAM BANK2 of the phyCORE-TC179X or phyCORE-TC399

closed /CS2 is connected to RAM BANK2 of the phyCORE-TC179X (this feature is only for phyCORE-TC179X) /CS1 is connected to RAM BANK2 of the phyCORE-TC179X

4.16 JTAG PLD Connector (phyCORE-TC1130 ONLY)

As shown in Table 24 , the 6 Pin connector JTAG_PLD provides all signals for connection of a PLD-Programmer to load software to the on-board PLD of the phyCORE-TC1130.

JTAG_PLD Signal Pin1 3,3V Pin2 PLD_TDO Pin3 PLD_TDI Pin4 PLD_TMS Pin5 GND Pin6 PLD_TCK

Table 24: Pin assignemt JTAG_PLD connector for phyCORE- TC1130

Caution! JTAG_PLD connector on the Development board must not be used when using the phyCORE-TC179X module on the phyCORE-TriCORE Development Board.



4.17 USB Connector (X12)

Depending on the used phyCORE-module on the Development Board, the USB connector X12 provides the following connection: For the phyCORE-TC1130:

• X12 enables the connection to the TC1130 USB feature

Table 25 shows the jumper settings for the phyCORE-TC1130.

Jumper Setting Description JP9 open

Disconnect 5V from USB Bus JP28 2+3

Table 25: TC1130 Jumper Configuration for X12

For the phyCORE-TC179X and phyCORE-TC399:

• X12 enables the connection to the TC179X onboard USB to UART Bridge. Table 26 shows the jumper settings for the phyCORE-TC179X or phyCORE-TC399. Jumper Setting Description JP9 closed configuration for phyCORE-TC179X module JP28 open configuration for phyCORE-TC179X module

Table 26: TC11796 Jumper Configuration for X12

4.17.1 OCDS2 connector only for phyCORE-TC179X

OCDS2 debugging requires additional Trace Signals of the CPU with the OCDS1 Signals. With phyCORE-TriCORE Development Board, a 60 Pin Highspeed connector OCDS2, both signals are available. Caution! When using OCDS2 Trace connector OCDS2 on the phyCORE-TriCORE Development Board , make sure there is NO or tristated connection on the JTAG connector of the phyCORE-TC1130 (X2) or phyCORE-TC179X (X1) and X11 must NOT be connected with the PC

Revision History


5 Revision History

Date Version # Changes in this manual 12 March 2009 Manual L-730e_0

KSP-0150-B0 PCB# 2200.0-001

Preliminary edition

09 October 2009 Manual L-730e_1 KSP-0150-B1 PCB# 2200.1-001

1st Edition

06 December 2018 Manual L-730e.A2 KSP-0150-B1 PCB# 2200.1-001

New versioning added. Addition of phyCORE-TC399



Index

B Bootstrap Loader ................................... 9

C CAN Interface

Plug P2A ........................................ 12 Plug P2B ........................................ 14

Connectors ........................................... 3

D D3 .................................................... 16 D4 .................................................... 27 D6 .................................................... 27 DS2401 ............................................. 26

E EMC ................................................... ix Ethernet ............................................ 16 Expansion Bus .................................... 16

F Features .............................................. 1

J JP39 ................................................. 30 JTAG

PLD Conncector ............................... 30 Jumpers .............................................. 5

L LCD ................................................... 27 LED

User Programmable ........................... 16 LEDs ................................................... 4

P Patch Field .......................................... 16 Peripherals ........................................... 3 Pin Assignment .................................... 16 Pin Header ........................................... 3 Power Connectors .................................. 9

S Serial Interface

P1A ................................................ 11 P1B ................................................ 11

Silicon Serial Number ............................ 26 Switches .............................................. 4

U USB ................................................... 31 USB Wiggler ........................................ 27

X X1 ...................................................... 9 X10 .................................................... 26 X11 .................................................... 27 X12 .................................................... 31 X4 ..................................................... 29 X7 ..................................................... 16

Suggestions for Improvement


Document: phyCORE-TriCORE Development Board Document number: L-730e.A2, December 2018 How would you improve this manual? Did you find any mistakes in this manual? page Submitted by: Customer number: Name: Company: Address: Return to: PHYTEC Messtechnik GmbH Postfach 100403 D-55135 Mainz, Germany Fax : +49 (6131) 9221-33


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