Physical Design Challenges in the Chip Power Distribution ... · Physical Design Challenges in the...

Physical Design Challenges in the Chip Power Distribution Network

Farid N. Najm Professor & Chair

ECE Dept, University of Toronto [email protected]

Outline

■  Introduction ●  Power grid topology ●  Physical design challenges

■  Power grid verification ●  EDA: simulation, vectorless verification ●  Engineering solution: over-design, and over-kill

■  Constraints-based verification ●  Voltage variations ●  Electromigration

■  Constraints generation ■  Conclusion

F. N. Najm Challenges in Power Grid 2

Power Grid Topology

■  ~ a Billion nodes ■  ~ 2,000 C4 pads

●  1,000 Vdd, 1,000 Vss

■  All levels of metal stack

■  Hundreds of millions of instances of logic cells


RLC RLC RLC

RC Layer

RC Layer

RC Layer

Vdd

Pads

Circuit current sources

Pkg, PCB

Power Grid Topology

■  Package, motherboard, and VRM model; inductance!


Power-Managed Chip Grid

■  Gated supplies

■  Voltage islands

■  Active devices!


RLC RLC RLC

M7 (RC Layer)

M6 (RC Layer)

M1 (RC Layer)

Vdd

Pads


Pkg, PCB

M5 (RC Layer)

M4 (RC Layer)M4

M3 (RC Layer)M3

M2 (RC Layer)M2

M1

Gate FET

M1 (RC Layer)


M4 (RC Layer)M4

M3 (RC Layer)M3

M2 (RC Layer)M2

M1

Gate FET

RLC RLC RLC

Vdd

Pads

Pkg, PCB

Glo

bal (

un-g

ated

) Grid

Loca

l (ga

ted)

Grid

Mesh Layer Structure

■  In every layer, the grid is mostly a regular mesh.


Metal 3

Metal 4

Vdd

Vdd

Vdd

Gnd

Gnd

Gnd

■  Note: ●  Many variations on this central theme ●  Top layer C4 pads typically on a ~200µm grid ●  Local non-uniformities make room for signal routing

Physical Design

■  With hundreds of millions of instances on die and clocks running at GHz rates, the total power is high ●  High performance SOCs might consume over 150 Watts ●  Very hard to keep supply regulated under such conditions

■  Physical design of the grid can have big impact: ●  Voltage variations in bottom layers impact circuit timing ●  Voltage overshoot (inductive kick) impact I/O signal noise ●  Electromigration damage can be catastrophic throughout

■  Nightmare: ensure circuit is safe from all this while distributing over 150 Amps to >400 million instances


Power Grid Verification


Power Grid Verification

■  Verification is needed to check the grid design: ●  Early high-level grid verification and planning ●  Incremental verification during redesign cycles ●  Detailed grid verification at sign-off time

■  Key problem: ●  The circuit currents are unknown or highly uncertain!

■  Need reliable verification in the face of uncertainty.


Existing Commercial Solutions

■  Simulation ●  Decouple grid from underlying circuit ●  Simulate the grid for given current source stimulus ●  Expensive and incomplete; inconclusive

■  Existing solutions for vectorless verification ●  Voltage variations: timing windows, random scenarios ●  Electromigration: Black’s model, current density check ●  Questionable results

■  Engineering solution: over-design, but also over-kill ■  Problem: running out of metal area for signal routing!


Constraints-Based Verification


Constraints-Based Verification

■  Given: ●  Power Grid (DC, RC, or RLC netlist) ●  Tolerance for grid node voltage fluctuations (Vth) ●  Tolerance for grid branch current densities (EM) ●  Peak budgets (current constraints) for block currents

■  Find: ●  Worst-case voltage variations for every grid node ●  Worst-case current variations in every grid branch

■  Features: ●  Based on user-provided current constraints (budgets) ●  Search/optimization (LP) approach for verification ●  Allows vectorless early high-level power grid verification


Current Constraints - Example

■  Local Constraints

■  Global Constraints


1 2

4 5

3

6

9 7 8

+ -

I3

I5

I2

I7 I9

Vdd

Global Constraint 1

Global Constraint 2

Voltage Drop: The RC Case

■  Define as the vector of worst-case voltage drops, at all nodes, over all transient currents in space

■  Define: shorthand notation for element-wise max:

■  Use upper-bound:


emax

i2F[v(i)] =

2

666664

max

i2F[v1(i)]

max

i2F[v2(i)]

.

.

.

max

i2F[vn(i)]

3

777775

Performance


Voltage Drop/Rise: The RLC Case


Electromigration: The Mesh Model

■  Traditional EM model is “series” ●  But power grid has

much redundancy

■  Vector-based mesh model approach ●  3-4X lifetime! ●  Can be 30-40X

■  Vectorless Mesh model approach


Chatterjee 2013, Fawaz 2013

Progress Towards Failure


Progress towards failure


Series



Series



Series



Series

Failure when v(t) > vth


Series Mesh

Results: MTF Comparisons


■  MTF estimation for the largest grid, with 1M nodes required 97 Monte Carlo iterations and 13.5 hrs.

But … there is a Problem

■  Ongoing development: ●  Electromigration verification

◆  Physical models to further reduce pessimism ●  Fast hierarchical/modular verification

◆  Boundary conditions to ensure sub-grid safety

■  But there is a fundamental issue with usability of the constraints-based approach:


The constraints are hard to specify

Constraints Generation


Alternative Approach

■  Constraints Generation (the “inverse” problem): ●  Generate circuit current constraints which, if satisfied by the

underlying circuitry, would guarantee grid safety

■  Applications: ●  Encapsulate much useful information about the grid,

captured in useful quality metrics (peak power, other) ●  Provides power budgets to drive design process, allowing

rebudgeting, or early hints for grid redesign or new floorplan ●  During low level physical design, allow local checks for block

compliance with grid safety constraints w/o grid simulation ●  Local checks in safety “islands” may be enough


Voltage Islands (RC case)

■  Typically, we find the constraints decoupled into “islands”

■  Checking of the local regions, independently

■  Parallel flow for verification


Container

■  Definition:


Safe Container

■  Rewriting the upper-bound on the exact worst-case voltage drop:

where and

■  We want to generate such that , from which and the grid is safe!

■  Definition: A container is said to be safe if:


All Safe Containers

■  Let and define the two sets:

■  Lemma: is safe for any , and: ●  All possible safe containers may be found as either specific

instances of , or as subsets of such instances.


Vth

Maximal Container

■  It’s enough to look at the set of all safe containers:

■  Define a safe container to be maximal if it’s not a subset of any other safe container.


■  We are interested in maximal containers!

All Maximal Containers

■  Theorem:


Maximal

Irreducible

Safe

Vth

Desirable Maximal Containers

■  The space of maximal safe containers represents a quality assessment for a power grid ●  What levels of current will this grid safely distribute?

■  Example: suppose the chip is expected to draw a peak power of 150W at 1V supply ●  A grid may be deemed unacceptable if no safe container for it

can be found that allows a peak total supply current of 150A

■  Design objectives must drive the choice of container!


Container Generation Algorithms

■  Peak Power Problem (P1): ●  Generate a container that

allows the largest possible peak power dissipation (instantaneous, total)

■  Uniform Current Problem (P2): ●  Generate a container that does

not severely limit the allowed supply current anywhere on the die


Algorithms

■  P1: peak power ●  One LP

■  P2: uniform budgets ●  One LP


■  We can prove that both resulting are maximal!

Performance (P1)


(Based on 65nm technology parameters and 1.1 Volt supply)

Grid Nodes Sources CPU Time Peak Power

(mW) M' LP G1 8K 500 2 sec 0.4 sec 1.7 G2 19K 1K 7 sec 1 sec 3.7 G3 33K 2K 17 sec 2 sec 6.8 G4 50K 3K 37 sec 5 sec 10 G5 113K 7K 3 min 10 sec 22 G6 201K 13K 9 min 28 sec 41 G7 312K 19K 22 min 57 sec 60 G8 449K 28K 44 min 2 min 85 G9 1M 63K 3.6 hr 9 min 198

Power Density (P1)


0 25 50 75 100 125Number of Windows

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

µ = 1.73 mA/cm2

σ = 0.8 mA/cm2

(G4)

Performance (P2)


Grid Nodes Sources CPU Time

Radius (uA) M' LP

G1 8K 500 2 sec 0.7 sec 1.8 G2 19K 1K 7 sec 2 sec 2.1 G3 33K 2K 17 sec 3 sec 1.5 G4 50K 3K 37 sec 6 sec 1.8 G5 113K 7K 3 min 20 sec 1.4 G6 201K 13K 9 min 40 sec 2.1 G7 312K 19K 22 min 1 min 2.0 G8 449K 28K 44 min 2 min 1.6 G9 1M 63K 3.6 hr 5 min 1.9

Power Density (P2)



0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

µ = 1.3 mA/cm2

σ = 0.2 mA/cm2

(G4)

Combined Objective (P3)

■  A combined objective gives the best of both worlds:

■  We can prove that the resulting is maximal! F. N. Najm Challenges in Power Grid 41

0 5 10 15I1 (mA)

0

5

10

15

I 2(m

A)

Performance (P3)


Grid Nodes Sources CPU Time

Peak Power (mW) Radius (uA) M' LP G1 8K 500 2 sec 2 sec 1.7 1.7 G2 19K 1K 7 sec 8 sec 3.4 2.0 G3 33K 2K 17 sec 17 sec 6.4 1.4 G4 50K 3K 37 sec 29 sec 5.6 1.8 G5 113K 7K 3 min 2 min 22 1.4 G6 201K 13K 9 min 5 min 37 2.0 G7 312K 19K 22 min 8 min 55 2.0 G8 449K 28K 44 min 15 min 84 1.6 G9 1M 63K 3.6 hr 56 min 184 1.9

Power Density (P3)



0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

µ = 1.56 mA/cm2

σ = 0.46 mA/cm2

(G4)

Conclusion

■  Physical design challenges in the power grid relate to impact on voltage drop/rise and electromigration ●  Predicting these effects is hard, due to stimulus uncertainty ●  Given budgets (constraints), there are ways to overcome the

uncertainty, but still expensive and under development ■  Constraints generation is possible and practical, and

is a rich area of study, previously unexplored ●  Quality metrics for the power grid provide a rigorous

approach for early grid design/planning ●  Voltage drop-aware placement and routing?

■  Future work: ●  Automatic safe grid generation, along with constraints?


Date post:	19-Apr-2018
Category:	Documents
Upload:	vulien
View:	222 times
Download:	3 times

Physical Design Challenges in the Chip Power Distribution ... · Physical Design Challenges in the...

Documents