Physical+ Interface Board OS81118 Optical/MediaLB 6-Pin ...

2015 Microchip Technology Inc. DS60001385A

Physical+ Interface Board OS81118Optical/MediaLB® 6-Pin

User’s Guide

DS60001385A-page 2 2015 Microchip Technology Inc.

Information contained in this publication regarding deviceapplications and the like is provided only for your convenience andmay be superseded by updates. It is your responsibility to ensurethat your application meets with your specifications. MICROCHIPMAKES NO REPRESENTATIONS OR WARRANTIES OF ANYKIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL,STATUTORY OR OTHERWISE, RELATED TO THEINFORMATION, INCLUDING BUT NOT LIMITED TO ITSCONDITION, QUALITY, PERFORMANCE, MERCHANTABILITYOR FITNESS FOR PURPOSE. Microchip disclaims all liabilityarising from this information and its use. Use of Microchip devicesin life support and/or safety applications is entirely at the buyer’srisk, and the buyer agrees to defend, indemnify and hold harmlessMicrochip from any and all damages, claims, suits, or expensesresulting from such use. No licenses are conveyed, implicitly orotherwise, under any Microchip intellectual property rights unlessotherwise stated.

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.

QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV

== ISO/TS 16949 ==

Trademarks

The Microchip name and logo, the Microchip logo, dsPIC,FlashFlex, flexPWR, JukeBlox, KEELOQ, KEELOQ logo, Kleer,LANCheck, MediaLB, MOST, MOST logo, MPLAB, OptoLyzer,PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC, SST, SSTLogo, SuperFlash and UNI/O are registered trademarks ofMicrochip Technology Incorporated in the U.S.A. and othercountries.

The Embedded Control Solutions Company and mTouch areregistered trademarks of Microchip Technology Incorporated inthe U.S.A.

Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo,CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit SerialProgramming, ICSP, Inter-Chip Connectivity, KleerNet, KleerNetlogo, MiWi, motorBench, MPASM, MPF, MPLAB Certified logo,MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient CodeGeneration, PICDEM, PICDEM.net, PICkit, PICtail, RightTouchlogo, REAL ICE, SQI, Serial Quad I/O, Total Endurance, TSHARC,USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, andZENA are trademarks of Microchip Technology Incorporated in theU.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated inthe U.S.A.

Silicon Storage Technology is a registered trademark of MicrochipTechnology Inc. in other countries.

GestIC is a registered trademark of Microchip TechnologyGermany II GmbH & Co. KG, a subsidiary of Microchip TechnologyInc., in other countries.

All other trademarks mentioned herein are property of theirrespective companies.

© 2015, Microchip Technology Incorporated, Printed in the U.S.A.,All Rights Reserved.

ISBN: 978-1-5224-0063-9

PHYSICAL+ INTERFACE BOARDOS81118 OPTICAL/MEDIALB 6-PIN

USER’S GUIDE

Table of Contents

Preface ........................................................................................................................... 5Introduction............................................................................................................ 5

Intended Use ......................................................................................................... 5

Scope of Delivery .................................................................................................. 6

Document Layout .................................................................................................. 6

Term Definitions .................................................................................................... 6

Recommended Reading........................................................................................ 7

Customer Support ................................................................................................. 7

Document Revision History ................................................................................... 7

Chapter 1. Introduction1.1 Product Features ............................................................................................ 91.2 Block Diagram ................................................................................................ 9

Chapter 2. Board Details2.1 Measurement Connector and Interface to Main Board Connector ............... 11

2.1.1 Electrical Characteristics ........................................................................... 12

2.2 Configuration/Debug Header Connector ...................................................... 122.3 FOT 2+0 (oPHY) .......................................................................................... 122.4 Mini-USB Connector ..................................................................................... 122.5 Activity LED .................................................................................................. 12

Chapter 3. Assembly Plan3.1 Top View ...................................................................................................... 133.2 Bottom View ................................................................................................. 14

Chapter 4. Mechanical Drawing4.1 Top View ...................................................................................................... 154.2 Bottom View ................................................................................................. 16

Chapter 5. Schematics ................................................................................................ 17

Worldwide Sales and Service .................................................................................... 28

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USER’S GUIDE

Preface

INTRODUCTION

This chapter contains general information that will be useful to know before using the Physical+ Interface Board OS81118 Optical/MediaLB 6-Pin (in the following abbreviated as Phy+ Interface Board). Topics discussed in this chapter include:

• Intended Use

• Scope of Delivery

• Document Layout

• Term Definitions

• Recommended Reading

• Customer Support

• Document Revision History

INTENDED USE

This Microchip product is intended to be used for developing, testing, or analyzing MOST® based multimedia products and systems by persons with experience in devel-oping multimedia devices.

NOTICE TO CUSTOMERS

All documentation becomes dated, and this manual is no exception. Microchip tools and documentation are constantly evolving to meet customer needs, so some actual dialogs and/or tool descriptions may differ from those in this document. Please refer to our web site (www.microchip.com) to obtain the latest documentation available.

Documents are identified with a “DS” number. This number is located on the bottom of each page, in front of the page number. The numbering convention for the DS number is “DSXXXXXA”, where “XXXXX” is the document number and “A” is the revision level of the document.

Note: The operation of this Microchip product is only admitted with original Micro-chip devices.Do not interfere with the product's original state. Otherwise user safety, faultless operation and electromagnetic compatibility are not guaranteed.To avoid electric shocks and short circuits use this device only in an appro-priate environment.This open device may exceed the limits of electromagnetic interference. Electromagnetic compatibility can be only achieved if the equipment is built into an appropriate housing.



SCOPE OF DELIVERY

This product is delivered with the Physical+ Interface Board OS81118 Optical/MediaLB 6-Pin. The product can be identified by the label affixed on the bottom side of the board. The first five digits represent the part number.

Check your shipment for completeness.If you have any complaints, direct them to your local Microchip sales and service office, listed on the last page of this document. Providing the delivery note number eases the handling.

DOCUMENT LAYOUT

This user’s guide describes how to use the Phy+ Interface Board. The document is organized as follows:

• Chapter 1, Introduction – This chapter introduces the Phy+ Interface Board. It pro-vides an overview about the product features, shows the main parts of the board and a hardware structure example.

• Chapter 2, Board Details – This chapter describes the pin-outs of the board connec-tors. In addition it explains jumper settings and LED states.

• Chapter 3, Assembly Plan – This chapter shows the top and bottom view of the assembly plan.

• Chapter 4, Mechanical Drawing – This chapter shows the mechanical dimensions of the board (top and bottom view), including connectors and further peripherals.

• Chapter 5, Schematics – This chapter shows the schematics.

TERM DEFINITIONS

This user’s guide uses the following term definitions:

Term Description

CNx Connector x

GND Ground

I²C Inter-Integrated Circuit

I²S™ Inter-IC Sound

INIC Intelligent Network Interface Controller

LED Light Emitting Diode

MediaLB Media Local Bus, an open standard from Microchip for inter-chip multime-dia communication

MOST Media Oriented System Transport

NC Not Connected

oPHY Optical physical layer

SPI Serial Peripheral Interface

USB Universal Serial Bus


Preface

RECOMMENDED READING

This user’s guide describes how to use the Phy+ Interface Board. Other useful documents are listed below. To obtain documents, contact: [email protected].

[1] OS81118 Hardware Data Sheet

[2] OS81118 INIC API User’s Guide

CUSTOMER SUPPORT

Users of Microchip products can receive assistance through several channels:

• Distributor or Representative

• Local Sales Office

• Field Application Engineer (FAE)

• Technical Support

Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document.

Technical support is available through [email protected].

DOCUMENT REVISION HISTORY

Revision A (December 2015)

• Initial release of this document.


mailto:[email protected]



NOTES:



USER’S GUIDE

Chapter 1. Introduction

1.1 PRODUCT FEATURES

The product features of the Phy+ Interface Board are as follows:

• Detached interface between application hardware and MOST network

• Supports a MOST network speed grade of 150 Mbits/s

• Available for optical physical layer (oPHY) applications

• Fully encapsulated kernel hardware

• Common and standard inter-board connector

- Connects to application hardware

- Serves as measurement connector

• Configuration/Debug Header Connector

• Lock detection

• Offers connection capabilities to the following ports and interfaces:

- I2C port

- Two Streaming ports (I2S): Streaming port A and Streaming port B

- MediaLB 6-Pin port

- Universal Serial Bus (USB) port

1.2 BLOCK DIAGRAM

Figure 1-1 gives an overview of the Phy+ Interface Board’s main components.

FIGURE 1-1: BLOCK DIAGRAM

Mea

sure

men

t Con

nect

or/

Inte

rface

to M

ain

Boa

rd C

onne

ctor

Configuration/Debug Header

ConnectorPhy

sica

l Int

erfa

ce C

onne

ctor

Physical LayerCircuit



As depicted in the figure below, the Phy+ Interface Board serves as an interface between the customer application hardware (specified as ‘Application’ in Figure 1-2) and the MOST150 network. The Phy+ Interface Board can be simply plugged on the application hardware via the inter-board connector CN8, see Section 2.1.

FIGURE 1-2: HARDWARE STRUCTURE EXAMPLE

Network Connector

Phy+ Interface Board

Application

MOST®

Network



USER’S GUIDE

Chapter 2. Board Details

2.1 MEASUREMENT CONNECTOR AND INTERFACE TO MAIN BOARD CONNECTOR

Measurement Connector CN15 (see Figure 3-1): Samtec QSH-020-01-L-D-DP-A

Interface to Main Board Connector CN8 (see Figure 3-2): Samtec QTH-020-01-L-D-DP-A

Connector CN15 is placed on the top side of the Phy+ Interface Board and can be used for measurement purposes. Connector CN8, placed on the bottom side of the Phy+ Interface Board, is used as interface to connector CN15, mounted on the customer application hardware.

CN15 and CN8 have the same pin assignment.

FIGURE 2-1: MEASUREMENT AND INTERFACE TO MAIN BOARD CONNECTOR

1 MLBSN 2 SCKA

3 MLBSP 4 Reserved

5 ID_SDA 6 FSYA

7 ID_SCL 8 Reserved

9 MLBDN 10 RMCK

11 MLBDP 12 Reserved

13 ID_A0 14 SRXA1

15 ID_A1 16 SRXB0

17 MLBCN 18 SRXA0

19 MLBCP 20 SRXB1

21 PS0 22 PS1

23 STATUS 24 PWROFF

25 RST 26 RSOUT

27 ERR/BOOT 28 Reserved

29 TCK/DSCL 30 TMS

31 TDO/DINT 32 TDI/DSDA

33 SCL 34 INT

35 SDA 36 Reserved

37 3.3 V switched 38 3.3 V continuous

39 3.3 V switched 40 Reserved* 4k7 pull-up resistors on board,

see Figure 5-6.

Legend:

MediaLB 6-Pin Port

Streaming Port A

Streaming Port B

I2C Port*

RMCK Port

Debug Port

Board ID

Power/Power Management

Miscellaneous

Reserved



2.1.1 Electrical Characteristics

2.2 CONFIGURATION/DEBUG HEADER CONNECTOR

Configuration/Debug Header Connector CN10 (see Figure 3-1): Molex 87832-1420

2.3 FOT 2+0 (oPHY)

The Phy+ Interface Board can be connected to the MOST150 network via a 2+0 con-nector from Tyco (see Figure 3-1).

2.4 MINI-USB CONNECTOR

The Phy+ Interface Board can be connected to USB via the Mini-USB connector CN3 (see Figure 3-1).

2.5 ACTIVITY LED

The activity LED (see Figure 3-1) indicates different activity states.

Parameter Min. Typ. Max. Unit

3.3 V continuous 30 mA

3.3 V 3.135 3.465 V

3.3 V 380 mA

Pin Description

1, 3, 13 NC

2, 5, 10 GND

4 Error/Boot

6, 9 3.3 V

7 TDI/DSDA

8 TCK/DSCL

11 TDO/DINT

12 Reset

14 TMS

Color Activity State

OFF No activity

Red Activity, but no lock

Green Lock



USER’S GUIDE

Chapter 3. Assembly Plan

3.1 TOP VIEWFIGURE 3-1: ASSEMBLY PLAN – TOP VIEW



3.2 BOTTOM VIEWFIGURE 3-2: ASSEMBLY PLAN – BOTTOM VIEW



USER’S GUIDE

Chapter 4. Mechanical Drawing

4.1 TOP VIEWFIGURE 4-1: MECHANICAL DRAWING – TOP VIEW



4.2 BOTTOM VIEWFIGURE 4-2: MECHANICAL DRAWING – BOTTOM VIEW



USER’S GUIDE

Chapter 5. Schematics

The following pages show the schematics.

Note: Schematics and layouts are provided "as is" without any warranty as an example application, and are not guaranteed to be suitable for any particu-lar application. Any design using this information should be tested over the full environmental stress conditions of the intended application. For appli-cation information, schematic and layout issues contact: [email protected].



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1

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FIGURE 5-1: MAIN SHEET

USB

BoardConnectorMOST

Network

BoardID PROM

LEDindicators

MediaLBI2SSPI

Power

MISCResetJTAGI2C

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URE 5-2: MEDIALB 6-PIN, I²S AND SPI INTERFACES

I2S_CLK

I2S_SRX0

I2S_SRX1

I2S_SRX2

I2S_FSY

I2S_SRX3

MLB

MLB

MLB

MLB

MLB

MLB

3V3

3V3

1 2 R25X

1

2

R8747K

1 2 R22X

1 2 R81100R

1 2 R106 47R

1 2 R107 47R

1

2

R8447K

1 2 R23X

1 2

R11847K

1 2

R11647K

1 2 R82100R

1 2 R33X

1 2 R101 47R

1 2 R83100R

1 2 R103 47R

1 2 R104 47R

1 2 R105 47R

1 2

R4847K

1 2

R7747K

1 2

R7847K

11

13

12

40

41

42

43

44

45

3

4

5

6

7

8

14

15

16

17

18

MLBCLK

MLBDAT

MediaLB

Streamingport

SPI

FSY

SCK

MLBSIG

MLBDN

MLBSN

MLBSP

MLBDP

MLBCN

MLBCP

SRXA0

SRXA1

SRXB0

SRXB1

SDIN/GP3

SDOUT/GP4

SCLK/GP5

'SINT'/GP6

'CS'/GP7

U1-B

OS81118BF Rev D2A

INIC SPI Interface

Note:R22,23=619R 0402R25,33=1k0 0402only populated at FPGA side

INIC

Dig

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ole 3.2 mm

1 2R113X

1 2R112X

1 2R115X

1 2R114X

MP3Position pad

MP4Position pad

MP5Position pad

MP6Position pad

8

ole 3.2 mm

7

3

QTH = BottomQSH = Top

Board Connectors

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FIGURE 5-3: BOARD CONNECTORS

PowerOff_INIC

ERR/'Boot'_Debug

TMS

TCK/DSCL

'RST'_Debug

Error

'Status'_Con

Ext-TDO/'DINT'Ext-TCK/DSCL

PS0

ID_A0

ID_SDAID_SCL

ID_A1

MLB_SN

MLB_CN

'RST'_IN

MLB_CP

MLB_SP

I2C_SDAI2C_SCL

MLB_DN

Error

'Status'_Con

MLB_DP

Ext-TDO/'DINT'Ext-TCK/DSCL

PS0

ID_A0

ID_SDAID_SCL

ID_A1

MLB_SN

MLB_CN

'RST'_IN

MLB_CP

MLB_SP

I2C_SDAI2C_SCL

RMCK

I2S_SRX0

I2S_SRX1

I2S_CLK

I2S_FSY

PS1PowerOff

Ext-TMSExt-TDI/DSDA

Reserved_2

Reserved_1

Reserved_0

DBGHDR

I2S_SRX2

I2S_SRX3

'RSOUT'

I2C_'INT'

I2S_SRX0

I2S_SRX1

I2S_FSY

RMCK

PS1PowerOff

Ext-TMSExt-TDI/DSDA

Reserved_2

Reserved_1

Reserved_0

DBGHDR

I2S_SRX2

I2S_SRX3

I2S_CLK

'RSOUT'

I2C_'INT'

PowerOff

3V3

3V3

3V3

3V3

3V3cont 3V3cont

12V

3V3

1M8

H

1 2

3 4

5 6

7 8

9 10

11 12

13 14

TDI/DSDA

TDO/'DINT'

CN1087832-1420

1 2

R8X

1

2

R504K7

1

2

R564K7

1

2

R574K7

12

34

56

78

910

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

MLB_SNI2S_CLKMLB_SPReserved_0

I2S_FSYReserved_1

MLB_DNRMCKMLB_DPReserved_2

I2S_SRX1I2S_SRX2

MLB_CNI2S_SRX0MLB_CPI2S_SRX3

PS0PS1'Status'_ConPowerOff

'RST'_IN'RSOUT'Error

Ext-TCK/DSCLExt-TMSExt-TDO/'DINT'Ext-TDI/DSDA

I2C_SCLI2C_'INT'I2C_SDADBGHDR

CN8QTH-020-01-L-D-DP-A

2

1

3

DA2BAS70-06

12

TDI/DSDAExt-TDI/DSDAR122X

12

TCK/DSCLExt-TCK/DSCLR123X

12

TMSExt-TMSR124X

12

TDO/'DINT'Ext-TDO/'DINT'R125X

12

PowerOff_Debug

R127X

1

1

1

1

1MP

Hole 2.7 mm

1M7

H

12

34

56

78

910

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

MLB_DNMLB_DP

12V_CN15

CN15QSH-020-01-L-D-DP-A

1MP

Hole 2.7 mm

12

R126X 1

2

R60100K

1

2

R5947K

Debug Header

Bottom

Optional: connecting Debug-Port to Application-Interfaceconnects to

Error Pin with 1K

Top

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URE 5-4: USB CONNECTOR

1

2

3

D22RClamp0502B

12

R238

0R

1

2

C241µF

12

USB-SHLD

R237

0R

1

2

3

4

5

6 7

89

USB-SHLD

Shield

Shield

GND

VBUS

D-

D+

ID

CN3Mini USB B WR-COM - R

1 2

L12X

1 2

R252

0R

1

2

C11010nF

1 2

R10

10K

21

D16SD05.TCT

53

54

50

51

64STROBE

DATA

VBUS

USBHSIC

DM

DP

U1-COS81118BF Rev D2A

TP2TP48mil-32drill

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FIGURE 5-5: ID PROM

ID_A0

ID_SDA

ID_SCL

ID_A1

3V3

3V3

1

2R

24

4

10K

1

2

R2

45

10K

1 2 3

4

5

6

7

8

CONTROL

SCL

SDA

VCC GND

EEPROM

'WC'

A1A0 A2

U724LC024I/SN

1 2

C156

100nF

1

2

R2

46

100K

1

2

R2

47

100K

1

2

R24810K

ID PROM

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URE 5-6: MISCELLANEOUS

PowerOff_INIC

PS1

PS0

'RST_FOT'

'RST'_INIC

'RST'_Debug

I2C_SDA

I2C_SCL

I2C_'INT'

TMS

TDI/DSDA

TDO/'DINT'

TCK/DSCL

Error

RMCK

'RSOUT

ERR/'Boot'_Debug

XTO

XTI

'RST'_IN

3V3

3V3

3V3

3V3

3V3

3V3

1

2

CN

9

TS

W-1

02

-23

-F-S

1 2R32 100R

2

1

3

DA1BAS70-06

12R3647R

12R34

47R

1

2

R4210K

1

2

R1

81

00

K

1

2

R1

71

00

K

1 2R971K

1

2

R1

91

00

K

1

2

R884K7

1

2

K0

11

5R

1 2 R8647R

1 2

R201K

1 2R31 100R

1 2R30 100R

1 2R29 100R

12R3747R

1

2

R894K7

1

2

R3910K

12

C80522pF

1

2

X318.432MHZ

1

2

3

4

5

6

'Reset'

CT

VDD

SENSE

GND

'MR'

U2TPS3808G01

1

2

R4010K

1

2

C41nF

1

2

R431K8

1

2

R4110K

1

2

C6100nF

12

C80622pF

1

2

R1

21

00

K

1

2

R914K7

70

71

72

66

67

68

69

19

1

2

60

46

47

61

62

63

XTI

XTO

MISC

SCL

SDA

TMS

PS1

PS0

'RST'

ERR/'BOOT'

RMCK

PWROFF

TDO/'DINT'

TDI/DSDA

TCK/DSCL

'INT'/GP0

'RSOUT'/GP8

U1-D

OS81118BF Rev D2A

UTh=0.405V

Power OnReset Generator

Treset:1nF->6.2msec100nF->570msec10k/10k+1k8 = Vit= 3.06V = -7.27%

Note:Reset generator for FOT TXto supress short light pulsesduring transmitter power-up

Reset Inputfrom EHC

JTAG Pullupsare at sheet"6pin_Conn"

Ph

ysical+ In

terface Bo

ard O

S81118 O

ptical/M

ediaL

B 6-P

in

DS

60001385A

-page 24

2015 Microchip T

echnology Inc.

ofSheets:

Date:Release:

Engineer:

Box for Comments:

Project-number:

Project Leader:

File:

Name of Sheet:

Project:

Board number:


1V8

1V8

3V3

1

10

42792640

1

1542792640

1

1442792640

1

1342792640

7

Power

23.10.2015


V1.1.1

AIS12018

9

FIGURE 5-7: POWER

3V3INIC

1V8INIC

1V8

3V3

3V3

1V8

3V3

1V8

1

2

C4610µF

1

2

3

4

5

6

VOUT

ADJ

VIN

'SHDN'

GND

U4MCP1825T-ADJE/DC

1

2

C29

1µF

2

L

7

2

L7

1

2

R451K

10

30

48

58

9

31

49

59

37

39

55

57

56

3638

52

VDDA18

GNDA2

POWER

GNDA3

VDDUSB

RBIAS

VDD12

VDDC1

VDDC2

VDDC3

VDDC4

VDDP1

VDDP2

VDDP3

VDDP4

VDDA33_1

VDDA33_2

U1-EOS81118BF Rev D2A

2

L7

1

2

C14100nF

1

2

C28

1µF

1

2

C16100nF

1

2

C18100nF

1

2

C15100nF

1

2

C13100nF

1

2

C11100nF

1

2

C3100nF

1

2

C8100nF

1

2

C9100nF

1

2

C10100nF

1 2

R270R

1 2

R240R

1

2

C4510µF

1

2

C4410µF

12D1MBR0520-LT1G

2

L7

1

2

R4912K Thin Film

1

2

R4410K

1

2

R3833K

1

2

C4910µF

1

2

R281K

TP1TP48mil-32drill

INIC Core

Wuerth 74279214:1k@100MHz, 200mA, 1206

HSIC IO VCC

INIC Periphery

INIC Power Supply

Core Supply LDO Regulators

Power Sequencing Diodes

USB PLL

USB analog

MLB PLL

USB BiasResistor

Sch

ematics

2015

Microchip T

echnology Inc.

DS

60001385A

-page 25

FIG

ofSheets:

Date:Release:

Engineer:

Box for Comments:

Project-number:

Project Leader:

File:

Name of Sheet:

Project:

Board number:


1

R5

3

1

R5

2

8

FOT

23.10.2015


V1.1.1

AIS12018

9

URE 5-8: FOT

'Status'_FOT

3V33V3contVCC_RX

VCC_TX

VCC_TX

VCC_RX

VCC_TX

3V3cont

1

2

C39100nF

1

2

C4110µF

1

2

C3710nF

1

2

C38100nF

12

L11742792640

1

2

C4010µF

1 2

R74 100R

1 2R14

10K

1 2R13

10K

1

2

R40R

1

2

R1X

1 2

'RST_FOT'

R69

100R

1

2

R547K

1

2

R15X

1

2

DP2X

1

2

DP1X

1 2

R68 100R

1

2

C3210nF

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15 16 17 18 19 20 21 22 23 24 25 26 27

-3dB

REXT

REXT

TX D-

TX D+

GND

VCC

VCC

GND

RX D-

RX D+

VCC

Shielding

Status

'RST'

M6MOST150 2+0 Header AVAGO Rev. B-2

2

1K

2

1K

12

L7742792640

65

32

33

34

35

29

27

28

22

23

26

21

20

24

25

'Status'_INIC

NetworkTransceiver cGND

TXN

TXP

RXP

RXN

cGNDA

NC

NC

NC

NC

NC

NC

NC

NC

STATUS

U1-AOS81118BF Rev D2A

GND1TP48mil-32drill

GND2TP48mil-32drill

Z0=100 Ohm Data->

INIC Status Pinis Input

FOT Status Out:Weak Push-pull Output pin

Z0=100 Ohm <-Data

Ph

ysical+ In

terface Bo

ard O

S81118 O

ptical/M

ediaL

B 6-P

in

DS

60001385A

-page 26

2015 Microchip T

echnology Inc.

ofSheets:

Date:Release:

Engineer:

Box for Comments:

Project-number:

Project Leader:

File:

Name of Sheet:

Project:

Board number:


9

LEDs

INIC Lock LEDs Thruth table:Error Status State Color 0 0 Lock green 0 1 Boot Mode off 1 0 unlockable red 1 1 no RX light off=> Transceiver LED equations:LED green = !( Error+Status)LED red = !(!Error+Status)

23.10.2015


V1.1.1

AIS12018

9

FIGURE 5-9: LEDS

Error

'Status'_Con

'Status'_INIC

3V3

3V3cont

1 2

C42 100nF

1

2

R4710K

8

9

10

=>1

U6-CSN74LVC02AD

5

6

4

=>1

U6-BSN74LVC02AD

1 2R46

10K

1

2

R2110K

1

2

R3100K

1

2

R2

14

68

R

12

R21368R

1

2

R660R

2

3

1

14 7VCC GND

=>1

U6-ASN74LVC02AD 1

2

3

GRNRED

D3L-42WUM/1EGW

11

12

13

=>1

U6-DSN74LVC02AD

E

B

C

T1BC847C

G

D

S

'Status'_FOT

T2BSS84

1

2 R650R

1

2

R67

X1

2

R64

X

2

1

3

D7

BAS70-05

ca.19mA

Status LED Driver

ca.22mA

Schematics

NOTES:



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