Physics of Power Dissipation in CMOS

8/13/2019 Physics of Power Dissipation in CMOS

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PHYSICS OF POWER DISSIPATION MOSFET DEVICES 15 16 PHYSICS OF POWER DISSIPATION CMOS FET DEVICESallow us to simplify th e above to dropped. Thus,

Integrating twice and applying boundary conditions ep x = 0 = eps andep(x = W = 0 yields

2.19

2.21

2.20

f 3 ~ s e {3 q,,-2q,B) ) - fffFrom 2.21 and 2.22 ,

Now the charge pe r unit area in th e semiconductor Qs is the sum of thecharge pe r unit area in th e inversion layer Qi and the charge pe r unit area inthe depletion region Qd Th e charge in the depletion region is due to theacceptor atoms using an extra electron to comolete their covalent bonds.Therefore, - . -2.15

2.14~

O::;;xe{3 q,,-2q,B) and using th e first two terms in th e Taylor series expansion aboute P q,,-2 q o = 0

YJ4BCSW = q A 2.17 2.222.2.1.3 Charge in the Inversion Layer Substituting in 2.23 ,In a nrevious section n _th e total chaTire in th e s emicon d uctor . w as s een to -- , . o ; o , . . . ~ ------0- --- ---- ---------------7 . -- -------depend on the parameters of the MIS structure according to the followingrelation:

2.23

Vqss NA Qs = B s ~ s = - f e -{3q f 4>s 2{3q,B e M , - f eps -12.18

In this section we will determine th e charge in the depletion region due toth e ionized atoms left behind when the holes ar e repelled away by th epositive potential on the metal and, in tum the charge in th e inversion layer.Th e inversion of th e semiconductor surface does not begin until 4>sFo r th e range of doping concentrations used in MOSFETs and for the rangeof temperatures of interest, 9::;; f 4>B 16, t he o th er terms in 2.20 ar enegligible in comparison with the second and the fourth terms and can be

2.2.1.4 Inversion Layer ThicknessAs the next step, we will derive an approximation for the thickness of theinversion layer. This is done by assuming tha t the charge density in theinversion layer is much higher than th e density of ionic charge in the bulkand that the inversion layer is very thin. Thus aEx/ ax in the inversion layeris much greater than in th e bulk. Here, Ex ax can be approximated byconsidering the value of th e electric field at the bottom edge of the inversionlayer to be zero Figure 2.7 .

Th e concentration of electrons at some point in the semiconductor isexponentially dependent upon the potential, with the exponential constantbeing f = kT /q. This implies that th e majority of th e charge is containedwithin a distance from th e surface over which ep drops by kT/q. To illustrate,


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PHYSICS OF POWER DISSIPATION IN MOSFET DEVICES 23 24 PHYSI S OF POVaJER DfSS PP T ON N MOS FET EVI ES

Invoking the depletion approximation again, the charge in the depletionregion is simply the ionic charge, that is, p(x, y) = qNA Substituting these inthe Poisson equation,

varies decreases with y to a minimum value at the drain end. Also, Ex x, y)has a value at the insulator-semiconductor surface given by Ex O y) and goesto zero at the bottom edge of the depletion region, that is, Ex W, y) = O__ _ _ ~ _ t _ ~ I \ 1

Most Imponanny, 11 IS assumea mat dl x l dX at eacn pOlllt \x , yJ can oereplaced with the average of its value at 0, y) and at W, y) given by

Furthermore,

2.40= _ esWmdV 8;17

where V.L = Vas - Vr , Vbi is the built-in potential at the drain-substrateand substrate-source p-n junctions, and I is the characteristic lengthdefined as

~ r s c is now found by subtracting the long-channel value of s at Vr fromthe minimum of 4>. y given by E.q. 2.39 . The minimum of 4>. y is found byevaluating the right-hand side of Eq. 2.39 for a handful of values o yo< y < L, plotting and fitting a curve to them. Figure 2.9 shows thevariation of the surface potential along the channel for channel lengths of0.35 and 0.8 /Lm. For each channel length, surface potential has been plottedfor VDS = 0.05 V and VDS = 1.5 V .The surface potential of the device with L = 0.8 /Lm is seen to remainconstant over a significant portion of the channel. This characteristic becomes more pronounced in cases of longer channel lengths. The surfacepotential of the device with L = 0.35 /Lm, however, does not exhibit a regionwhere its value is unvarying. The minimum surface potential value for thedevice with L = 0.35 /Lm is greater than that for the device with L = 0.8/Lm. In fact, the minimum value of the surface.potential increases withdecreasing channel length and increasing VDS

2.33

2.34

2.35

EAD,yW

E = Vr - VFB - 4>s Yox Y d

aEx EAO, y - EAW, yx W

From the condition of continuity of the electric displacement vector,

where 17 is an empirical fitting parameter and W = Wm at the onset of stronginversion. Or,

Under boundary conditions 4>9 0 = Vbi and 4>9 L = Vbi VDS the solution4>s Y to the above equation is

0.8.6.4.2

,L = .8. Vos =1.5 V- L= .8. Vos = .05 V f L =.35. Vos =1.5 V i/ L = .35. Vos = .05 V/ // i

/ i/ II / / /

: : : : ~~ = = . . ; . _ = = : : ; : _ . _ _ .

3

2

5

o

4

L .l L .....oFigure 2.9 Surface potential along the channel for two lengths.

2.37

2.36

2.38

2.39

aE aE p(x, y)- - = - ax ay 8 9

sinh YII4>s Y = V.L Vbi VDS - V.L) sinh LIIsinh [L - y lit) Vbi - V.L) sinh LII

we get


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POWER DISSIPATION IN CMOS 31 3 PHYSICS O POWER DISSIPATION IN CMOS FET DEVICES

Figure 2.12 An inverter.

Solving ~ n O = 0, ~ n t l = VDD and ~ n t 2 = 0, we obtainVT Tt l = and t2 =VDD 2

Substituting 2.51), 2.53), and 2.54) into 2.52), we get21/2 3 VT 2[ = 2 - - - V dtm n T 2 TVT/VOO}r T

2.54)

2.55)

i l iz i)Figure 2.13 Short-circuit current.

T2.56)

2.57)

2.58)

Let 0 = Vy/T t - VT; then1 = 3 j VT/VOO}r0 dOmean T ,,/2

Therefore, the short-circuit power dissipation of an unloaded inverter isp 3 T

PSC = 12 VDD VT T

Solving,Vn.It--- . t R

YDD IMu

2.52)

output load is increased. Exact analysis of the short-circuit dissipation for aloaded inverter [28] is complex The following analysis while simplifiedoffers insights into the short-circuit dissipation and gives an upper bound.For simplicity a symmetrical inverter i.e., f3N = p and VT = - VT ;Figure 2.12) and a symmetrical input signal i.e., rise time TR : fall tin{e

TF = T Figure 2.13) are considered. The input signal is also periodic withperiod equal to T During the interval from t1 to t2 the short-circuit currentincreases from 0 to Imax As, for the NMOST, VDS > Vas - VT it will be insaturation. The simple square-law formula then gives the drain current: f 3 1 2 ~ n VT2 for 0 ;S; [ :;;; [max 2.51)

Due to the assumption of the symmetry of the inverter, this current will reachits peak: when = VDD I2 and its waveform will be symmetric about thevertical axis t = t2The mean current is given by dividing by T the result of integrating theinstantaneous current from t = 0 to t = T:liT 2 3 2I m n = l t dt = T - ~ n t - VT dtT o 11,2Assuming the rising and falling portions of the input voltage waveform to belinear ramps, V

DD~ n t = 2.53T

We see from Eq. 2.58) that Psc depends upon frequency = l iT , thesupply voltage and the rise and fan times of the input signalThe short-circuit power dissipation characteristic of an inverter with a loadcapacitance CL can be studied using simulation [27]. t is seen that if theinput and the output signal have equal rise and fall times, the short-circuitdissipation is small. However, if the inverter is lightly loaded, causing outputrise and fall times that a re relatively shorte r than the input rise and falltimes, the short-circuit dissipation increases to become comparable to dynamic dissipation. Therefore, to minimize dissipation, an inverter should bedesigned in such a way so that the input rise and fall times are about equal tothe output rise and fall times.2.3.2 Dynamic DissipationFor an inverter, the average dynamic dissipation can be obtained by summingthe average dynamic dissipation in the NMOST and the PMOST Figure2.14). Assuming that the input is a square wave having a period T andthat the rise and fall times of the input are much less than the repetitionperiod, the dynamic dissipation is given by

2.59)


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POWER DISSIPATION IN MOS 35 36 PHYSICS O POWER DISSIPATION CMOS FET DEVICES

elk

tVI

V ~7\ = High I

TABLE 2 1 Average Gate Capacitance of a MOS Transistor in the Three Regionsof OperationOperation Region CgCutoff r\ ox rr .LJ XX V uTriode 0 C WL exx C WL exxSaturation 0 2/3 CoxWLexx 0

The overall load capacitance is modeled as the parallel combination offour capacitances the gat e capacitance C , the overlap capacitance C thediffusion capacitance Cdiff and the interccfnnect capacitance Cint OV

2.67)

2.68)

2 3 3 The Gate CapacitanceThe gate capacitance is the largest of the four components. It is theequivalent capacitance of three capacitors in parallel and is given by

where Cgb is the sum of the gate-to-bulk capacitances of the two MOSTs inthe load inverter and the other two capacitances are the sum of the gate-todrain/source capacitances of the MOSTs in the load inverter. The value ofan individual component capacitance depends on the region of operation ofthe respective MOST. The values are given in Table 2.l.The W in Table 2 1 is the sum of the channel widths of the PMOST andthe NMOST of the load inverter, Cox = Boxltox and L is the identicalchannel width of the two MOSTs.2 3 3 2 The Overlap CapacitanceThe overlap capacitances arise from the unwanted lateral diffusion of thedrain and source impurities into the channel region under the gate Figure2.18). The gate-drain overlap capacitances of the driver inverter need to beconsidered in addition to the load inverter. Because of the Miller effect, thegate-drain overlap capacitances of the driver invert er app ear to b e lar gerthan a similar sized load inverter. The gate-drain overlap capacitances of theMOSTs in the driver inverter are given by

whereas the gate-to-source/ drain capacitances or the MOSTs in the loadinverter are given by

Figure 2 16 Charge sharing in dynamic circuitsEnergy transferred during a complete cycle, E101 comprising of a prechargeand an evaluate phase, is given by

2 3 3 The Load CapacitanceI t can be observed from 2.60) and 2.66) that t he power dissipation of aCMOS inverter is directly proportional to the load capacitance. Besides gatesthat a re in-chip output buffers and that drive chip output and input pinsthrough printed wiring board PWB) interconnects, all gates in the interior ofa chip only drive o th er gates through on-chip interconnects. The loadcapacitance of such a gate comprises o f a number of parasitic componentssome of which are shown in Figure 2.17.

Figure 2 17 An inverter driving another and its model on the right of the arrow)forcomputing the parasitic load capacitance2.69)


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5 PHYSICS OF POWER DISSIPATION IN CMOS FET DEVICES


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[28] L. Bisdounis, O. Koufopavlou, and S. Nikolaidis, Accurate Evaluation ofCMOS Short Circuit Power Dissipation for Short Channel Devices, Interna-tional Symposium on Low Power Electronics Design Monterey, CA, Aug.1996 pp. 181-192.[29] M. Nagata, Limitations, Innovations and Challenges of Circuits and Devicesinto a Half Micrometer and Beyond, I Solid State Circuits vol. 27pp. 465-472, 1992.[30] C. Hu, MOSFET Scaling in the Next Decade and Beyond, Proc. InternationalSemiconductor Device Research Symp. Semicon. Int. pp. 105-114, June 1994.[31] J. D. Meindl, Low Power Microelectronics: Retrospect and Prospect, Proc.IEEE vol. 83 no. 4, pp. 619-635, 1995.[32] Y. Taur et aI. High-Performance 0.1 mm CMOS Devices with 1.5 V PowerSupply, I M Tech. Dig. vol. 38 pp. 127-130, 1993.[33] J. D. Meindl, Theoretical, Practical, and Analogical Limits in ULSI I MTech. Dig. vol. 28 pp. 8-13, 1983.[34] A. P. Chandrakasan et aI., Low Power CMOS Digital Design, ISolid State Circuits vol. 27 pp. 473-484, 1992.[35] K N. Ratnakumer et al., Short-Channel MOSFET Threshold Voltage Model,IEEE Solid State Circuits vol. SC-17 pp. 937-947, 1982.[36] Agarwla et aI. Opportunities for Scaling MOSFETs for GSI, roc

ESS ER 1993 voL 25 pp. 919-926, September 1993[37] C. Fiegna et aI. New Scaling Method for 0.1-0.25 Micron MOSFET, Symp.VLSI Tech. Dig. pp. 33-34, May 1993.[38} M. Ono et aI. Sub-59 nm Gate Length N-MOSFET s with 10 nm Phosphorous

SI Junctions, IEDM Tech. Dig. vol. 38 pp. 119-121, 1993.[39] D. Hisamoto et aI A Funy Depleted Lean Channel Transistor DELTA aNovel Vertical Ultrathin SOl MOSFET, IEEE Electron. Devices Lett. vol. 11pp. 36-38, 1990.[40] D. J. Frank e t aI. Monte-Carlo Simulation of a 30 nm Dual Gate MOSFET:How Short Can Si Go? IEDM Tech. Dig. vol. 37 pp. 553-556, 1992.[41] T. Tanaka et aI. Ultrafast Low Power Operation of P N Double-GateSOl MOSFETS, Symp. VLSI Tech. Dig. pp. 11-12,1994.[42] R M. Swanson et aI. Ion-Implanted Complimentary MOS Transistors inLow-Voltage Circuits, I Solid State Circuits vol. SC-7, pp. 146-152;

1972.[43] Bakoglu, Circuits Interconnections and Packaging for VLSI Addison-Wesley,Reading, MA pp. 198-200, 1990.[44] H. S. Stone et aI. Computer Architecture in the 1990s, I Computer vol.24 pp. 30-38, Sept. 1991.[45] B. S. Landrum and R L. Russo, On Pin Versus Block Relationship forPartitioning of Logic Graphs, IEEE Trans. on Computers vol. C-20 pp.1469-1479, Dec. 1971.[46] A. Masaki, Possibilities of Deep Submicrometer CMOS for Very High-SpeedComputer Logic, Proc. IEEE vol. 81 pp. 1311-1324, 1993.[47] M. Shoji, CMOS Digital Circuit Technology Prentice Hall, New Jersey, 1988.

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Physics of Power Dissipation in CMOS

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