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pi-fp-info

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Anasim π -fp Power Integrity and Energy aware SoC Floor Planning www.anasim.com Methodology Physics-based simulation with a high-degree of Abstraction Resource and Layout planning starts at Architecture Floor Planning and Energy Optimization are interlinked Floor Plan and resource use refined with synthesis iteration Benefits Floor Plan correct by design and optimized for IP & SoC Lowest possible power grid noise across the SoC Lowest possible operating voltage for minimum energy First-Si success greatly enhanced Copyright © Anasim Corporation 2006-2008. All rights reserved. Anasim Corporation, 3838 E Encinas Ave, Gilbert, AZ 85234, USA. Contact email: [email protected] What is π -fp? Novel SoC floor planning methodolgy & tool IP Core and Full-Chip layout optimization Complete, true-dynamic Power Integrity analysis Low Energy SoC design
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Page 1: pi-fp-info

Anasim π-fpPower Integrity and Energy aware SoC Floor Planning

www.anasim.com

Methodology

Physics-based simulation with a high-degree of Abstraction

Resource and Layout planning starts at Architecture

Floor Planning and Energy Optimization are interlinked

Floor Plan and resource use refined with synthesis iteration

Benefits

Floor Plan correct by design and optimized for IP & SoC

Lowest possible power grid noise across the SoC

Lowest possible operating voltage for minimum energy

First-Si success greatly enhanced

Copyright © Anasim Corporation 2006-2008. All rights reserved. Anasim Corporation, 3838 E Encinas Ave, Gilbert, AZ 85234, USA. Contact email: [email protected]

What is π -fp?

Novel SoC floor planning methodolgy & tool

IP Core and Full-Chip layout optimization

Complete, true-dynamic Power Integrity analysis

Low Energy SoC design

Page 2: pi-fp-info

Anasim π-fpPower Integrity and Energy aware SoC Floor Planning

www.anasim.com

Methodology

Differential, optimized power grid design minimizes effort

Simple Netlist input/ GUI, ECD based 10x faster simulator

Ease of dynamic results views

Benefits

Rapid ‘what-if’ analyses and resource optimization

Accurate, true-dynamic view of core, chip & system noise

Low Voltage & Energy SoC

Why π -fp?

Only tool enhancing static I*R drop with distributed I*R, L*di/dt, and C*dv/dt

Only noise propagation tool

Only tool revealing 2-D grid, system resonances

A: Analysis run on a floor plan B: Spatial Noise Distribution (dynamic)

C: Multi chip/core floor plan capture

Simulation netlist

.TRAN 200e-12

.PLOT 20

.ACC 0.0060

.PRINTNODE ALLGgrid1 0.2 0.2 0.0005 0.0080 0.030 10e-9 10e-9Igrid1 0.1 0.1 0.02 0.02 pulse.txt 1Ttline1 1 2 0.01 10e-9 100e-12 0.3Ngrid1 1 0.11 0.11

pulse.txt : Current Source

0 022E-12 0.03090169940E-12 0.05877852560E-12 0.08090169980E-12 0.095105652100E-12 0.1120E-12 0.095105652140E-12 0.080901699160E-12 0.058778525180E-12 0.030901699200E-12 0

D: SIM Simplification

Maximum noise with grid wire width, 3nf cap

0

50

100

150

200

250

300

5 10 20 30 40 50

Wire width (microns)

Noise (mv)

E: Noise Shaping

F: Resource Optimization

Copyright © Anasim Corporation 2006-2008. All rights reserved. Anasim Corporation, 3838 E Encinas Ave, Gilbert, AZ 85234, USA. Contact email: [email protected]


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