PIC16F8X - 18-pin Flash/EEPROM 8-Bit Microcontrollers - 30430c

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1998 Microchip Technology Inc. DS30430C-page 1

Devices Included in this Data Sheet:

PIC16F83

PIC16F84

PIC16CR83

PIC16CR84

Extended voltage range devices available

(PIC16LF8X, PIC16LCR8X)

High Performance RISC CPU Features:

Only 35 single word instructions to learn

All instructions single cycle except for program

branches which are two-cycle

Operating speed: DC - 10 MHz clock inputDC - 400 ns instruction cycle

14-bit wide instructions

8-bit wide data path

15 special function hardware registers

Eight-level deep hardware stack

Direct, indirect and relative addressing modes

Four interrupt sources:

- External RB0/INT pin

- TMR0 timer overflow

- PORTB interrupt on change

- Data EEPROM write complete

1000 erase/write cycles Flash program memory

10,000,000 erase/write cycles EEPROM data mem-

ory

EEPROM Data Retention > 40 years

Peripheral Features:

13 I/O pins with individual direction control

High current sink/source for direct LED drive

- 25 mA sink max. per pin

- 20 mA source max. per pin

TMR0: 8-bit timer/counter with 8-bit

programmable prescaler

Pin Diagrams

Special Microcontroller Features:

In-Circuit Serial Programming (ICSP) - via two

pins (ROM devices support only Data EEPROM

programming)

Power-on Reset (POR)

Power-up Timer (PWRT)

Oscillator Start-up Timer (OST)

Watchdog Timer (WDT) with its own on-chip RC

oscillator for reliable operation

Code-protection

Power saving SLEEP mode

Selectable oscillator options

CMOS Flash/EEPROM Technology:

Low-power, high-speed technology

Fully static design

Wide operating voltage range:

- Commercial: 2.0V to 6.0V

- Industrial: 2.0V to 6.0V

Low power consumption:

- < 2 mA typical @ 5V, 4 MHz

- 15 A typical @ 2V, 32 kHz- < 1 A typical standby current @ 2V

Device

Program

Memory

(words)

Data

RAM

(bytes)

Data

EEPROM

(bytes)

Max.

Freq

(MHz)

PIC16F83 512 Flash 36 64 10

PIC16F84 1 K Flash 68 64 10

PIC16CR83 512 ROM 36 64 10

PIC16CR84 1 K ROM 68 64 10

RA1

RA0

OSC1/CLKIN

OSC2/CLKOUT

VDD

RB7

RB6

RB5

RB4

RA2

RA3

RA4/T0CKI

MCLR

VSS

RB0/INT

RB1

RB2

RB3

1

2

3

4

5

6

7

8

9

18

17

16

15

14

13

12

11

10

PDIP, SOIC

PIC16F8X

PIC16CR8X

PIC16F8X18-pin Flash/EEPROM 8-Bit Microcontrollers


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PIC16F8X

DS30430C-page 2 1998 Microchip Technology Inc.

Table of Contents

1.0 General Description ...................................................................................................................................................................... 3

2.0 PIC16F8X Device Varieties .......................................................................................................................................................... 5

3.0 Architectural Overview.................................................................................................................................................................. 7

4.0 Memory Organization ................................................................................................................................................................. 11

5.0 I/O Ports...................................................................................................................................................................................... 21

6.0 Timer0 Module and TMR0 Register............................................................................................................................................ 27

7.0 Data EEPROM Memory.............................................................................................................................................................. 33

8.0 Special Features of the CPU ...................................................................................................................................................... 379.0 Instruction Set Summary ............................................................................................................................................................ 53

10.0 Development Support................................................................................................................................................................. 69

11.0 Electrical Characteristics for PIC16F83 and PIC16F84.............................................................................................................. 73

12.0 Electrical Characteristics for PIC16CR83 and PIC16CR84........................................................................................................ 85

13.0 DC & AC Characteristics Graphs/Tables.................................................................................................................................... 97

14.0 Packaging Information.............................................................................................................................................................. 109

Appendix A: Feature Improvements - From PIC16C5X To PIC16F8X .......................................................................................... 113

Appendix B: Code Compatibility - from PIC16C5X to PIC16F8X.................................................................................................. 113

Appendix C: Whats New In This Data Sheet................. ................ ............... ............... ................. ................ ............... ............... ... 114

Appendix D: Whats Changed In This Data Sheet ......................................................................................................................... 114

Appendix E: Conversion Considerations - PIC16C84 to PIC16F83/F84 And PIC16CR83/CR84.................................................. 115

Index .............. .................. ............... ............... ............... .................. ............... ............... ............... .................. ............... ............... ..... 117

On-Line Support........ ............... ................ ............... ................. ............... ................ ............... ............... ................. ................ ............ 119

Reader Response ............... ............... ................. ............... ................ ............... ................. ............... ................ ............... ............... ... 120

PIC16F8X Product Identification System.............. ............... ............... .................. ............... ............... ............... .................. .............. 121

Sales and Support.................. ................ ............... ............... ................. ................ ............... ............... ............... .................. .............. 121

To Our Valued CustomersWe constantly strive to improve the quality of all our products and documentation. We have spent a great deal of

time to ensure that these documents are correct. However, we realize that we may have missed a few things. If you

find any information that is missing or appears in error, please use the reader response form in the back of this data

sheet to inform us. We appreciate your assistance in making this a better document.
http://c8x_cov.pdf/http://c8x_cov.pdf/


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PIC16F8X


TABLE 1-1 PIC16F8X FAMILY OF DEVICES

PIC16F83 PIC16CR83 PIC16F84 PIC16CR84

ClockMaximum Frequency

of Operation (MHz)

10 10 10 10

Flash Program Memory 512 1K

Memory

EEPROM Program Memory

ROM Program Memory 512 1K

Data Memory (bytes) 36 36 68 68

Data EEPROM (bytes) 64 64 64 64

Peripherals Timer Module(s) TMR0 TMR0 TMR0 TMR0

Features

Interrupt Sources 4 4 4 4

I/O Pins 13 13 13 13

Voltage Range (Volts) 2.0-6.0 2.0-6.0 2.0-6.0 2.0-6.0

Packages 18-pin DIP,

SOIC

18-pin DIP,

SOIC

18-pin DIP,

SOIC

18-pin DIP,

SOIC

All PICmicro Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current capa-

bility. All PIC16F8X Family devices use serial programming with clock pin RB6 and data pin RB7.


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PIC16F8X


2.0 PIC16F8X DEVICE VARIETIES

A variety of frequency ranges and packaging options

are available. Depending on application and production

requirements the proper device option can be selected

using the information in this section. When placing

orders, please use the PIC16F8X Product

Identification System at the back of this data sheet to

specify the correct part number.There are four device types as indicated in the device

number.

1. F, as in PIC16F84. These devices have Flash

program memory and operate over the standard

voltage range.

2. LF, as in PIC16LF84. These devices have Flash

program memory and operate over an extended

voltage range.

3. CR, as in PIC16CR83. These devices have

ROM program memory and operate over the

standard voltage range.

4. LCR, as in PIC16LCR84. These devices have

ROM program memory and operate over anextended voltage range.

When discussing memory maps and other architectural

features, the use of F and CR also implies the LF and

LCR versions.

2.1 Flash Devices

These devices are offered in the lower cost plastic

package, even though the device can be erased and

reprogrammed. This allows the same device to be used

for prototype development and pilot programs as well

as production.

A further advantage of the electrically-erasable Flash

version is that it can be erased and reprogrammed in-

circuit, or by device programmers, such as Microchip's

PICSTARTPlus or PRO MATEII programmers.

2.2 Quick-Turnaround-Production (QTP)Devices

Microchip offers a QTP Programming Service for

factory production orders. This service is made

available for users who choose not to program a

medium to high quantity of units and whose code

patterns have stabilized. The devices have all Flash

locations and configuration options already pro-

grammed by the factory. Certain code and prototype

verification procedures do apply before productionshipments are available.

For information on submitting a QTP code, please

contact your Microchip Regional Sales Office.

2.3 Serialized Quick-Turnaround-Production (SQTP ) Devices

Microchip offers the unique programming service

where a few user-defined locations in each device are

programmed with different serial numbers. The serial

numbers may be random, pseudo-random

or sequential.

Serial programming allows each device to have a

unique number which can serve as an entry-code,

password or ID number.

For information on submitting a SQTP code, please


2.4 ROM Devices

Some of Microchips devices have a corresponding

device where the program memory is a ROM. These

devices give a cost savings over Microchips traditional

user programmed devices (EPROM, EEPROM).

ROM devices (PIC16CR8X) do not allow serialization

information in the program memory space. The usermay program this information into the Data EEPROM.

For information on submitting a ROM code, please


SM


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PIC16F8X


NOTES:


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PIC16F8X


3.0 ARCHITECTURAL OVERVIEW

The high performance of the PIC16CXX family can be

attributed to a number of architectural features

commonly found in RISC microprocessors. To begin

with, the PIC16CXX uses a Harvard architecture. This

architecture has the program and data accessed from

separate memories. So the device has a program

memory bus and a data memory bus. This improvesbandwidth over traditional von Neumann architecture

where program and data are fetched from the same

memory (accesses over the same bus). Separating

program and data memory further allows instructions to

be sized differently than the 8-bit wide data word.

PIC16CXX opcodes are 14-bits wide, enabling single

word instructions. The full 14-bit wide program memory

bus fetches a 14-bit instruction in a single cycle. A two-

stage pipeline overlaps fetch and execution of instruc-

tions (Example 3-1). Consequently, all instructions exe-

cute in a single cycle except for program branches.

The PIC16F83 and PIC16CR83 address 512 x 14 of

program memory, and the PIC16F84 and PIC16CR84

address 1K x 14 program memory. All program mem-ory is internal.

The PIC16CXX can directly or indirectly address its

register files or data memory. All special function

registers including the program counter are mapped in

the data memory. An orthogonal (symmetrical)

instruction set makes it possible to carry out any oper-

ation on any register using any addressing mode. This

symmetrical nature and lack of special optimal

situations make programming with the PIC16CXX

simple yet efficient. In addition, the learning curve is

reduced significantly.


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PIC16F8X


PIC16CXX devices contain an 8-bit ALU and working

register. The ALU is a general purpose arithmetic unit.

It performs arithmetic and Boolean functions between

data in the working register and any register file.

The ALU is 8-bits wide and capable of addition,

subtraction, shift and logical operations. Unless

otherwise mentioned, arithmetic operations are twos

complement in nature. In two-operand instructions,

typically one operand is the working register

(W register), and the other operand is a file register or

an immediate constant. In single operand instructions,

the operand is either the W register or a file register.

The W register is an 8-bit working register used for ALU

operations. It is not an addressable register.

Depending on the instruction executed, the ALU may

affect the values of the Carry (C), Digit Carry (DC), and

Zero (Z) bits in the STATUS register. The C and DC bits

operate as a borrow and digit borrow out bit,

respectively, in subtraction. See the SUBLW and SUBWF

instructions for examples.

A simplified block diagram for the PIC16F8X is shown

in Figure 3-1, its corresponding pin description is

shown in Table 3-1.

FIGURE 3-1: PIC16F8X BLOCK DIAGRAM

Flash/ROMProgramMemory

Program Counter13

ProgramBus

Instruction reg

8 Level Stack(13-bit)

Direct Addr

8

InstructionDecode &

Control

TimingGeneration

OSC2/CLKOUTOSC1/CLKIN

Power-upTimer

OscillatorStart-up Timer

Power-onReset

WatchdogTimer

MCLR VDD, VSS

W reg

ALU

MUX

I/O Ports

TMR0

STATUS reg

FSR reg

IndirectAddr

RA3:RA0

RB7:RB1

RA4/T0CKI

EEADR

EEPROMData Memory

64 x 8EEDATA

Addr Mux

RAM Addr

RAMFile Registers

EEPROM Data Memory

Data Bus

5

7

7

PIC16F84/CR841K x 14

PIC16F83/CR83512 x 14

PIC16F83/CR8336 x 8

PIC16F84/CR8468 x 8

RB0/INT

14

8

8


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PIC16F8X


TABLE 3-1 PIC16F8X PINOUT DESCRIPTION

Pin NameDIP

No.

SOIC

No.

I/O/P

Type

Buffer

TypeDescription

OSC1/CLKIN 16 16 I ST/CMOS (3) Oscillator crystal input/external clock source input.

OSC2/CLKOUT 15 15 O Oscillator crystal output. Connects to crystal or resonator in crystal

oscillator mode. In RC mode, OSC2 pin outputs CLKOUT which has

1/4 the frequency of OSC1, and denotes the instruction cycle rate.

MCLR 4 4 I/P ST Master clear (reset) input/programming voltage input. This pin is an

active low reset to the device.

PORTA is a bi-directional I/O port.

RA0 17 17 I/O TTL

RA1 18 18 I/O TTL

RA2 1 1 I/O TTL

RA3 2 2 I/O TTL

RA4/T0CKI 3 3 I/O ST Can also be selected to be the clock input to the TMR0 timer/

counter. Output is open drain type.

PORTB is a bi-directional I/O port. PORTB can be software pro-

grammed for internal weak pull-up on all inputs.

RB0/INT 6 6 I/O TTL/ST (1) RB0/INT can also be selected as an external interrupt pin.

RB1 7 7 I/O TTL

RB2 8 8 I/O TTL

RB3 9 9 I/O TTL

RB4 10 10 I/O TTL Interrupt on change pin.

RB5 11 11 I/O TTL Interrupt on change pin.

RB6 12 12 I/O TTL/ST (2) Interrupt on change pin. Serial programming clock.

RB7 13 13 I/O TTL/ST (2) Interrupt on change pin. Serial programming data.

VSS 5 5 P Ground reference for logic and I/O pins.

VDD 14 14 P Positive supply for logic and I/O pins.

Legend: I= input O = output I/O = Input/Output P = power

= Not used TTL = TTL input ST = Schmitt Trigger inputNote 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.

2: This buffer is a Schmitt Trigger input when used in serial programming mode.

3: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise.


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PIC16F8X


4.0 MEMORY ORGANIZATION

There are two memory blocks in the PIC16F8X. These

are the program memory and the data memory. Each

block has its own bus, so that access to each block can

occur during the same oscillator cycle.

The data memory can further be broken down into the

general purpose RAM and the Special Function

Registers (SFRs). The operation of the SFRs thatcontrol the core are described here. The SFRs used

to control the peripheral modules are described in the

section discussing each individual peripheral module.

The data memory area also contains the data

EEPROM memory. This memory is not directly mapped

into the data memory, but is indirectly mapped. That is,

an indirect address pointer specifies the address of the

data EEPROM memory to read/write. The 64 bytes of

data EEPROM memory have the address range

0h-3Fh. More details on the EEPROM memory can be

found in Section 7.0.

4.1 Program Memory Organization

The PIC16FXX has a 13-bit program counter capable

of addressing an 8K x 14 program memory space. For

the PIC16F83 and PIC16CR83, the first 512 x 14

(0000h-01FFh) are physically implemented

(Figure 4-1). For the PIC16F84 and PIC16CR84, the

first 1K x 14 (0000h-03FFh) are physically imple-

mented (Figure 4-2). Accessing a location above the

physically implemented address will cause a wrap-

around. For example, for the PIC16F84 locations 20h,

420h, 820h, C20h, 1020h, 1420h, 1820h, and 1C20h

will be the same instruction.

The reset vector is at 0000h and the interrupt vector is

at 0004h.

FIGURE 4-1: PROGRAM MEMORY MAPAND STACK - PIC16F83/CR83

FIGURE 4-2: PROGRAM MEMORY MAPAND STACK - PIC16F84/CR84

PC

Stack Level 1

Stack Level 8

Reset Vector

Peripheral Interrupt Vector

UserMemory

Space

CALL, RETURN

RETFIE, RETLW

13

0000h

0004h

1FFFh

1FFh

PC

Stack Level 1

Stack Level 8

Reset Vector

Peripheral Interrupt Vector

UserMemory

Space

CALL, RETURNRETFIE, RETLW

13

0000h

0004h

1FFFh

3FFh
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PIC16F8X


4.2 Data Memory Organization

The data memory is partitioned into two areas. The first

is the Special Function Registers (SFR) area, while the

second is the General Purpose Registers (GPR) area.

The SFRs control the operation of the device.

Portions of data memory are banked. This is for both

the SFR area and the GPR area. The GPR area is

banked to allow greater than 116 bytes of generalpurpose RAM. The banked areas of the SFR are for the

registers that control the peripheral functions. Banking

requires the use of control bits for bank selection.

These control bits are located in the STATUS Register.

Figure 4-1 and Figure 4-2 show the data memory map

organization.

Instructions MOVWF and MOVF can move values from

the W register to any location in the register file (F),

and vice-versa.

The entire data memory can be accessed either

directly using the absolute address of each register file

or indirectly through the File Select Register (FSR)

(Section 4.5). Indirect addressing uses the presentvalue of the RP1:RP0 bits for access into the banked

areas of data memory.

Data memory is partitioned into two banks which

contain the general purpose registers and the special

function registers. Bank 0 is selected by clearing the

RP0 bit (STATUS). Setting the RP0 bit selects Bank

1. Each Bank extends up to 7Fh (128 bytes). The first

twelve locations of each Bank are reserved for the

Special Function Registers. The remainder are Gen-

eral Purpose Registers implemented as static RAM.

4.2.1 GENERAL PURPOSE REGISTER FILE

All devices have some amount of General Purpose

Register (GPR) area. Each GPR is 8 bits wide and is

accessed either directly or indirectly through the FSR

(Section 4.5).

The GPR addresses in bank 1 are mapped to

addresses in bank 0. As an example, addressing loca-

tion 0Ch or 8Ch will access the same GPR.

4.2.2 SPECIAL FUNCTION REGISTERS

The Special Function Registers (Figure 4-1, Figure 4-2

and Table 4-1) are used by the CPU and Peripheral

functions to control the device operation. These

registers are static RAM.

The special function registers can be classified into two

sets, core and peripheral. Those associated with the

core functions are described in this section. Those

related to the operation of the peripheral features are

described in the section for that specific feature.


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PIC16F8X


FIGURE 4-1: REGISTER FILE MAP -PIC16F83/CR83

FIGURE 4-2: REGISTER FILE MAP -PIC16F84/CR84

File Address

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

2Fh

30h

7Fh

80h

81h

82h

83h

84h

85h

86h

87h

88h

89h

8Ah

8Bh

8Ch

FFhBank 0 Bank 1

Indirect addr.(1) Indirect addr.(1)

TMR0 OPTION

PCL

STATUS

FSR

PORTA

PORTB

EEDATA

EEADR

PCLATH

INTCON

36GeneralPurposeregisters(SRAM)

PCL

STATUS

FSR

TRISA

TRISB

EECON1

EECON2(1)

PCLATH

INTCON

Mappedin Bank 0

Unimplemented data memory location; read as 0.

File Address

AFh

B0h

Note 1: Not a physical register.

(accesses)

File Address

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

7Fh

80h

81h

82h

83h

84h

85h

86h

87h

88h

89h

8Ah

8Bh

8Ch

FFhBank 0 Bank 1

Indirect addr.(1) Indirect addr.(1)

TMR0 OPTION

PCL

STATUS

FSR

PORTA

PORTB

EEDATA

EEADR

PCLATH

INTCON

68GeneralPurposeregisters(SRAM)

PCL

STATUS

FSR

TRISA

TRISB

EECON1

EECON2(1)

PCLATH

INTCON

Mapped

in Bank 0

Unimplemented data memory location; read as 0.

File Address

Note 1: Not a physical register.

CFh

D0h

4Fh

50h

(accesses)


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TABLE 4-1 REGISTER FILE SUMMARY

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0Value onPower-on

Reset

Value on allother resets

(Note3)

Bank 0

00h INDF Uses contents of FSR to address data memory (not a physical register) ---- ---- ---- ----

01h TMR0 8-bit real-time clock/counter xxxx xxxx uuuu uuuu

02h PCL Low order 8 bits of the Program Counter (PC) 0000 0000 0000 0000

03h STATUS(2)

IRP RP1 RP0 TO PD Z DC C 0001 1xxx 000q quuu

04h FSR Indirect data memory address pointer 0 xxxx xxxx uuuu uuuu

05h PORTA RA4/T0CKI RA3 RA2 RA1 RA0 ---x xxxx ---u uuuu

06h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0/INT xxxx xxxx uuuu uuuu

07h Unimplemented location, read as '0' ---- ---- ---- ----

08h EEDATA EEPROM data register xxxx xxxx uuuu uuuu

09h EEADR EEPROM address register xxxx xxxx uuuu uuuu

0Ah PCLATH Write buffer for upper 5 bits of the PC(1)

---0 0000 ---0 0000

0Bh INTCON GIE EEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u

Bank 1

80h INDF Uses contents of FSR to address data memory (not a physical register) ---- ---- ---- ----

81hOPTION_REG

RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS01111 1111 1111 1111

82h PCL Low order 8 bits of Program Counter (PC) 0000 0000 0000 0000

83h STATUS (2) IRP RP1 RP0 TO PD Z DC C 0001 1xxx 000q quuu

84h FSR Indirect data memory address pointer 0 xxxx xxxx uuuu uuuu

85h TRISA PORTA data direction register ---1 1111 ---1 1111

86h TRISB PORTB data direction register 1111 1111 1111 1111

87h Unimplemented location, read as '0' ---- ---- ---- ----

88h EECON1 EEIF WRERR WREN WR RD ---0 x000 ---0 q000

89h EECON2 EEPROM control register 2 (not a physical register) ---- ---- ---- ----

0Ah PCLATH Write buffer for upper 5 bits of the PC(1)

---0 0000 ---0 0000

0Bh INTCON GIE EEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u

Legend: x = unknown, u = unchanged. - = unimplemented read as 0, q = value depends on condition.Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a slave register for PC. The contents

of PCLATH can be transferred to the upper byte of the program counter, but the contents of PC is never transferred

to PCLATH.

2: The TO and PD status bits in the STATUS register are not affected by a MCLR reset.

3: Other (non power-up) resets include: external reset through MCLR and the Watchdog Timer Reset.


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PIC16F8X


4.2.2.1 STATUS REGISTER

The STATUS register contains the arithmetic status of

the ALU, the RESET status and the bank select bit for

data memory.

As with any register, the STATUS register can be the

destination for any instruction. If the STATUS register is

the destination for an instruction that affects the Z, DC

or C bits, then the write to these three bits is disabled.These bits are set or cleared according to device logic.

Furthermore, the TO and PD bits are not writable.

Therefore, the result of an instruction with the STATUS

register as destination may be different than intended.

For example, CLRF STATUS will clear the upper-three

bits and set the Z bit. This leaves the STATUS register

as 000u u1uu (where u = unchanged).

Only the BCF, BSF, SWAPF and MOVWF instructions

should be used to alter the STATUS register (Table 9-2)

because these instructions do not affect any status bit.

FIGURE 4-1: STATUS REGISTER (ADDRESS 03h, 83h)

Note 1: The IRP and RP1 bits (STATUS) are

not used by the PIC16F8X and should be

programmed as cleared. Use of these bits

as general purpose R/W bits is NOT

recommended, since this may affectupward compatibility with future products.

Note 2: The C and DC bits operate as a borrow

and digit borrow out bit, respectively, in

subtraction. See the SUBLW and SUBWF

instructions for examples.

Note 3: When the STATUS register is the

destination for an instruction that affects

the Z, DC or C bits, then the write to these

three bits is disabled. The specified bit(s)

will be updated according to device logic

R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x

IRP RP1 RP0 TO PD Z DC C R = Readable bit

W = Writable bit

U = Unimplemented bit,

read as 0

- n = Value at POR reset

bit7 bit0

bit 7: IRP: Register Bank Select bit (used for indirect addressing)

0 = Bank 0, 1 (00h - FFh)

1 = Bank 2, 3 (100h - 1FFh)

The IRP bit is not used by the PIC16F8X. IRP should be maintained clear.

bit 6-5: RP1:RP0: Register Bank Select bits (used for direct addressing)

00 = Bank 0 (00h - 7Fh)

01 = Bank 1 (80h - FFh)

10 = Bank 2 (100h - 17Fh)

11 = Bank 3 (180h - 1FFh)

Each bank is 128 bytes. Only bit RP0 is used by the PIC16F8X. RP1 should be maintained clear.

bit 4: TO: Time-out bit

1 = After power-up, CLRWDT instruction, or SLEEP instruction

0 = A WDT time-out occurred

bit 3: PD: Power-down bit

1 = After power-up or by the CLRWDT instruction

0 = By execution of the SLEEP instruction

bit 2: Z: Zero bit

1 = The result of an arithmetic or logic operation is zero

0 = The result of an arithmetic or logic operation is not zero

bit 1: DC: Digit carry/borrow bit (for ADDWF and ADDLW instructions) (For borrow the polarity is reversed)1 = A carry-out from the 4th low order bit of the result occurred

0 = No carry-out from the 4th low order bit of the result

bit 0: C: Carry/borrow bit (for ADDWF and ADDLW instructions)

1 = A carry-out from the most significant bit of the result occurred

0 = No carry-out from the most significant bit of the result occurred

Note:For borrow the polarity is reversed. A subtraction is executed by adding the twos complement of

the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low

order bit of the source register.
http://../common/P16_inst.pdfhttp://../common/P16_inst.pdf


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4.2.2.2 OPTION_REG REGISTER

The OPTION_REG register is a readable and writable

register which contains various control bits to configure

the TMR0/WDT prescaler, the external INT interrupt,

TMR0, and the weak pull-ups on PORTB.

FIGURE 4-1: OPTION_REG REGISTER (ADDRESS 81h)

Note: When the prescaler is assigned to

the WDT (PSA = 1), TMR0 has a 1:1

prescaler assignment.

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 R = Readable bit

W = Writable bit


read as 0


bit7 bit0

bit 7: RBPU: PORTB Pull-up Enable bit

1 = PORTB pull-ups are disabled

0 = PORTB pull-ups are enabled (by individual port latch values)

bit 6: INTEDG: Interrupt Edge Select bit

1 = Interrupt on r ising edge of RB0/INT pin

0 = Interrupt on falling edge of RB0/INT pin

bit 5: T0CS: TMR0 Clock Source Select bit

1 = Transition on RA4/T0CKI pin

0 = Internal instruction cycle clock (CLKOUT)

bit 4: T0SE: TMR0 Source Edge Select bit

1 = Increment on high-to-low transition on RA4/T0CKI pin

0 = Increment on low-to-high transition on RA4/T0CKI pin

bit 3: PSA: Prescaler Assignment bit

1 = Prescaler assigned to the WDT

0 = Prescaler assigned to TMR0

bit 2-0: PS2:PS0: Prescaler Rate Select bits

000

001

010

011

100

101

110

111

1 : 21 : 41 : 81 : 161 : 321 : 641 : 1281 : 256

1 : 11 : 21 : 41 : 81 : 161 : 321 : 641 : 128

Bit Value TMR0 Rate WDT Rate


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4.2.2.3 INTCON REGISTER

The INTCON register is a readable and writable

register which contains the various enable bits for all

interrupt sources.

FIGURE 4-1: INTCON REGISTER (ADDRESS 0Bh, 8Bh)

Note: Interrupt flag bits get set when an interrupt

condition occurs regardless of the state of

its corresponding enable bit or the global

enable bit, GIE (INTCON).

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x

GIE EEIE T0IE INTE RBIE T0IF INTF RBIF R = Readable bit

W = Writable bit


read as 0


bit7 bit0

bit 7: GIE: Global Interrupt Enable bit

1 = Enables all un-masked interrupts

0 = Disables all interrupts

Note: For the operation of the interrupt structure, please refer to Section 8.5.

bit 6: EEIE: EE Write Complete Interrupt Enable bit

1 = Enables the EE write complete interrupt

0 = Disables the EE write complete interruptbit 5: T0IE: TMR0 Overflow Interrupt Enable bit

1 = Enables the TMR0 interrupt

0 = Disables the TMR0 interrupt

bit 4: INTE: RB0/INT Interrupt Enable bit

1 = Enables the RB0/INT interrupt

0 = Disables the RB0/INT interrupt

bit 3: RBIE: RB Port Change Interrupt Enable bit

1 = Enables the RB port change interrupt

0 = Disables the RB port change interrupt

bit 2: T0IF: TMR0 overflow interrupt flag bit

1 = TMR0 has overflowed (must be cleared in software)

0 = TMR0 did not overflow

bit 1: INTF: RB0/INT Interrupt Flag bit

1 = The RB0/INT interrupt occurred

0 = The RB0/INT interrupt did not occur

bit 0: RBIF: RB Port Change Interrupt Flag bit

1 = When at least one of the RB7:RB4 pins changed state (must be cleared in software)

0 = None of the RB7:RB4 pins have changed state


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4.3 Program Counter: PCL and PCLATH

The Program Counter (PC) is 13-bits wide. The low

byte is the PCL register, which is a readable and

writable register. The high byte of the PC (PC) is

not directly readable nor writable and comes from the

PCLATH register. The PCLATH (PC latch high) register

is a holding register for PC. The contents of

PCLATH are transferred to the upper byte of theprogram counter when the PC is loaded with a new

value. This occurs during a CALL, GOTO or a write to

PCL. The high bits of PC are loaded from PCLATH as

shown in Figure 4-1.

FIGURE 4-1: LOADING OF PC INDIFFERENT SITUATIONS

4.3.1 COMPUTED GOTO

A computed GOTO is accomplished by adding an offset

to the program counter (ADDWF PCL). When doing atable read using a computed GOTO method, care should

be exercised if the table location crosses a PCL memory

boundary (each 256 word block). Refer to the application

note Implementing a Table Read(AN556).

4.3.2 PROGRAM MEMORY PAGING

The PIC16F83 and PIC16CR83 have 512 words of pro-

gram memory. The PIC16F84 and PIC16CR84 have

1K of program memory. The CALL and GOTO instruc-

tions have an 11-bit address range. This 11-bit address

range allows a branch within a 2K program memory

page size. For future PIC16F8X program memory

expansion, there must be another two bits to specify

the program memory page. These paging bits comefrom the PCLATH bits (Figure 4-1). When doing a

CALL or a GOTO instruction, the user must ensure that

these page bits (PCLATH) are programmed to

the desired program memory page. If a CALL instruc-

tion (or interrupt) is executed, the entire 13-bit PC is

pushed onto the stack (see next section). Therefore,

manipulation of the PCLATH is not required for

the return instructions (which pops the PC from the

stack).

4.4 Stack

The PIC16FXX has an 8 deep x 13-bit wide hardware

stack (Figure 4-1). The stack space is not part of either

program or data space and the stack pointer is not

readable or writable.

The entire 13-bit PC is pushed onto the stack when a

CALL instruction is executed or an interrupt is acknowl-

edged. The stack is popped in the event of a

RETURN, RETLW or a RETFIE instruction execution.

PCLATH is not affected by a push or a pop operation.

The stack operates as a circular buffer. That is, after the

stack has been pushed eight times, the ninth push over-

writes the value that was stored from the first push. The

tenth push overwrites the second push (and so on).

If the stack is effectively popped nine times, the PC

value is the same as the value from the first pop.

PC

12 8 7 0

5PCLATH

PCLATH

INST with PCLas dest

ALU result

GOTO, CALL

Opcode

8

PC

12 11 10 0

11PCLATH

PCH PCL

8 7

2

PCLATH

PCH PCL

Note: The PIC16F8X ignores the PCLATH

bits, which are used for program memory

pages 1, 2 and 3 (0800h - 1FFFh). The

use of PCLATH as general purpose

R/W bits is not recommended since thismay affect upward compatibility with

future products.

Note: There are no instruction mnemonics

called push or pop. These are actions that

occur from the execution of the CALL,

RETURN, RETLW, and RETFIE instruc-

tions, or the vectoring to an interrupt

address.

Note: There are no status bits to indicate stack

overflow or stack underflow conditions.


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4.5 Indirect Addressing; INDF and FSRRegisters

The INDF register is not a physical register. Address-

ing INDF actually addresses the register whose

address is contained in the FSR register (FSR is a

pointer). This is indirect addressing.

EXAMPLE 4-1: INDIRECT ADDRESSING Register file 05 contains the value 10h

Register file 06 contains the value 0Ah

Load the value 05 into the FSR register

A read of the INDF register will return the value of

10h

Increment the value of the FSR register by one

(FSR = 06)

A read of the INDF register now will return the

value of 0Ah.

Reading INDF itself indirectly (FSR = 0) will produce

00h. Writing to the INDF register indirectly results in a

no-operation (although STATUS bits may be affected).

A simple program to clear RAM locations 20h-2Fh

using indirect addressing is shown in Example 4-2.

EXAMPLE 4-2: HOW TO CLEAR RAMUSING INDIRECT

ADDRESSINGmovlw 0x20 ;initialize pointer

movwf FSR ; to RAM

NEXT clrf INDF ;clear INDF register

incf FSR ;inc pointer

btfss FSR,4 ;all done?

goto NEXT ;NO, clear next

CONTINUE

: ;YES, continue

An effective 9-bit address is obtained by concatenating

the 8-bit FSR register and the IRP bit (STATUS), as

shown in Figure 4-1. However, IRP is not used in the

PIC16F8X.

FIGURE 4-1: DIRECT/INDIRECT ADDRESSING

Direct Addressing

RP1 RP0 6 from opcode 0 IRP 7 (FSR) 0

Indirect Addressing

bank select location select bank select location select

00 01 10 11

00h

7Fh

00h

0Bh

0Ch

2Fh (1)

30h (1)

7Fh

not used

Bank 0 Bank 1 Bank 2 Bank 3

Note 1: PIC16F83 and PIC16CR83 devices.

2: PIC16F84 and PIC16CR84 devices

3: For memory map detail see Figure 4-1.

4Fh (2)

50h (2)

Addresses

map back

to Bank 0

Data

Memory (3)

not used


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5.0 I/O PORTS

The PIC16F8X has two ports, PORTA and PORTB.

Some port pins are multiplexed with an alternate func-

tion for other features on the device.

5.1 PORTA and TRISA Registers

PORTA is a 5-bit wide latch. RA4 is a Schmitt Trigger

input and an open drain output. All other RA port pinshave TTL input levels and full CMOS output drivers. All

pins have data direction bits (TRIS registers) which can

configure these pins as output or input.

Setting a TRISA bit (=1) will make the corresponding

PORTA pin an input, i.e., put the corresponding output

driver in a hi-impedance mode. Clearing a TRISA bit

(=0) will make the corresponding PORTA pin an output,

i.e., put the contents of the output latch on the selected

pin.

Reading the PORTA register reads the status of the pins

whereas writing to it will write to the port latch. All write

operations are read-modify-write operations. So a write

to a port implies that the port pins are first read, then thisvalue is modified and written to the port data latch.

The RA4 pin is multiplexed with the TMR0 clock input.

FIGURE 5-1: BLOCK DIAGRAM OF PINS

RA3:RA0

EXAMPLE 5-1: INITIALIZING PORTACLRF PORTA ; Initialize PORTA by

; setting output

; data latches

BSF STATUS, RP0 ; Select Bank 1

MOVLW 0x0F ; Value used to

; initialize data

; direction

MOVWF TRISA ; Set RA as inputs

; RA4 as outputs

; TRISA are always

; read as 0.

FIGURE 5-2: BLOCK DIAGRAM OF PIN RA4

Note: I/O pins have protection diodes to VDD and VSS.

Databus

QD

QCK

QD

QCK

Q D

EN

P

N

WRPort

WRTRIS

Data Latch

TRIS Latch

RD TRIS

RD PORT

TTLinputbuffer

VSS

VDD

I/O pin

Databus

WRPORT

WRTRIS

RD PORT

Data Latch

TRIS Latch

RD TRIS

SchmittTriggerinputbuffer

N

VSS

RA4 pin

TMR0 clock input

Note: I/O pin has protection diodes to VSS only.

QD

QCK

QD

QCK

EN

Q D

EN


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TABLE 5-1 PORTA FUNCTIONS

TABLE 5-2 SUMMARY OF REGISTERS ASSOCIATED WITH PORTA

Name Bit0 Buffer Type Function

RA0 bit0 TTL Input/output




RA4/T0CKI bit4 ST Input/output or external clock input for TMR0.

Output is open drain type.

Legend: TTL = TTL input, ST = Schmitt Trigger input


Reset


05h PORTA RA4/T0CKI RA3 RA2 RA1 RA0 ---x xxxx ---u uuuu

85h TRISA TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 ---1 1111 ---1 1111

Legend: x = unknown, u = unchanged, - = unimplemented read as 0. Shaded cells are unimplemented, read as 0


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5.2 PORTB and TRISB Registers

PORTB is an 8-bit wide bi-directional port. The

corresponding data direction register is TRISB. A 1 on

any bit in the TRISB register puts the corresponding

output driver in a hi-impedance mode. A 0 on any bit

in the TRISB register puts the contents of the output

latch on the selected pin(s).

Each of the PORTB pins have a weak internal pull-up.A single control bit can turn on all the pull-ups. This is

done by clearing the RBPU (OPTION_REG) bit.

The weak pull-up is automatically turned off when the

port pin is configured as an output. The pull-ups are

disabled on a Power-on Reset.

Four of PORTBs pins, RB7:RB4, have an interrupt on

change feature. Only pins configured as inputs can

cause this interrupt to occur (i.e., any RB7:RB4 pin

configured as an output is excluded from the interrupt

on change comparison). The pins value in input mode

are compared with the old value latched on the last

read of PORTB. The mismatch outputs of the pins are

ORed together to generate the RB portchange interrupt.

FIGURE 5-3: BLOCK DIAGRAM OF PINSRB7:RB4

This interrupt can wake the device from SLEEP. The

user, in the interrupt service routine, can clear the

interrupt in the following manner:

a) Read (or write) PORTB. This will end the mis-

match condition.

b) Clear flag bit RBIF.

A mismatch condition will continue to set the RBIF bit.

Reading PORTB will end the mismatch condition, andallow the RBIF bit to be cleared.

This interrupt on mismatch feature, together with

software configurable pull-ups on these four pins allow

easy interface to a key pad and make it possible for

wake-up on key-depression (see AN552 in the

Embedded Control Handbook).

The interrupt on change feature is recommended for

wake-up on key depression operation and operations

where PORTB is only used for the interrupt on change

feature. Polling of PORTB is not recommended while

using the interrupt on change feature.

FIGURE 5-4: BLOCK DIAGRAM OF PINSRB3:RB0

RBPU(1)

Data Latch

From other

P

VDD

QD

CK

QD

CK

Q D

EN

Q D

EN

Data bus

WR Port

WR TRIS

Set RBIF

TRIS Latch

RD TRIS

RD Port

RB7:RB4 pins

weakpull-up

RD Port

Latch

TTLInputBuffer

Note 1: TRISB = 1 enables weak pull-up(if RBPU = 0 in the OPTION_REG register).

2: I/O pins have diode protection to VDD and VSS.

I/Opin(2)

Note 1: For a change on the I/O pin to be

recognized, the pulse width must be at

least TCY (4/fOSC) wide.

RBPU(1)

I/Opin(2)

Data Latch

P

VDD

QD

CK

QD

CK

Q D

EN

Data bus

WR Port

WR TRIS

RD TRIS

RD Port

weakpull-up

RD Port

RB0/INT

TTLInputBuffer

Schmitt TriggerBuffer

TRIS Latch

Note 1: TRISB = 1 enables weak pull-up

(if RBPU = 0 in the OPTION_REG register).2: I/O pins have diode protection to VDD and VSS.


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EXAMPLE 5-1: INITIALIZING PORTBCLRF PORTB ; Initialize PORTB by

; setting output

; data latches

BSF STATUS, RP0 ; Select Bank 1

MOVLW 0xCF ; Value used to

; initialize data

; direction

MOVWF TRISB ; Set RB as inputs

; RB as outputs

; RB as inputs

TABLE 5-3 PORTB FUNCTIONS

TABLE 5-4 SUMMARY OF REGISTERS ASSOCIATED WITH PORTB

Name Bit Buffer Type I/O Consistency Function

RB0/INT bit0 TTL/ST(1) Input/output pin or external interrupt input. Internal software

programmable weak pull-up.

RB1 bit1 TTL Input/output pin. Internal software programmable weak pull-up.



RB4 bit4 TTL Input/output pin (with interrupt on change). Internal software programmable

weak pull-up.

RB5 bit5 TTL Input/output pin (with interrupt on change). Internal software programmable

weak pull-up.

RB6 bit6 TTL/ST(2) Input/output pin (with interrupt on change). Internal software programmable

weak pull-up. Serial programming clock.

RB7 bit7 TTL/ST(2) Input/output pin (with interrupt on change). Internal software programmable

weak pull-up. Serial programming data.

Legend: TTL = TTL input, ST = Schmitt Trigger.

Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.

2: This buffer is a Schmitt Trigger input when used in serial programming mode.


Reset


06h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0/INT xxxx xxxx uuuu uuuu

86h TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 1111 1111

81hOPTION_REG

RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS01111 1111 1111 1111

Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTB.


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5.3 I/O Programming Considerations

5.3.1 BI-DIRECTIONAL I/O PORTS

Any instruction which writes, operates internally as a

read followed by a write operation. The BCF and BSF

instructions, for example, read the register into the

CPU, execute the bit operation and write the result back

to the register. Caution must be used when theseinstructions are applied to a port with both inputs and

outputs defined. For example, a BSF operation on bit5

of PORTB will cause all eight bits of PORTB to be read

into the CPU. Then the BSF operation takes place on

bit5 and PORTB is written to the output latches. If

another bit of PORTB is used as a bi-directional I/O pin

(i.e., bit0) and it is defined as an input at this time, the

input signal present on the pin itself would be read into

the CPU and rewritten to the data latch of this particular

pin, overwriting the previous content. As long as the pin

stays in the input mode, no problem occurs. However, if

bit0 is switched into output mode later on, the content

of the data latch is unknown.

Reading the port register, reads the values of the portpins. Writing to the port register writes the value to the

port latch. When using read-modify-write instructions

(i.e., BCF, BSF, etc.) on a port, the value of the port

pins is read, the desired operation is done to this value,

and this value is then written to the port latch.

A pin actively outputting a Low or High should not be

driven from external devices at the same time in order

to change the level on this pin (wired-or, wired-and).

The resulting high output current may damage the chip.

5.3.2 SUCCESSIVE OPERATIONS ON I/O

PORTS

The actual write to an I/O port happens at the end of an

instruction cycle, whereas for reading, the data must be

valid at the beginning of the instruction cycle

(Figure 5-5). Therefore, care must be exercised if a

write followed by a read operation is carried out on the

same I/O port. The sequence of instructions should besuch that the pin voltage stabilizes (load dependent)

before the next instruction which causes that file to be

read into the CPU is executed. Otherwise, the previous

state of that pin may be read into the CPU rather than

the new state. When in doubt, it is better to separate

these instructions with a NOP or another instruction not

accessing this I/O port.

Example 5-1 shows the effect of two sequential

read-modify-write instructions (e.g., BCF, BSF, etc.) on

an I/O port.

EXAMPLE 5-1: READ-MODIFY-WRITEINSTRUCTIONS ON AN

I/O PORT;Initial PORT settings: PORTB Inputs

; PORTB Outputs

;PORTB have external pull-ups and are

;not connected to other circuitry

;

; PORT latch PORT pins

; ---------- ---------

BCF PORTB, 7 ; 01pp ppp 11pp ppp

BCF PORTB, 6 ; 10pp ppp 11pp ppp

BSF STATUS, RP0 ;

BCF TRISB, 7 ; 10pp ppp 11pp ppp

BCF TRISB, 6 ; 10pp ppp 10pp ppp

;

;Note that the user may have expected the

;pin values to be 00pp ppp. The 2nd BCF

;caused RB7 to be latched as the pin value

;(high).

FIGURE 5-5: SUCCESSIVE I/O OPERATION

PC PC + 1 PC + 2 PC + 3

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

Instructionfetched

RB7:RB0

MOVWF PORTBwrite toPORTB

NOP

Port pinsampled here

NOPMOVF PORTB,W

Instructionexecuted

MOVWF PORTBwrite toPORTB

NOP

MOVF PORTB,W

PC

TPD

Note:

This example shows a write to PORTB

followed by a read from PORTB.

Note that:

data setup time = (0.25TCY - TPD)

where TCY = instruction cycle

TPD = propagation delay

Therefore, at higher clock frequencies,

a write followed by a read may be prob-

lematic.


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NOTES:


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6.0 TIMER0 MODULE AND TMR0REGISTER

The Timer0 module timer/counter has the following

features:

8-bit timer/counter

Readable and writable

8-bit software programmable prescaler Internal or external clock select

Interrupt on overflow from FFh to 00h

Edge select for external clock

Timer mode is selected by clearing the T0CS bit

(OPTION_REG). In timer mode, the Timer0 mod-

ule (Figure 6-1) will increment every instruction cycle

(without prescaler). If the TMR0 register is written, the

increment is inhibited for the following two cycles

(Figure 6-2 and Figure 6-3). The user can work around

this by writing an adjusted value to the TMR0 register.

Counter mode is selected by setting the T0CS bit

(OPTION_REG). In this mode TMR0 will increment

either on every rising or falling edge of pin RA4/T0CKI.The incrementing edge is determined by the T0 source

edge select bit, T0SE (OPTION_REG). Clearing bit

T0SE selects the rising edge. Restrictions on the exter-

nal clock input are discussed in detail in Section 6.2.

The prescaler is shared between the Timer0 Module

and the Watchdog Timer. The prescaler assignment is

controlled, in software, by control bit PSA

(OPTION_REG). Clearing bit PSA will assign the

prescaler to the Timer0 Module. The prescaler is not

readable or writable. When the prescaler (Section 6.3)

is assigned to the Timer0 Module, the prescale value

(1:2, 1:4, ..., 1:256) is software selectable.

6.1 TMR0 Interrupt

The TMR0 interrupt is generated when the TMR0

register overflows from FFh to 00h. This overflow sets

the T0IF bit (INTCON). The interrupt can be

masked by clearing enable bit T0IE (INTCON). The

T0IF bit must be cleared in software by the Timer0

Module interrupt service routine before re-enabling this

interrupt. The TMR0 interrupt (Figure 6-4) cannot wake

the processor from SLEEP since the timer is shut off

during SLEEP.

FIGURE 6-1: TMR0 BLOCK DIAGRAM

FIGURE 6-2: TMR0 TIMING: INTERNAL CLOCK/NO PRESCALER

Note 1: Bits T0CS, T0SE, PS2, PS1, PS0 and PSA are located in the OPTION_REG register.

2: The prescaler is shared with the Watchdog Timer (Figure 6-6)

RA4/T0CKI

T0SE

0

1

1

0pin

T0CS

FOSC/4

ProgrammablePrescaler

Sync withInternalclocks

TMR0 register

PSout

(2 cycle delay)

PSout

Data bus

8

Set bit T0IF

on OverflowPSAPS2, PS1, PS0

3

PC-1

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

PC

InstructionFetch

TMR0

PC PC+1 PC+2 PC+3 PC+4 PC+5 PC+6

T0 T0+1 T0+2 NT0 NT0 NT0 NT0+1 NT0+2 T0

MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W

Write TMR0executed

Read TMR0reads NT0

Read TMR0reads NT0

Read TMR0reads NT0

Read TMR0reads NT0 + 1


InstructionExecuted


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FIGURE 6-3: TMR0 TIMING: INTERNAL CLOCK/PRESCALE 1:2

FIGURE 6-4: TMR0 INTERRUPT TIMING

PC-1

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

PC

InstructionFetch

TMR0

PC PC+1 PC+2 PC+3 PC+4 PC+5 PC+6

T0 NT0+1

MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W

Write TMR0executed

Read TMR0reads NT0

Read TMR0reads NT0

Read TMR0reads NT0

Read TMR0reads NT0


T0+1 NT0

InstructionExecute

Q2Q1 Q3 Q4Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4

1 1

OSC1

CLKOUT(3)

TMR0 timer

T0IF bit(INTCON)

FEh

GIE bit(INTCON)

INSTRUCTION FLOW

PC

Instructionfetched

PC PC +1 PC +1 0004h 0005h

Instructionexecuted

Inst (PC)

Inst (PC-1)

Inst (PC+1)

Inst (PC)

Inst (0004h) Inst (0005h)

Inst (0004h)Dummy cycle Dummy cycle

FFh 00h 01h 02h

Note 1: T0IF interrupt flag is sampled here (every Q1).2: Interrupt latency = 3.25Tcy, where Tcy = instruction cycle time.

3: CLKOUT is available only in RC oscillator mode.

4

Interrupt Latency(2)

4: The timer clock (after the synchronizer circuit) which increments the timer from FFh to 00h immediately sets the T0IF bit.The TMR0 register will roll over 3 Tosc cycles later.


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6.2 Using TMR0 with External Clock

When an external clock input is used for TMR0, it must

meet certain requirements. The external clock

requirement is due to internal phase clock (TOSC)

synchronization. Also, there is a delay in the actual

incrementing of the TMR0 register after

synchronization.

6.2.1 EXTERNAL CLOCK SYNCHRONIZATION

When no prescaler is used, the external clock input is

the same as the prescaler output. The synchronization

of pin RA4/T0CKI with the internal phase clocks is

accomplished by sampling the prescaler output on the

Q2 and Q4 cycles of the internal phase clocks

(Figure 6-5). Therefore, it is necessary for T0CKI to be

high for at least 2Tosc (plus a small RC delay) and low

for at least 2Tosc (plus a small RC delay). Refer to the

electrical specification of the desired device.

When a prescaler is used, the external clock input is

divided by an asynchronous ripple counter type

prescaler so that the prescaler output is symmetrical.For the external clock to meet the sampling

requirement, the ripple counter must be taken into

account. Therefore, it is necessary for T0CKI to have a

period of at least 4Tosc (plus a small RC delay) divided

by the prescaler value. The only requirement on T0CKI

high and low time is that they do not violate the

minimum pulse width requirement of 10 ns. Refer to

parameters 40, 41 and 42 in the AC Electrical

Specifications of the desired device.

6.2.2 TMR0 INCREMENT DELAY

Since the prescaler output is synchronized with the

internal clocks, there is a small delay from the time the

external clock edge occurs to the time the Timer0

Module is actually incremented. Figure 6-5 shows the

delay from the external clock edge to the timer

incrementing.

6.3 Prescaler

An 8-bit counter is available as a prescaler for the

Timer0 Module, or as a postscaler for the Watchdog

Timer (Figure 6-6). For simplicity, this counter is being

referred to as prescaler throughout this data sheet.

Note that there is only one prescaler available which is

mutually exclusive between the Timer0 Module and the

Watchdog Timer. Thus, a prescaler assignment for the

Timer0 Module means that there is no prescaler for the

Watchdog Timer, and vice-versa.

The PSA and PS2:PS0 bits (OPTION_REG)

determine the prescaler assignment and prescale ratio.

When assigned to the Timer0 Module, all instructionswriting to the Timer0 Module (e.g., CLRF 1, MOVWF

1, BSF 1,x ....etc.) will clear the prescaler. When

assigned to WDT, a CLRWDT instruction will clear the

prescaler along with the Watchdog Timer. The

prescaler is not readable or writable.


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FIGURE 6-5: TIMER0 TIMING WITH EXTERNAL CLOCK

FIGURE 6-6: BLOCK DIAGRAM OF THE TMR0/WDT PRESCALER

Increment TMR0 (Q4)

Ext. Clock Input or

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

TMR0 T0 T0 + 1 T0 + 2

Ext. Clock/Prescaler

Output After Sampling

(Note 3)

Note 1:

2:

3:

Delay from clock input change to TMR0 increment is 3Tosc to 7Tosc. (Duration of Q = Tosc).

Therefore, the error in measuring the interval between two edges on TMR0 input = 4Tosc max.External clock if no prescaler selected, Prescaler output otherwise.

The arrows indicate where sampling occurs. A small clock pulse may be missed by sampling.

Prescaler Out (Note 2)

RA4/T0CKI

T0SE

pin

M

UX

CLKOUT (= Fosc/4)

SYNC2

CyclesTMR0 register

8-bit Prescaler

8 - to - 1MUX

MUX

M U X

WatchdogTimer

PSA

0 1

0

1

WDTtime-out

PS2:PS0

8

Note: T0CS, T0SE, PSA, PS2:PS0 are bits in the OPTION_REG register.

PSA

WDT Enable bit

M

UX

0

1 0

1

Data Bus

Set bit T0IFon overflow

8

PSAT0CS


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6.3.1 SWITCHING PRESCALER ASSIGNMENT

The prescaler assignment is fully under software

control (i.e., it can be changed on the fly during

program execution).

EXAMPLE 6-1: CHANGING PRESCALER(TIMER0WDT)

BCF STATUS, RP0 ;Bank 0

CLRF TMR0 ;Clear TMR0

; and Prescaler

BSF STATUS, RP0 ;Bank 1

CLRWDT ;Clears WDT

MOVLW bxxxx1xxx ;Select new

MOVWF OPTION_REG ; prescale valueBCF STATUS, RP0 ;Bank 0

EXAMPLE 6-2: CHANGING PRESCALER(WDTTIMER0)

CLRWDT ;Clear WDT and

; prescaler

BSF STATUS, RP0 ;Bank 1

MOVLW bxxxx0xxx ;Select TMR0, new

; prescale value

and clock source

MOVWF OPTION_REG ;

BCF STATUS, RP0 ;Bank 0

TABLE 6-1 REGISTERS ASSOCIATED WITH TIMER0

Note: To avoid an unintended device RESET, the

following instruction sequence

(Example 6-1) must be executed when

changing the prescaler assignment from

Timer0 to the WDT. This sequence must

be taken even if the WDT is disabled. To

change prescaler from the WDT to the

Timer0 module use the sequence shown in

Example 6-2.


Reset


01h TMR0 Timer0 modules register xxxx xxxx uuuu uuuu

0Bh INTCON GIE EEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 0000

81hOPTION_

REGRBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0

1111 1111 1111 1111

85h TRISA TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 ---1 1111 ---1 1111

Legend: x = unknown, u = unchanged. - = unimplemented read as 0. Shaded cells are not associated with Timer0.


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NOTES:


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7.0 DATA EEPROM MEMORY

The EEPROM data memory is readable and writable

during normal operation (full VDD range). This memory

is not directly mapped in the register file space. Instead

it is indirectly addressed through the Special Function

Registers. There are four SFRs used to read and write

this memory. These registers are:

EECON1 EECON2

EEDATA

EEADR

EEDATA holds the 8-bit data for read/write, and EEADR

holds the address of the EEPROM location being

accessed. PIC16F8X devices have 64 bytes of data

EEPROM with an address range from 0h to 3Fh.

The EEPROM data memory allows byte read and write.

A byte write automatically erases the location and

writes the new data (erase before write). The EEPROM

data memory is rated for high erase/write cycles. The

write time is controlled by an on-chip timer. The write-

time will vary with voltage and temperature as well as

from chip to chip. Please refer to AC specifications for

exact limits.

When the device is code protected, the CPU may

continue to read and write the data EEPROM memory.

The device programmer can no longer access

this memory.

7.1 EEADR

The EEADR register can address up to a maximum of

256 bytes of data EEPROM. Only the first 64 bytes of

data EEPROM are implemented.

The upper two bits are address decoded. This means

that these two bits must always be '0' to ensure that the

address is in the 64 byte memory space.

FIGURE 7-1: EECON1 REGISTER (ADDRESS 88h)

U U U R/W-0 R/W-x R/W-0 R/S-0 R/S-x

EEIF WRERR WREN WR RD R = Readable bit

W = Writable bit

S = Settable bit


read as 0


bit7 bit0

bit 7:5 Unimplemented: Read as 0

bit 4 EEIF: EEPROM Write Operation Interrupt Flag bit

1 = The write operation completed (must be cleared in software)

0 = The write operation is not complete or has not been started

bit 3 WRERR: EEPROM Error Flag bit1 = A write operation is prematurely terminated

(any MCLR reset or any WDT reset during normal operation)

0 = The write operation completed

bit 2 WREN: EEPROM Write Enable bit

1 = Allows write cycles

0 = Inhibits write to the data EEPROM

bit 1 WR: Write Control bit

1 = initiates a write cycle. (The bit is cleared by hardware once write is complete. The WR bit can only

be set (not cleared) in software.

0 = Write cycle to the data EEPROM is complete

bit 0 RD: Read Control bit

1 = Initiates an EEPROM read (read takes one cycle. RD is cleared in hardware. The RD bit can only

be set (not cleared) in software).0 = Does not initiate an EEPROM read


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7.2 EECON1 and EECON2 Registers

EECON1 is the control register with five low order bits

physically implemented. The upper-three bits are non-

existent and read as 0s.

Control bits RD and WR initiate read and write,

respectively. These bits cannot be cleared, only set, in

software. They are cleared in hardware at completion

of the read or write operation. The inability to clear theWR bit in software prevents the accidental, premature

termination of a write operation.

The WREN bit, when set, will allow a write operation.

On power-up, the WREN bit is clear. The WRERR bit is

set when a write operation is interrupted by a MCLR

reset or a WDT time-out reset during normal operation.

In these situations, following reset, the user can check

the WRERR bit and rewrite the location. The data and

address will be unchanged in the EEDATA and

EEADR registers.

Interrupt flag bit EEIF is set when write is complete. It

must be cleared in software.

EECON2 is not a physical register. Reading EECON2

will read all 0s. The EECON2 register is used

exclusively in the Data EEPROM write sequence.

7.3 Reading the EEPROM Data Memory

To read a data memory location, the user must write the

address to the EEADR register and then set control bit

RD (EECON1). The data is available, in the very

next cycle, in the EEDATA register; therefore it can be

read in the next instruction. EEDATA will hold this value

until another read or until it is written to by the user

(during a write operation).

EXAMPLE 7-1: DATA EEPROM READ

BCF STATUS, RP0 ; Bank 0

MOVLW CONFIG_ADDR ;

MOVWF EEADR ; Address to read

BSF STATUS, RP0 ; Bank 1

BSF EECON1, RD ; EE Read


MOVF EEDATA, W ; W = EEDATA

7.4 Writing to the EEPROM Data Memory

To write an EEPROM data location, the user must first

write the address to the EEADR register and the data

to the EEDATA register. Then the user must follow a

specific sequence to initiate the write for each byte.

EXAMPLE 7-1: DATA EEPROM WRITE


BCF INTCON, GIE ; Disable INTs.

BSF EECON1, WREN ; Enable Write

MOVLW 55h ;

MOVWF EECON2 ; Write 55h

MOVLW AAh ;

MOVWF EECON2 ; Write AAh

BSF EECON1,WR ; Set WR bit

; begin write

BSF INTCON, GIE ; Enable INTs.

The write will not initiate if the above sequence is not

exactly followed (write 55h to EECON2, write AAh to

EECON2, then set WR bit) for each byte. We strongly

recommend that interrupts be disabled during this

code segment.

Additionally, the WREN bit in EECON1 must be set to

enable write. This mechanism prevents accidental

writes to data EEPROM due to errant (unexpected)

code execution (i.e., lost programs). The user should

keep the WREN bit clear at all times, except when

updating EEPROM. The WREN bit is not cleared

by hardware

After a write sequence has been initiated, clearing the

WREN bit will not affect this write cycle. The WR bit will

be inhibited from being set unless the WREN bit is set.

At the completion of the write cycle, the WR bit is

cleared in hardware and the EE Write Complete

Interrupt Flag bit (EEIF) is set. The user can either

enable this interrupt or poll this bit. EEIF must be

cleared by software.

Required

Sequence


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PIC16F8X


7.5 Write Verify

Depending on the application, good programming prac-

tice may dictate that the value written to the Data

EEPROM should be verified (Example 7-1) to the

desired value to be written. This should be used in

applications where an EEPROM bit will be stressed

near the specification limit. The Total Endurance disk

will help determine your comfort level.Generally the EEPROM write failure will be a bit which

was written as a 1, but reads back as a 0 (due to

leakage off the bit).

EXAMPLE 7-1: WRITE VERIFY


: ; Any code can go here

: ;

MOVF EEDATA, W ; Must be in Bank 0


READ

BSF EECON1, RD ; YES, Read the

; value written


;

; Is the value written (in W reg) and

; read (in EEDATA) the same?

;

SUBWF EEDATA, W ;

BTFSS STATUS, Z ; Is difference 0?

GOTO WRITE_ERR ; NO, Write error

: ; YES, Good write

: ; Continue program

7.6 Protection Against Spurious Writes

There are conditions when the device may not want to

write to the data EEPROM memory. To protect againstspurious EEPROM writes, various mechanisms have

been built in. On power-up, WREN is cleared. Also, the

Power-up Timer (72 ms duration) prevents

EEPROM write.

The write initiate sequence and the WREN bit together

help prevent an accidental write during brown-out,

power glitch, or software malfunction.

7.7 Data EEPROM Operation during CodeProtect

When the device is code protected, the CPU is able to

read and write unscrambled data to the Data EEPROM.

For ROM devices, there are two code protection bits

(Section 8.1). One for the ROM program memory and

one for the Data EEPROM memory.

TABLE 7-1 REGISTERS/BITS ASSOCIATED WITH DATA EEPROM


Reset


08h EEDATA EEPROM data register xxxx xxxx uuuu uuuu

09h EEADR EEPROM address register xxxx xxxx uuuu uuuu

88h EECON1 EEIF WRERR WREN WR RD ---0 x000 ---0 q000

89h EECON2 EEPROM control register 2 ---- ---- ---- ----

Legend: x = unknown, u = unchanged, - = unimplemented read as 0, q = value depends upon condition. Shaded cells are not

used by Data EEPROM.
http://../16c84/30445x/C84_spf.pdfhttp://../16c84/30445x/C84_spf.pdf


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NOTES:


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PIC16F8X


8.0 SPECIAL FEATURES OF THECPU

What sets a microcontroller apart from other

processors are special circuits to deal with the needs of

real time applications. The PIC16F8X has a host of

such features intended to maximize system reliability,

minimize cost through elimination of external

components, provide power saving operating modesand offer code protection. These features are:

OSC Selection

Reset

- Power-on Reset (POR)

- Power-up Timer (PWRT)

- Oscillator Start-up Timer (OST)

Interrupts

Watchdog Timer (WDT)

SLEEP

Code protection

ID locations

In-circuit serial programming

The PIC16F8X has a Watchdog Timer which can be

shut off only through configuration bits. It runs off its

own RC oscillator for added reliability. There are two

timers that offer necessary delays on power-up. One is

the Oscillator Start-up Timer (OST), intended to keep

the chip in reset until the crystal oscillator is stable. The

other is the Power-up Timer (PWRT), which provides a

fixed delay of 72 ms (nominal) on power-up only. This

design keeps the device in reset while the power supply

stabilizes. With these two timers on-chip, most

applications need no external reset circuitry.

SLEEP mode offers a very low current power-down

mode. The user can wake-up from SLEEP throughexternal reset, Watchdog Timer time-out or through an

interrupt. Several oscillator options are provided to

allow the part to fit the application. The RC oscillator

option saves system cost while the LP crystal option

saves power. A set of configuration bits are used to

select the various options.


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PIC16F8X


8.1 Configuration Bits

The configuration bits can be programmed (read as 0)

or left unprogrammed (read as 1) to select various

device configurations. These bits are mapped in

program memory location 2007h.

Address 2007h is beyond the user program memory

space and it belongs to the special test/configuration

memory space (2000h - 3FFFh). This space can only

be accessed during programming.

To find out how to program the PIC16C84, refer to

PIC16C84 EEPROM Memory Programming Specifica-

tion(DS30189).

FIGURE 8-1: CONFIGURATION WORD - PIC16CR83 AND PIC16CR84

R-u R-u R-u R-u R-u R-u R/P-u R-u R-u R-u R-u R-u R-u R-u

CP CP CP CP CP CP DP CP CP CP PWRTE WDTE FOSC1 FOSC0

bit13 bit0

R = Readable bit

P = Programmable bit


u = unchanged

bit 13:8 CP: Program Memory Code Protection bit

1 = Code protection off

0 = Program memory is code protected

bit 7 DP: Data Memory Code Protection bit1 = Code protection off

0 = Data memory is code protected

bit 6:4 CP: Program Memory Code Protection bit

1 = Code protection off

0 = Program memory is code protected

bit 3 PWRTE: Power-up Timer Enable bit

1 = Power-up timer is disabled

0 = Power-up timer is enabled

bit 2 WDTE: Watchdog Timer Enable bit

1 = WDT enabled

0 = WDT disabled

bit 1:0 FOSC1:FOSC0: Oscillator Selection bits11 = RC oscillator

10 = HS oscillator

01 = XT oscillator

00 = LP oscillator


39/124


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PIC16F8X


FIGURE 8-4: EXTERNAL CLOCK INPUT

OPERATION (HS, XT OR LPOSC CONFIGURATION)

TABLE 8-1 CAPACITOR SELECTION FORCERAMIC RESONATORS

TABLE 8-2 CAPACITOR SELECTION FOR

CRYSTAL OSCILLATOR

8.2.3 EXTERNAL CRYSTAL OSCILLATOR

CIRCUIT

Either a prepackaged oscillator can be used or a simple

oscillator circuit with TTL gates can be built.

Prepackaged oscillators provide a wide operating

range and better stability. A well-designed crystal

oscillator will provide good performance with TTL

gates. Two types of crystal oscillator circuits are

available; one with series resonance, and one with

parallel resonance.

Figure 8-5 shows a parallel resonant oscillator circuit.The circuit is designed to use the fundamental

frequency of the crystal. The 74AS04 inverter performs

the 180-degree phase shift that a parallel oscillator

requires. The 4.7 k resistor provides negativefeedback for stability. The 10 k potentiometer biasesthe 74AS04 in the linear region. This could be used for

external oscillator designs.

FIGURE 8-5: EXTERNAL PARALLEL

RESONANT CRYSTALOSCILLATOR CIRCUIT

Figure 8-6 shows a series resonant oscillator circuit.This circuit is also designed to use the fundamental

frequency of the crystal. The inverter performs a

180-degree phase shift. The 330 k resistors providethe negative feedback to bias the inverters in their

linear region.

Ranges Tested:

Mode Freq OSC1/C1 OSC2/C2

XT 455 kHz

2.0 MHz

4.0 MHz

47 - 100 pF

15 - 33 pF

15 - 33 pF

47 - 100 pF

15 - 33 pF

15 - 33 pF

HS 8.0 MHz

10.0 MHz

15 - 33 pF

15 - 33 pF

15 - 33 pF

15 - 33 pF

Note: Recommended values of C1 and C2 are identical tothe ranges tested table.

Higher capacitance increases the stability of the

oscillator but also increases the start-up time.

These values are for design guidance only. Since

each resonator has its own characteristics, the user

should consult the resonator manufacturer for the

appropriate values of external components.

Resonators Tested:

455 kHz Panasonic EFO-A455K04B 0.3%

2.0 MHz Murata Erie CSA2.00MG 0.5%

4.0 MHz Murata Erie CSA4.00MG 0.5%

8.0 MHz Murata Erie CSA8.00MT 0.5%

10.0 MHz Murata Erie CSA10.00MTZ 0.5%None of the resonators had built-in capacitors.

Mode Freq OSC1/C1 OSC2/C2

LP 32 kHz

200 kHz

68 - 100 pF

15 - 33 pF

68 - 100 pF

15 - 33 pF

XT 100 kHz

2 MHz

4 MHz

100 - 150 pF

15 - 33 pF

15 - 33 pF

100 - 150 pF

15 - 33 pF

15 - 33 pF

HS 4 MHz

10 MHz

15 - 33 pF

15 - 33 pF

15 - 33 pF

15 - 33 pFNote : Higher capacitance increases the stability of

oscillator but also increases the start-up time.

These values are for design guidance only. Rs may

be required in HS mode as well as XT mode to

avoid overdriving crystals with low drive level speci-

fication. Since each crystal has its own characteris-

tics, the user should consult the crystal

manufacturer for appropriate values of external

components.

For VDD > 4.5V, C1 = C2 30 pF is recommended.

OSC1

OSC2Open

Clock fromext. system PIC16FXX

Crystals Tested:

32.768 kHz Epson C-001R32.768K-A 20 PPM

100 kHz Epson C-2 100.00 KC-P 20 PPM

200 kHz STD XTL 200.000 KHz 20 PPM

1.0 MHz ECS ECS-10-13-2 50 PPM

2.0 MHz ECS ECS-20-S-2 50 PPM

4.0 MHz ECS ECS-40-S-4 50 PPM10.0 MHz ECS ECS-100-S-4 50 PPM

20 pF

+5V

20 pF

10k

4.7k

10k

74AS04

XTAL

10k

74AS04

PIC16FXX

CLKIN

To OtherDevices


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PIC16F8X


FIGURE 8-6: EXTERNAL SERIESRESONANT CRYSTAL

OSCILLATOR CIRCUIT

8.2.4 RC OSCILLATOR

For timing insensitive applications the RC device option

offers additional cost savings. The RC oscillator

frequency is a function of the supply voltage, the

resistor (Rext) values, capacitor (Cext) values, and the

operating temperature. In addition to this, the oscillator

frequency will vary from unit to unit due to normalprocess parameter variation. Furthermore, the

difference in lead frame capacitance between package

types also affects the oscillation frequency, especially

for low Cext values. The user needs to take into

account variation due to tolerance of the external

R and C components. Figure 8-7 shows how an R/C

combination is connected to the PIC16F8X. For Rext

values below 4 k, the oscillator operation maybecome unstable, or stop completely. For very high

Rext values (e.g., 1 M), the oscillator becomessensitive to noise, humidity and leakage. Thus, we

recommend keeping Rext between 5 k and 100 k.

Although the oscillator will operate with no external

capacitor (Cext = 0 pF), we recommend using values

above 20 pF for noise and stability reasons. With little

or no external capacitance, the oscillation frequency

can vary dramatically due to changes in external

capacitances, such as PCB trace capacitance or

package lead frame capacitance.

See the electrical specification section for RC

frequency variation from part to part due to normal

process variation. The variation is larger for larger R

(since leakage current variation will affect RC

frequency more for large R) and for smaller C (since

variation of input capacitance has a greater affect on

RC frequency).

See the electrical specification section for variation ofoscillator frequency due to VDD for given Rext/Cext

values as well as frequency variation due to

operating temperature.

The oscillator frequency, divided by 4, is available on

the OSC2/CLKOUT pin, and can be used for test

purposes or to synchronize other logic (see Figure 3-2

for waveform).

FIGURE 8-7: RC OSCILLATOR MODE

8.3 Reset

The PIC16F8X differentiates between various kinds

of reset:

Power-on Reset (POR) MCLR reset during normal operation

MCLR reset during SLEEP

WDT Reset (during normal operation)

WDT Wake-up (during SLEEP)

Figure 8-8 shows a simplified block diagram of the

on-chip reset circuit. The MCLR reset path has a noise

filter to ignore small pulses. The electrical specifica-

tions state the pulse width requirements for the MCLR

pin.

Some registers are not affected in any reset condition;

their status is unknown on a POR reset and unchanged

in any other reset. Most other registers are reset to a

reset state on POR, MCLR or WDT reset during

normal operation and on MCLR reset during SLEEP.

They are not affected by a WDT reset during SLEEP,

since this reset is viewed as the resumption of normal

operation.

Table 8-3 gives a description of reset conditions for the

program counter (PC) and the STATUS register.

Table 8-4 gives a full description of reset states for all

registers.

The TO and PD bits are set or cleared differently in dif-

ferent reset situations (Section 8.7). These bits are

used in software to determine the nature of the reset.

330 k

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PIC16F8X - 18-pin Flash/EEPROM 8-Bit Microcontrollers - 30430c

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