PIPELINED ANALOG-TO-DIGITAL CONVERSION USING CLASS-AB ...tn724tb5229/... · PIPELINED...

PIPELINED ANALOG-TO-DIGITAL CONVERSION

USING CLASS-AB AMPLIFIERS

A DISSERTATION

SUBMITTED TO THE DEPARTMENT OF ELECTRICAL ENGINEERING

AND THE COMMITTEE ON GRADUATE STUDIES

OF STANFORD UNIVERSITY

IN PARTIAL FULFILLMENT OF THE REQUIREMENTS

FOR THE DEGREE OF

DOCTOR OF PHILOSOPHY

Kyung Ryun Kim

December 2010

http://creativecommons.org/licenses/by-nc/3.0/us/

This dissertation is online at: http://purl.stanford.edu/tn724tb5229

© 2011 by Kyung Ryun Kim. All Rights Reserved.

Re-distributed by Stanford University under license with the author.

This work is licensed under a Creative Commons Attribution-Noncommercial 3.0 United States License.

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http://purl.stanford.edu/tn724tb5229

I certify that I have read this dissertation and that, in my opinion, it is fully adequatein scope and quality as a dissertation for the degree of Doctor of Philosophy.

Boris Murmann, Primary Adviser


S Wong


Bruce Wooley

Approved for the Stanford University Committee on Graduate Studies.

Patricia J. Gumport, Vice Provost Graduate Education

This signature page was generated electronically upon submission of this dissertation in electronic format. An original signed hard copy of the signature page is on file inUniversity Archives.

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Abstract

In high-performance pipelined analog-to-digital converters (ADCs), the residue

amplifiers dissipate the majority of the overall converter power. Therefore, finding

alternatives to the relatively inefficient, conventional class-A circuit realization is an

active area of research. One option for improvement is to employ class-AB amplifiers,

which can, in principle, provide large drive currents on demand and improve the

efficiency of residue amplification. Unfortunately, due to the simultaneous demand for

high speed and high gain in pipelined ADCs, the improvements seen in class-AB

designs have so far been limited.

This dissertation presents the design of an efficient class-AB amplification

scheme based on a pseudo-differential, single-stage and cascode-free architecture. The

proposed amplifier exhibits fast turn-on and turn-off times, making it possible to apply

dynamic power cycling to further reduce power. Nonlinear errors due to finite DC

gain are addressed using a deterministic background calibration scheme that measures

the circuit imperfections in time intervals between normal conversion cycles of the

ADC. This proposed scheme also features a spline-based correction that handles the

measured errors based on piecewise polynomial functions.

As a proof of concept, a 12-bit 30-MS/s pipelined ADC was realized using class-

AB amplifiers with the proposed digital calibration. The prototype ADC occupies an

active area of 0.36 mm2 in 90-nm CMOS. It dissipates 2.95 mW from a 1.2-V supply

and achieves an SNDR of 64.5 dB for inputs near the Nyquist frequency. The

corresponding figure of merit is 72 fJ/conversion-step.

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Acknowledgments

It has been a great honor and a privilege to be a graduate student at Stanford

University. My experience at Stanford has been both tremendously educational and

enjoyable. During the six years of my stay, I have learned so many things from

professors and colleagues. From them, I not only have learned technical skills in the

area of engineering but also wisdoms for life. I wish to acknowledge many people for

giving me valuable lessons and joy during my life at Stanford.

First of all, I would like to thank Professor Boris Murmann for supervising my

doctoral research. Throughout my graduate program, he has been a great mentor and

supporter who gave me valuable advices without which none of my doctoral work

would have been possible. I learned how to design circuits and to conduct a quality

research from him. Whenever I encountered a problem along the way to the Ph.D., his

keen insights guided me to the right direction, and his engineering expertise provided

me with a new idea. Sincerely, working with him was the best part of my life at

Stanford.

I would like to extend my appreciation to my associate advisor, Professor Bruce A.

Wooley, and Professor S. Simon Wong for being my reading and oral examination

committee members. With great expertise, they gave me lots of technical feedbacks

and helped me consolidate my work. I also thank Professor Roger T. Howe for

chairing my oral examination committee and sharing his wisdoms of life. It is an

honor for me to have them all in my committee.

I would also like to give my sincere gratitude to Ms. Ann Guerra, who is our

group’s administrative assistant. I’m one of the many people who were touched by her

kindness. She helped me in many ways including, but not limited to, creating

important administrative forms or getting a reimbursement. She made such tasks

incomparably easier.

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For sponsorship, I thank Samsung Scholarship and the Stanford Initiative for

Rethinking Analog Design (RAD). I also thank United Microelectronics Corporation

(UMC) for the fabrication of the prototype chip.

I also thank Professor Murmann’s research group members, both past and present.

In particular, I thank Dr. Jung-Hoon Chun, Paul Wang Lee, Dr. Echere Iroaga, Dr.

Yangjin Oh, Dr. Jason Hu, Dr. Parastoo Nikaeen, Pedram Lajevardi, Dr. Clay Daigle,

Dr. Manar El-Chammas, Alireza Dastgheib, Donghyun Kim, Wei Xiong, Noam Dolev,

Drew Hall, Ray Nguyen, Ross Walker, Alex Guo, Yoonyoung Chung, Vaibhav

Tripathi, Martin Johannes Krämer, Bill Chen, Ryan Boesch, Man-Chia Chen,

Jonathon Spaulding and Alex Omid-Zohoor for technical discussions we shared and

all the feedbacks I received at the group meetings. I would also like to thank other

former and current colleagues in Allen building and Gates building for their technical

advices. This includes Dr. Haechang Lee, Dr. Jaeha Kim, Dr. Moonjung Kim, Dr.

Sangmin Lee, Dr. Hyunsik Park, Dr. Jim Salvia, Mohammad Hekmat, Roxana Trofin

Heitz, Henrique Miranda, Maryam Fathi, Dr. Sungbeom Park and Byongchan Lim.

I also thank friends who were always within close reach and made my life at

Stanford more enjoyable and memorable. In particular, I thank everyone from Korea

Advanced Institute of Science and Technology (KAIST) alumni community,

especially Seunghwa Ryu, Dr. Saeroonter Oh, Byungil Lee, Dr. Donghyun Kim and

Dr. Hyunwoo Nho. I also thank everyone from Cornerstone Community Church,

especially Jungjune Lee, Jeesoo Lee, Kyungmin Lim, Minyong Shin, Kibum Lee,

Wonhee Go, Jooeun Lee, Pastor Taegyun Sihn and Pastor Hun Sol. Last, I want to

thank Jaeyoung Lee for her kindness and affection.

Finally, I want to express my sincerest appreciation to my family. My father, Dr.

Kwon Jeep Kim, always encouraged and supported me throughout my life. He has

always enjoyed teaching me words of wisdom from history and the stories about great

thinkers and leaders, which gave me so many inspirations in my life. He also has been

a great role model for me. In particular, I grew up frequently watching my father read

and write books. This experience partly drove me to pursue this path. My mother, Sun

Ho Park, always showed me unconditional love and truly believed in me for my

ix

success. Her love and support brought out the best in me. Last, I’m also very grateful

to my sister, Ji Hye Kim. She has been very kind and loving to me and always has

been a great example for me to follow. My family has always given me love and

support without asking anything for return. This journey would not have been

successful, if it weren’t for their love and support. Therefore, I dedicate this

dissertation to my family.

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Table of Contents

Abstract ......................................................................................................................... v Acknowledgments ....................................................................................................... vii List of Tables ............................................................................................................... xv List of Figures ........................................................................................................... xvii Chapter 1 ....................................................................................................................... 1

1.1 Motivation .................................................................................................. 1 1.2 Background ................................................................................................. 2

1.2.1 Pipelined ADCs ................................................................................... 2 1.2.2 Multiplying Digital-to-Analog Converter (MDAC) Circuit ................ 4

1.3 Organization ............................................................................................... 5 Chapter 2 ....................................................................................................................... 7

2.1 Conceptual Overview ................................................................................. 8 2.2 Detailed Circuit Description ..................................................................... 11

2.2.1 MDAC with a Single-Stage Class-AB Amplifier .............................. 11 2.2.2 Differential Input Sampling ............................................................... 15 2.2.3 Output CM Stability ........................................................................... 19 2.2.4 Noise .................................................................................................. 20 2.2.5 Dynamic Power Cycling .................................................................... 21

2.2.5.1 Implementation of the Turn-on Switches……………………...21 2.2.5.2 Fast Turn-on Transient of the Amplifier Architecture…………23

2.2.6 Maximum Swing and Nonlinearity .................................................... 23

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2.3 Summary ................................................................................................... 24 Chapter 3 ..................................................................................................................... 25

3.1 Overview .................................................................................................. 27 3.2 Spline-Based Nonlinearity Modeling ....................................................... 28 3.3 Deterministic Background Calibration ..................................................... 35

3.3.1 Overview ............................................................................................ 35 3.3.2 Providing a Test Signal ...................................................................... 35 3.3.3 Deterministic Background Calibration .............................................. 36

3.4 Implementation ......................................................................................... 37 3.4.1 ADC Architecture .............................................................................. 37 3.4.2 Stage Calibration Sequence ............................................................... 38 3.4.3 Clocking Scheme ............................................................................... 39 3.4.4 Test Input DAC Implementation ....................................................... 40 3.4.5 Dynamic Element Matching of Unit Capacitors ................................ 41 3.4.6 Implementation of Post-Processing Block ......................................... 46 3.4.7 Calibration of Backend Stages ........................................................... 47 3.4.8 Convergence of the calibration .......................................................... 47

3.5 Summary ................................................................................................... 48 Chapter 4 ..................................................................................................................... 49

4.1 ADC Architecture ..................................................................................... 49 4.2 MDAC ...................................................................................................... 51 4.3 SHA-less Frontend ................................................................................... 54 4.4 Comparator ............................................................................................... 56 4.5 Reference Generation ............................................................................... 58

xiii

4.6 Supply Regulator ...................................................................................... 61 4.7 Output Multiplexing and LVDS Signaling ............................................... 61 4.8 Summary ................................................................................................... 62

Chapter 5 ..................................................................................................................... 63 5.1 Prototype Die ............................................................................................ 64 5.2 Test Setup ................................................................................................. 65 5.3 Measured Results ...................................................................................... 67

5.3.1 Dynamic Linearity ............................................................................. 67 5.3.2 Static Linearity ................................................................................... 71 5.3.3 Power ................................................................................................. 74 5.3.4 Calibration Settling ............................................................................ 75 5.3.5 Input Common-Mode Variation ........................................................ 77 5.3.6 Temperature Variation ....................................................................... 78 5.3.7 Supply Variation ................................................................................ 79 5.3.8 Performance Comparison .................................................................. 80

5.4 ADC Performance at fs = 50 MHz ........................................................... 82 5.4.1 Linearity Degradation ........................................................................ 82 5.4.2 Analysis ............................................................................................. 84 5.4.3 Source of the Error ............................................................................. 86 5.4.4 Solution to the Problem ..................................................................... 89

5.5 Summary ................................................................................................... 90 Chapter 6 ..................................................................................................................... 93

6.1 Summary ................................................................................................... 93 6.2 Future Work .............................................................................................. 94

xiv

Appendix A …………………………………………………………………………97

A.1 Time Alignment ……………………………………………………......97

A.2 Post-Processing…………………………………………………………97

A.3 Power Estimation ………………………………………………………99

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List of Tables

Table 4.1: Specifications and design parameters for the ADC. ................................... 51 Table 4.2: Device sizes and design parameters in the circuit of Figure 4.2. ................ 52 Table 5.1: Test equipment. ........................................................................................... 66 Table 5.2: Specifications of state-of-the-art 12-bit pipelined ADC designs. ............... 81 Table 5.3: Performance summary. ................................................................................ 91 Table A.1: Average energy required when the output switches (VDD of 1.2V). ........ 100 Table A.2: Estimated digital post-processing power breakdown. .............................. 100

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List of Figures

Figure 1.1: Pipelined ADC. (a) Converter block diagram. (b) Stage block diagram. (c)

Two non-overlapping clocks. ..................................................................... 3 Figure 1.2: Operation of an MDAC circuit. ................................................................... 4 Figure 2.1: Block diagram of a typical two-stage class-AB amplifier. .......................... 7 Figure 2.2: Basic operation of a single-stage class-AB amplifier. ................................. 8 Figure 2.3: Input and output transient voltages of a switched-capacitor class-A/class-

AB amplifier. ............................................................................................ 10 Figure 2.4: Supply and load current waveforms. (a) Waveform of a class-A amplifier.

(b) Waveform of a class-AB amplifier that features dynamic power

cycling. ..................................................................................................... 10 Figure 2.5: MDAC implementation. ............................................................................ 11 Figure 2.6: Cgd neutralization for transistor N0 (subscripts P and N indicate the positive

and negative half circuits, respectively). The gate widths of NNP and NNN

are designed to half the widths of N0P and N0N. ....................................... 12 Figure 2.7: Reset phase schematic. ............................................................................... 13 Figure 2.8: Sample phase schematic. ........................................................................... 13 Figure 2.9: Compare phase schematic. ......................................................................... 14 Figure 2.10: Amplify phase schematic. ........................................................................ 14 Figure 2.11: The full circuit of the differential input network in the sample phase. .... 16 Figure 2.12: Half circuits for the input network in the sample phase. (a) The CM half

circuit. (b) The DM half circuit. ............................................................... 16 Figure 2.13: The CM half circuits for the input network in the compare phase. ......... 17

xviii

Figure 2.14: Simplified schematic of the MDAC circuit in the amplify phase. ........... 20 Figure 2.15: Implementation of low-overhead turn-on switches. (a) Basic amplifier

schematic. (b) Amplifier schematic after splitting the Φ4 switch. (c)

Amplifier schematic after disconnecting the drains of P0 and N0. (d) Final

amplifier schematic, indicating the current path. ..................................... 22 Figure 2.16: Simplified schematic of the amplifier (a) before and (b) after turning on.

.................................................................................................................. 23 Figure 2.17: Amplifier output swing analysis. The plot shows the conceptual closed-

loop transfer function of the proposed amplifier. ..................................... 24 Figure 3.1: Block diagram of an ADC with digital nonlinearity calibration. ............... 27 Figure 3.2: Four-section spline-based model. .............................................................. 29 Figure 3.3: Modeling of second order nonlinearity using third order spline functions.

.................................................................................................................. 31 Figure 3.4: The effect of the four-section spline-based calibration on THD. .............. 32 Figure 3.5: Three-section spline-based calibration. ..................................................... 33 Figure 3.6: Residue plot after spline-based nonlinearity correction. ............................ 34 Figure 3.7: Implementation of Σ block in Figure 3.1. .................................................. 34 Figure 3.8: Stage’s mode of operation. ........................................................................ 36 Figure 3.9: Conceptual stage output with the deterministic background calibration. .. 37 Figure 3.10: ADC block diagram featuring the proposed calibration. ......................... 38 Figure 3.11: Stage calibration sequence. (a) Direction of calibration. (b) Timing

diagram of Stage_sel signal. ..................................................................... 39 Figure 3.12: Timing diagram of clocks, control signals and stage modes. .................. 40 Figure 3.13: Sub-DAC with capacitor splitting. (a) Circuit schematic. (b) Sub-DAC

output after the capacitor splitting. ........................................................... 41

xix

Figure 3.14: Permutation method of the eight unit capacitors. .................................... 43 Figure 3.15: Calibration path diagram. ......................................................................... 43 Figure 3.16: Post-processing block diagram. ............................................................... 46 Figure 3.17: Sub-DAC with capacitor splitting. (a) Circuit schematic. (b) Sub-DAC

output after the capacitor splitting. ........................................................... 47 Figure 4.1: Block diagram of the 12-bit prototype pipelined ADC. ............................ 50 Figure 4.2: MDAC implementation in the first stage. .................................................. 52 Figure 4.3: Simulated first stage gain. .......................................................................... 53 Figure 4.4: Simulated waveform of the supply and load currents. ............................... 54 Figure 4.5: Maximum tolerable sub-ADC error. .......................................................... 55 Figure 4.6: Schematic of our dynamic latch comparator. ............................................ 56 Figure 4.7: Sub-ADC schematic (only one out of two comparator channels is shown).

.................................................................................................................. 58 Figure 4.8: Reference voltage generation. (a) An internal buffer with an internal

bypass capacitor. (b) An internal buffer with an external bypass capacitor.

(c) An external buffer with an external bypass capacitor (and optional

internal bypass capacitor). ........................................................................ 60 Figure 4.9: Output processing. ..................................................................................... 61 Figure 5.1: Die photograph and layout. ........................................................................ 63 Figure 5.2: Layout of the pipeline stages. .................................................................... 64 Figure 5.3: Down-bonding. .......................................................................................... 64 Figure 5.4: Test setup. .................................................................................................. 65 Figure 5.5: Measured output spectrum (16384 point FFT) of the experimental ADC

with and without calibration (fs = 30 MHz and fin = 1 MHz). .................. 68

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Figure 5.6: Measured output spectrum (16384 point FFT) of the experimental ADC

with and without calibration (fs = 30 MHz and fin = 14.8 MHz). ............. 69 Figure 5.7: Measured peak SNDR versus input frequency (fs = 30 MHz). .................. 70 Figure 5.8: Measured SNDR versus input amplitude (fs = 30 MHz and fin = 14.8 MHz).

.................................................................................................................. 70 Figure 5.9: Measured DNL/INL without calibration. .................................................. 72 Figure 5.10: Measured DNL/INL with calibration. ...................................................... 73 Figure 5.11: Measured INL with calibration (magnified). ........................................... 73 Figure 5.12: Measured power consumption versus the sampling frequency (fin = 1

MHz). ........................................................................................................ 75 Figure 5.13: Calibration algorithm settling result (fs = 30 MHz and fin = 14.8 MHz). . 76 Figure 5.14: Measured peak SNDR versus input CM variation (fs = 30 MHz and fin = 1

MHz). ........................................................................................................ 77 Figure 5.15: Measured peak SNDR versus temperature variation (fs = 30 MHz and fin =

1 MHz). ..................................................................................................... 78 Figure 5.16: Measured peak SNDR versus supply variation (fs = 30 MHz and fin = 1

MHz). ........................................................................................................ 80 Figure 5.17: Energy per conversion versus SNDR for ADCs published at ISSCC and

VLSI from 1997 to 2010. ......................................................................... 81 Figure 5.18: Measured output spectrum (16384 point FFT) of the experimental ADC

without calibration (fs = 50 MHz and fin = 1 MHz). ................................. 82 Figure 5.19: Output spectrum (16384 point FFT) after removing the seven “strange”

tones shown in Figure 5.18 (fs = 50 MHz and fin = 1 MHz). .................... 83 Figure 5.20: Time-domain representation of (a) the error tones and (b) the input signal

(measured using the ADC). ...................................................................... 85 Figure 5.21: Timing diagram for the first stage. .......................................................... 86

xxi

Figure 5.22: Sampling instance and behavior of kickback noise. ................................ 87 Figure 5.23: Conceptual errors due to unsettled kickback noise for a sinusoidal input.

.................................................................................................................. 87 Figure 5.24: ADC input driving network. .................................................................... 88 Figure 5.25: Simulated spectrum of the sampled input (fs = 50 MHz and fin = 1 MHz).

.................................................................................................................. 89 Figure 5.26: Timing diagram for the first stage after the modification. ....................... 89 Figure 5.27: Simulated spectrum of the sampled input after the modification (fs = 50

MHz and fin = 1 MHz). Kickback noise component is removed. ............ 90 Figure A.1: Time alignment block diagram. ................................................................ 98 Figure A.2: Simplified correction block diagram of the first stage. ............................. 98 Figure A.3: Multiplication of two 7-bit numbers. ........................................................ 99

xxii

1

Chapter 1

Introduction

1.1 Motivation

The pipelined ADC is one of the most popular ADC architectures since it has

proven power-efficient for high speed (10-500 MS/s) and moderate resolution (8-14

bits). These performance specifications are commonly encountered in applications

such as communication and imaging systems. With evolutionary progress over the

past decades, pipelined ADCs have come very close to practical power limits imposed

by their conventional underlying circuit topologies [1]. However, due to the ever

growing demand for low-power, which is mostly driven by the proliferation of battery-

powered hand-held devices, today’s levels of pipelined ADC power consumption are

still unsatisfactory.

Recently, many researchers have achieved dramatic improvements in converter

power by changing the traditional underlying circuit topologies (especially residue

amplification principles in pipelined ADCs). One way of improvement is achieved by

incorporating digital calibration to relax analog circuit requirements such as high gain

[2] and precision settling [3]. Another way of improvement was achieved by replacing

the linear gain stages with comparator-based stages [4], zero-crossing-based stages [5]

or dynamic source followers [6].

This research explores a new direction towards further power improvements by

utilizing class-AB amplification. This work presents an efficient single-stage cascode-

free class-AB amplifier that leverages digital calibration. Such a combination

2 Chapter 1: Introduction

improves the efficacy of the class-AB amplification since it can relax the high-gain

requirements traditionally imposed in pipeline stages. In addition, no complex biasing

and explicit common-mode feedback circuitry are used in the design. This simplified

amplifier exhibits fast turn-on and turn-off times, making it possible to dynamically

switch off the amplifier to further reduce power in clock phases where it is not utilized

for amplification. The proposed amplifier architecture, in combination with the

dynamic power cycling, saves a significant amount of “wasted” supply charge seen in

a conventional switched-capacitor class-A amplifier. Here, “wasted” charge refers to

the fraction of power supply charge within a clock cycle that isn’t delivered to the load.

1.2 Background

This section presents a brief review of pipelined ADCs. Section 1.2.1 first

describes the overall architecture and operation of pipelined ADCs, and Section 1.2.2

discusses the multiplying digital-to-analog converter (MDAC), which is one of the

most important building blocks in pipelined ADCs. The pipelined ADC design

presented in this dissertation is based on the basic architecture described in this review.

More detailed review material on pipelined ADCs can be found in [7]-[11].

1.2.1 Pipelined ADCs

A pipelined ADC is comprised of several stages successively connected as in

Figure 1.1(a) [7]. Each stage generates a low-resolution estimate of its input, and all of

the estimates are aligned and combined using digital logic to obtain a high resolution

conversion result.

Each stage contains four sub-blocks: a sub-ADC, a sub-DAC, an adder and an

amplifier, as shown in Figure 1.1(b). The operation of each stage generally has two

phases, a sample phase and an amplify phase. In the sample phase, a stage samples the

input and coarsely quantizes it using the sub-ADC to generate the corresponding

digital output. In the amplify phase, the stage first calculates the quantization error

using the sub-DAC and the adder blocks, and then it multiplies the error using the

Chapter 1: Introduction 3

internal amplifier such that the maximum output swing of the stage occupies the full

input range of the next stage. Therefore, the amplifier gain, G, is typically designed as

2B, where B is the effective number of bits resolved in the stage. Because of the stage

operation, which calculates the difference between the input and the quantized digital

output, the internal amplifier and the stage output are referred to as the residue

amplifier and the residue, respectively.

…

D1 D2 D3 Dn

Stage 1

(B1 Bits)

Digital Logic: Align and Combine Data

Stage 2

(B2 Bits)

Stage 3

(B3 Bits)

Stage n

(Bn Bits)

1 cycle

DO (B1 + B2 + … + Bn) Bits

VI

Φ1 High

Φ2 High

Sample

Amplify Sample

Amplify Sample

Amplify

Φ1

Φ2

VI VO

D

A/D D/A

++

-

G

(a)

(b) (c)

Figure 1.1: Pipelined ADC. (a) Converter block diagram. (b) Stage block diagram. (c)

Two non-overlapping clocks.

All the stages concurrently run based on a pair of non-overlapping clocks, Φ1 and

Φ2 [see Figure 1.1(c)]. When a stage (say, stage i) is in the amplify phase, the next

stage (stage i+1) is in the sample phase to acquire stage i’s residue. Therefore, two

consecutive stages always operate in opposite phases. In the next clock phase, stage i

alternates back to the sample phase and it is free to acquire the next input sample,

while stage i+1 generates its own residue based on the sample obtained in the previous


clock phase. This operation continues through the pipeline until the last stage

generates the final digital bits. Due to this pipelined stage operation, each stage is

processing different input samples at a given time, and the speed of the entire ADC is

identical to that of a single stage.

One important observation about the pipelined stage is that the majority of power

is consumed by the residue amplifier. This is because the sub-ADC is typically formed

using just a few voltage comparators, and the sub-DAC and the adder are passive. Due

to the significant power contribution of the residue amplification, low-power pipelined

ADC designs typically focus on designing efficient residue amplifiers.

1.2.2 Multiplying Digital-to-Analog Converter (MDAC) Circuit

Usually, the sub-DAC, the adder and the amplifier in pipeline stage are combined

into a single block called MDAC. Figure 1.2 shows a typical design of a 1.5 bit per

stage switched-capacitor MDAC [9]. The circuit is operated based on two phases,

sample and amplify. In the sample phase, the input voltage, VI, is acquired on the

sampling capacitors. Then, in the amplify phase, the charge stored on CS is

redistributed onto CF, generating the residue voltage, which is given by

V C CC · V CC C V . (1-1)

In this expression, VDAC is the output voltage of the sub-DAC block.

VIVO

VDAC

VOCS

CF

CS

CF

[Sample] [Amplify]

CL

MUX

VR

0

-VR

D

Figure 1.2: Operation of an MDAC circuit.

Chapter 1: Introduction 5

1.3 Organization

This dissertation consists of six chapters. Chapter 2 presents the design of the

proposed single-stage class-AB amplifier, which features dynamic power cycling.

Chapter 3 starts with the principles of the deterministic background calibration and the

spline-based calibration, and then it explains the implementation of the proposed

schemes to handle the gain error in the residue amplifiers. Chapters 4 and 5 discuss the

architecture and measurement results of an experimental ADC which is designed to

demonstrate the feasibility of the idea presented in Chapters 2 and 3. Finally, Chapter

6 concludes with a summary and suggestions for future work.


7

Chapter 2

Design of an Efficient Class-AB

Amplifier

Class-AB amplifiers are known as power-efficient alternatives to conventional

class-A amplifiers because they can, in principle, provide large drive currents on

demand, without drawing large static currents [12], [13]. Class-AB amplifiers have

been typically designed based on a high gain input stage followed by a class-AB

output stage in order to simultaneously provide a large DC gain and a large signal

swing (see Figure 2.1) [14], [15]. Unfortunately, due to the large power needed to bias

and drive the output stage with a high-gain input stage, the improvements seen in

class-AB designs have so far been limited, especially when the output drives only a

moderate load capacitance. In this chapter we introduce an efficient, single-stage

design of a class-AB amplifier for pipelined ADCs.

VI VO

High-Gain Input Stage Class-AB Output Stage

Figure 2.1: Block diagram of a typical two-stage class-AB amplifier.

8 Chapter 2: Design of an Efficient Class-AB Amplifier

2.1 Conceptual Overview

In order to improve the efficacy of the class-AB amplification, our approach is to

remove the high-gain input stage in the circuit of Figure 2.1 and try to build a residue

amplifier out of only the class-AB output stage. This section provides a brief and

conceptual overview of the single-stage class-AB amplifier proposed in this chapter,

and discusses why it is power-efficient. The detailed implementation of the concept is

discussed in Section 2.2.

Figure 2.2 shows the basic operation of a single-stage class-AB amplifier. This

circuit is formed using a PMOS transistor, an NMOS transistor and two bias voltage

sources, which control the quiescent point current of the two devices. Typically, the

devices are slightly on at the quiescent condition, so that the conduction angles of the

devices are a little larger than 180 degrees [12]. As a result, the static power

consumption of the amplifier is low.

VDD/2

VI

t

IN0

t

IP0

t

VI

VO

P0

N0

VDD

CL

Figure 2.2: Basic operation of a single-stage class-AB amplifier.

Suppose that a small-signal input around VDD/2 is applied to the circuit (assuming

that the circuit is configured to be at the quiescent condition with VI = VDD/2). Since

the input is tied to both transistors and controls them simultaneously, the amplifier

effectively has approximately twice the transconductance (gm) compared to class-A

amplifiers, where only a single transistor is controlled by the input.

Chapter 2: Design of an Efficient Class-AB Amplifier 9

For an input much lower than VDD/2, the NMOS is barely on, while the PMOS is

strongly active, pushing a large amount of current to the load (CL). For an input much

higher than VDD/2, only the NMOS transistor is strongly active, pulling a large amount

of current from the load. This push-pull action can dynamically boost the maximum

load current level well above the quiescent point level, quickly transferring a large

amount of current. As a result, the maximum load current is not bounded, unlike class-

A amplifiers, where the maximum load current is limited to the bias current. Therefore,

the class-AB amplifier doesn’t slew.

Another advantage of the proposed circuit in Figure 2.2 is that the amplifier can

be built to exhibit fast turn-on and turn-off times because it has a small number of

nodes that need to be switched to cut the flow of current. This property makes it

suitable to apply dynamic power cycling to the amplifier; the amplifier is turned off to

further save power when it is not utilized for amplification (see Section 2.2.5 for the

implementation).

Now suppose that this class-AB amplifier is used in a two-phase closed-loop

switched-capacitor feedback configuration (see Section 1.2.2). Due to the capacitor

switching between the phases (sample and amplify), the amplifier’s input is effectively

driven by transient voltage steps, and the amplifier’s output settles exponentially (see

Figure 2.3). This behavior is similar to that of a class-A amplifier. Figure 2.4(a) shows

the supply and load currents in a conventional class-A amplifier, while Figure 2.4(b)

shows those in the class-AB amplifier featuring the dynamic power cycling. Note that

the load currents in Figure 2.4(a) and (b) are similar, while the supply currents are

different. In class-AB amplifier, the supply current is nearly zero during the sample

phase due to the dynamic power cycling (only a small leakage current flows), and it

dynamically changes according to the load current during the amplify phase. However,

the supply current of the class-A amplifier stays constant. This class-AB amplifier

therefore utilizes charge drawn from the supply more efficiently.


G

CL

VOVI

ILoad

ISupply

Figure 2.3: Input and output transient voltages of a switched-capacitor class-A/class-

AB amplifier.

[Sample] [Amplify]

t

I

[Sample] [Amplify]

t

I

(a)

(b)

ILoad

Wasted Charge

ISupply

ISupply

ILoad

Figure 2.4: Supply and load current waveforms. (a) Waveform of a class-A amplifier.

(b) Waveform of a class-AB amplifier that features dynamic power

cycling.

Unfortunately, a disadvantage of this architecture is a significantly degraded DC

gain that results in nonlinear gain errors. This error will be explained in more detail in

Section 2.2.6, and it will be addressed using the calibration scheme discussed in

Chapter 3.


2.2 Detailed Circuit Description

2.2.1 MDAC with a Single-Stage Class-AB Amplifier

Figure 2.5 shows a half circuit schematic of the MDAC portion of a pipeline stage

using the proposed amplifier (the sub-ADC, consisting of conventional dynamic

comparators, is omitted). The full circuit is pseudo-differential and combines two

copies of this circuit that are connected as indicated in the drawing (for charge

sampling). The Cgd neutralization technique [16] is used for the amplifier transistors,

N0 and P0, but the implementation of this is omitted in Figure 2.5 for clarity (see

Figure 2.6 for the implementation of the technique). The load capacitor, CL, is

comprised of the next stage’s sampling capacitors, CS and CF. The quiescent point

current of N0 and P0 is set by the dynamic biasing capacitors, CBN and CBP. These

capacitors are functionally the same as the batteries shown symbolically in Figure 2.2.

The pre-charge voltages VBN and VBP are generated using diode-connected MOSFET

devices and constitute about 20 percent in bias power dissipation.

VI

Φ2

Φ2

VDAC

VCM

VCM

To negative half circuit

CS

CF

Φ3,4

Φ1,3

Φ1 Φ2e

VCM

Φ4

Φ4

P0

N0

CBN

CBP

Φ1

VBN

Φ1

VBP

Φ1

CL

Φ4

Φ4

To negative

half circuit

Φ4e

Φ1 : Reset

Φ2 : Sample

Φ3 : Compare

Φ4 : Amplify

Bootstrapped

A

Stage1 Stage2

Figure 2.5: MDAC implementation.


N0P N0N

NNP

NNN

Figure 2.6: Cgd neutralization for transistor N0 (subscripts P and N indicate the positive

and negative half circuits, respectively). The gate widths of NNP and NNN

are designed to half the widths of N0P and N0N.

The MDAC operates in four non-overlapping phases: reset, sample, compare, and

amplify. In the reset phase, the voltages across all capacitors are initialized,

eliminating residual charge from the previous clock cycle (see Figure 2.7). In the

sample phase, the input voltage, VI, is acquired on the sampling capacitors, CS and CF

(see Figure 2.8). The input sampling switches are bootstrapped during the sampling to

improve linearity [17], [18], and bottom plate sampling is used to suppress signal

dependent charge injection (the switch controlled by Φ2e opens early) [19], [20]. Note

that node A is connected to the same point in the other half of the pseudo-differential

circuit. Therefore, this node is floating while sampling the input. This configuration

samples the input only differentially and rejects the input common-mode (CM) voltage

to first order. Assuming no input CM deviations, the voltage at the node A stays

around VCM, as initialized in the reset phase. In the compare phase, the sub-ADC

makes its decision and switches in the proper DAC voltage, VDAC (see Figure 2.9).

Finally, in the amplify phase, the charge stored on CS is redistributed onto CF,

generating the residue voltage (see Figure 2.10). Note that N0 and P0 carry bias current

only during the amplify phase. This is due to the dynamic power cycling technique

employed in this circuit (see Section 2.2.5 for further details).


VCM

VCM

CS

CF

VCM

CBN

CBP

VBN

VBP

Stage1

Bootstrapped

Φ1 : Reset

Initialize

Φ1

Φ1 Φ1

Φ1

Φ1

Stage2

Figure 2.7: Reset phase schematic.

VI


CS

CF

Bootstrapped

Φ2 : Sample

A

Signal ChargeΦ2

Φ2

Φ2e

Stage1 Stage2

Figure 2.8: Sample phase schematic.


VDAC

VCM

CS

CF

Bootstrapped

Φ3 : Compare

Φ3

Φ3

Stage1 Stage2

Figure 2.9: Compare phase schematic.

VDAC

CS

CF

Bootstrapped

Φ4 : Amplify

To negative

half circuit

CL

Signal Charge

Redistribute

Φ4

Φ4

Φ4

Φ4

Φ4

Φ4e

Stage1 Stage2

CBN

CBP

Figure 2.10: Amplify phase schematic.


In this class-AB configuration, the gm of N0 and P0 add, and the amplifier does not

slew. In addition, the circuit allows for a relatively large differential output swing,

which helps reduce the size of the required sampling capacitances in each stage. The

output of the amplifier is a function of the input, the sub-DAC output, the sampling

capacitances and the closed-loop gain (GCL) of the amplifier as expressed below.

V G · V CC C · V . (2-1)

Here, GCL is a function of the sampling capacitances and the loop gain (T) of the

amplifier, and T is a function of the sampling capacitances and the transistor

parameters. The expressions for GCL and T are given below, respectively.

G C CC · TT 1. (2-2)

T CC C C C · g g · r || r . (2-3)

2.2.2 Differential Input Sampling

In the circuit of Figure 2.5, the input is sampled with node A connected to the

same point in the other half of the pseudo-differential circuit. To see the effect of this

configuration more clearly, Figure 2.11 shows the full differential input network

during the sample phase (subscripts P and N are used for indicating the positive and

negative half circuits, respectively). CPP and CPN shows the total parasitic capacitance

hanging at nodes AP and AN, respectively. These capacitances are dominated by the

gate capacitances of N0 and P0 and parasitic capacitances of CBN and CBP (see Figure

2.5). For the CM component of the input, the connection between the nodes AP and AN

is effectively open, while for the differential-mode (DM) component of the input the

nodes AP and AN are virtual grounds. As a result, the circuit of Figure 2.11 can be


reduced as the circuits in Figure 2.12(a) and (b) for CM and DM input signals,

respectively.

Φ2

Φ2CSP

CFP

Φ2e

AP

Φ2

CSN

Φ2

CFN

CPP

CPN

VIP

VIN

AN

Figure 2.11: The full circuit of the differential input network in the sample phase.

Φ2

Φ2CS

CF

CP

VI,DM

Φ2

Φ2CS

CF

(a)

(b)

VI,CM

A

CM:

DM:

Figure 2.12: Half circuits for the input network in the sample phase. (a) The CM half

circuit. (b) The DM half circuit.


From the CM half circuit in Figure 2.12(a), the CM voltage of the node A is given

by

V ,# V# ∆V,# · C CC C C%, (2-4)

where ∆VI,CM is the input CM voltage deviation. Equation (2-4) indicates that when CP

is much smaller than CS + CF, VA,CM tracks the input CM voltage very well during the

sample phase. Next we will investigate how the voltage behaves in the compare phase

(see Figure 2.13). Assuming that the CM of VDAC (VDAC,CM) is VCM, VA,CM returns

exactly back to VCM, perfectly rejecting the effect of input CM voltage deviation. This

is true because the total CM charge stored at node A (the average of the total charge

stored at nodes AP and AN) is preserved during the process.

Φ3

Φ3CS

CF

CP

VDAC,CM

A

VCM

CM:

Figure 2.13: The CM half circuits for the input network in the compare phase.

The above conclusion was reached with an assumption that the two half circuits

perfectly match each other. However, when mismatch is taken into account, the input

CM deviation is not rejected completely. For Figure 2.11, let’s analyze the effect of

the mismatch between CPP and CPN (CSP = CSN = CS and CFP = CFN = CF are still

assumed for simplicity). With the mismatch, the effective parasitic capacitances

during the sample phase and during the compare phase are different. As a result, the

voltage at node AP (VAP) at the end of the sample phase is given by


V % V# ∆V,# · C CC C C%% C%&2

, (2-5)

while the voltage at the end of the compare phase is given by (VDAC,CM = VCM is

assumed for simplicity)

V % V# ∆V,# · C CC C C%% C%&2

∆V,# · C CC C C%%

V# ∆V,# · 1 C%% C%&2 · (C C) ∆V,# · 1 C%%C C

V# ∆V,# · C%% C%&2 · (C C) . (2-6)

Similarly, the voltage at node AN (VAN) at the end of the compare phase is given by

V & V# ∆V,# · C%& C%%2 · (C C) . (2-7)

Now these voltages have both CM and DM components, which are respectively given

by

CM: V % V &2 V#. (2-8)

DM: V % V & ∆V,# · C%% C%&C C . (2-9)


Interestingly, the result shows that CM voltage of VA is still VCM. However, due

to the effective capacitance modulation of CP between the sample and compare phases,

the input CM deviation is transformed into a DM error at the output, which is given by

V,# 2 · ∆V,# · C%% C%&C C . (2-10)

This error is not a problem as long as ∆VI,CM changes very slowly. When ∆VI,CM

is almost constant, the error contributes to the global offset which is fine in many

applications. The effect of the mismatches between the sampling capacitors (which

was initially ignored in the above analysis for simplicity) is very similar to that of CP

mismatch, and it also results in transforming the input CM deviation into an output

DM error.

The above analysis confirms that input CM deviation doesn’t manifest itself as an

output CM deviation even with the presence of the mismatch. This is because the total

CM charge stored at node A is preserved. However, this is not true when the leakage

current at node A is taken into account. Since the CM voltage of the node A at the end

of the sampling phase is changed by the input CM as expressed in (2-4), the leakage

currents can also vary according to the input CM. This will result in changing the

output CM and the quiescent operating point of the amplifier. This can be a problem

because any variation in the amplifier characteristic due to the input CM deviation

cannot be addressed by the calibration scheme explained in Chapter 3. As a result, the

effect of the leakage current modulation due to the input CM must be designed small.

2.2.3 Output CM Stability

In the proposed MDAC circuit, no explicit CM feedback circuitry is needed.

This is accomplished by the following two features of the circuit. First, the amplifier

has a single-stage architecture whose input and output is coupled through CF during

the amplify phase (see Figure 2.14). Unlike a fully differential input pair with a tail

current source, the pseudo-differential pair has a relatively large CM gain, which is


sufficient to provide feedback to control CM output voltage by itself. Second, the

input CM is rejected to first order due to the previously mentioned differential input

sampling. Without this sampling technique, any input CM deviation will be amplified

by the stage gain and appears as an output CM deviation (because of the pseudo-

differential architecture). Since several stages are cascaded in the pipelined ADC, the

output CM deviation in the last stage will be large and saturate the DM output signal.

However, with the input CM rejection, the output CM voltage is set only by the CM of

VDAC, and thus the CM deviation doesn’t accrue as the input signal propagates through

the pipeline stages.

VOP VON

CS CF

VDACP

CSCF

VDACP

Figure 2.14: Simplified schematic of the MDAC circuit in the amplify phase.

2.2.4 Noise

The total integrated output noise of the MDAC circuit consists of three major

components: bias noise, input sampling noise and amplifier noise. Approximate half

circuit expressions for these noise sources are given below (see [7], [21], [22] for more

detailed information on noise analysis in switched-capacitor circuits).


N./0 v2333 kTC.& kTC.% (2-11)

N05/ v2333 kTC ·C C C CC (2-12)

N 5/6/708/ v2333 γ · kTC:: ·g gβ · g β · g. (2-13)

Here, γ is the so-called white noise factor (2/3 for a long-channel MOS device), CTOT

is the total capacitance seen at the output of the amplifier, and βn and βp are the return

factors from the output of the amplifier to the gates of N0 and P0, respectively.

2.2.5 Dynamic Power Cycling

Similar to the switched-opamp scheme proposed previously [23], [24], the

amplifier devices N0 and P0 carry a bias current only during the amplification phase.

The turn-on in our design is controlled by the Φ4 switches at the output (see Figure

2.5), which simultaneously act as the sampling switches for the next stage. This

reduces the total resistance of the network, allowing for fast transients. In the next two

sub-sections, we will discuss the details on the turn-on switches and the turn-on

transient of the amplifier.

2.2.5.1 Implementation of the Turn-on Switches

To implement low-overhead turn-on switches that do not introduce any additional

series resistance to a critical signal path, the next stage’s sampling switches are

modified in a way that they simultaneously act as the turn-on switches of the amplifier

as well as the sampling switches for the next stage. This is accomplished in the

following conceptual steps. First, the next stage’s sampling switch is split into two

pieces [see Figure 2.15(b)]. Up to this change, the circuit is identical to what was

before in term of its operation. Second, the direct connection between the drains of N0


and P0 is removed [see Figure 2.15(c)]. After the change, the amplifier devices N0 and

P0 carry a bias current only during the amplification phase through the shaded path

denoted in Figure 2.15(d), and they are off in all other phases. Note that throughout

the modification, no additional switches are added, and the total resistance of the

network is maintained.

P0

N0 CL

Φ4

Stage1 Stage2

(a)

Divided

into twoP0

N0 CL

Stage1 Stage2

Φ4

Φ4

(b)

No

conn.

P0

N0 CL

Stage1 Stage2

Φ4

Φ4

(c)

Act as the turn-on

switches as well as the sampling

switches

P0

N0 CL

Stage1 Stage2

Φ4

Φ4

(d)

Figure 2.15: Implementation of low-overhead turn-on switches. (a) Basic amplifier

schematic. (b) Amplifier schematic after splitting the Φ4 switch. (c)

Amplifier schematic after disconnecting the drains of P0 and N0. (d) Final

amplifier schematic, indicating the current path.


2.2.5.2 Fast Turn-on Transient of the Amplifier Architecture

Figure 2.16 shows the simplified schematic of the amplifier featuring the dynamic

power cycling. This amplifier has only two nodes (A and B) that are being switched

when turning on and off the amplifier. Before the amplifier is turned on, the nodes A,

B and C are separately charged to VDD, GND and VCM, respectively [see Figure

2.16(a)]. However, at the onset of turning on the amplifier, the three nodes are

connected together, and they rapidly share charges that are previously stored in their

total node capacitances [see Figure 2.16(b)]. The total capacitances of nodes A and B

are dominated by the drain capacitances of P0 and N0, respectively. If CL is designed

much larger than the drain capacitances, the output voltage of the amplifier starts at a

value somewhere near VCM. This makes the turn-on transient of the amplifier even

faster, since the amplifier needs to settle the small perturbation at the output. This

feature, combined with the previously proposed amplifier switching mechanism,

allows for on and off transients that contribute only a very small timing overhead.

P0

N0 CL

Stage1 Stage2

Φ4

Φ4

(a)

P0

N0 CL

Stage1 Stage2

Φ4

Φ4

(b)

A

B

C

VDD VDD

Figure 2.16: Simplified schematic of the amplifier (a) before and (b) after turning on.

2.2.6 Maximum Swing and Nonlinearity

The maximum output swing of the amplifier is limited by the minimum drain-to-

source saturation voltages of N0 and P0 (see Figure 2.17). As the output voltage

approaches the rails, the overall output resistance of the transistors decreases, thereby

reducing the amplifier gain. In our design, partly due to the low loop gain, the


resulting nonlinearities are significant at the 12-bit accuracy (which is the target

accuracy of the prototype ADC explained in Chapter 4). In order to address this issue,

we employed a nonlinear correction scheme explained in Chapter 3.

P0

N0

Max

Swing

VDS_MIN

VDS_MIN

VI

VO

Figure 2.17: Amplifier output swing analysis. The plot shows the conceptual closed-

loop transfer function of the proposed amplifier.

2.3 Summary

This chapter has presented an efficient class-AB amplifier based on a pseudo-

differential, single-stage, cascode-free and CMFB-free architecture. In addition, the

low complexity of the overall circuit makes it suitable to employ dynamic power

cycling to further reduce power when the amplifier is not in use. With this

combination, the proposed amplifier can deliver most of the supply current to the load,

unlike conventional class-A amplifiers. However, the cost of the simplified amplifier

architecture is a significantly degraded DC gain that results in nonlinear errors. In

order to address this issue, we propose a digital background calibration scheme in the

next chapter.

25

Chapter 3

Deterministic Background Calibration

Background calibration and rapid parameter convergence are desirable features of

ADC calibration schemes. The calibration process should run continuously in the

background, without interrupting the normal ADC operation. Also, the calibration

algorithm should rapidly adapt so that calibration parameters can track any drift due to

ambient conditions such as temperature. Otherwise, the ADC will only slowly recover

from performance degradation after a sudden environmental change. In addition, the

calibration scheme is preferred to be able to calibrate nonlinear correction parameters.

However, these desirable features are somewhat mutually exclusive, making it

hard for a calibration scheme to exhibit all three features at the same time. Background

calibration is done in many of the statistics-based methods [2], [25]-[29]. In these

calibration schemes, a pseudorandom sequence is used to modulate a behavior of an

ADC such as the sub-ADC offset [2] or DAC segment selection [25]. Such

modulation is adopted to reveal the information on target calibration parameters while

maintaining the integrity of the ADC’s foreground input processing operation.

Therefore, this scheme is naturally performed in the background. However, a large

number of samples (typically millions of samples) are required in general to

successfully decorrelate and extract the calibration-related information from the ADC

output. In [29], this problem is addressed by using a so-called “split ADC” scheme,

where an ADC is split into two channels and the calibration is developed from the

output difference between the two channels. Since the difference doesn’t contain the

large input signal, the extraction of the calibration-related information can be done

much faster (in about 10,000 samples).

26 Chapter 3: Deterministic Background Calibration

A rapid algorithm convergence can be observed in many of the deterministic

calibration methods [30]-[33]. Unlike the statistics-based schemes, a deterministic

method provides an analog test signal directly to an ADC and puts the ADC in a

special “offline” mode of operation. As a result, the ADC typically does not convert

the input signal while performing the calibration [30], [31]. However, there are also

some deterministic schemes that can run in the background [32], [33]. They typically

introduce some form of redundancy, such as additional stages [32] or extra conversion

speed [33], in order to handle the limitation. In any case, since it is possible to directly

observe the ADC’s response to the test signal, a deterministic calibration can be

performed fast.

Calibration of nonlinear parameters has been studied in [2], [27], [33]. In [2] and

[33], third order harmonic distortion in a residue amplifier gain is modeled and

corrected. In [27], a more general way of dealing with the harmonic distortions in a

residue amplifier is presented. However, a nonlinearity calibration scheme typically

exhibits a longer time constant for the algorithm to converge, simply because it needs

to extract more information compared to linear calibration schemes. For example, the

statistics-based schemes in [2] and [27] require about ten million and four billion

samples to converge, respectively.

This work presents a deterministic background calibration scheme that features

nonlinear gain error correction for the residue amplifiers. This scheme is deterministic

in that it provides an analog test signal for calibration. However, by measuring the

circuit imperfections in time intervals between normal conversion cycles, this

calibration operates continuously in the background. In addition, this scheme handles

the digital linearization of the amplifier transfer function using a spline-based

correction method. This method utilizes a piecewise function to effectively handle the

high-order distortion in the transfer function. For the nonlinear calibration scheme

used in this work, it takes only about 3000 clock cycles to adapt the calibration of a

single frontend pipeline stage and about 22,000 cycles to adapt the calibration of the

entire ADC (based on the prototype ADC architecture explained in Chapter 4).

Chapter 3: Deterministic Background Calibration 27

3.1 Overview

As pointed out in Chapter 2, the proposed amplifier exhibits nonlinear gain errors,

partly due to the low loop gain. Typically, this makes the amplifier unsuitable for high

resolution applications unless its accuracy is digitally enhanced using a calibration

scheme. Figure 3.1 shows the block diagram of an ADC with digital nonlinearity

calibration (a similar block diagram can be found in [34]). Note that the post-processor

block is added from the block diagram of Figure 1.1, and the backend stages (from 2

to n) and their corresponding digital logic in Figure 1.1 are combined into the backend

ADC block. As illustrated in the figure, the analog nonlinearity in the residue

amplifier is digitally corrected using an inverse function estimated in the post-

processing block.

+

-

A/D

+ G

D/A

Backend

ADC

DO

VI

VO

D1

Stage 1

Analog

Nonlinearity

Digital

Inverse

Post-

processor

ΣΣΣΣ

Correction

DBE Dx

Estimation

Figure 3.1: Block diagram of an ADC with digital nonlinearity calibration.


In order to calibrate the residue amplifier, we first need an appropriate model of

the amplifier, so that the interpolation error between the model and the amplifier is

small. For example, in [34], an open-loop residue amplifier is modeled using a third

order polynomial function. Our approach uses a so-called spline-based scheme to

model the characteristic of the class-AB amplifier proposed in Chapter 2. Section 3.2

will provide a detailed description of the spline-based modeling. Next, we will discuss

a deterministic background calibration scheme that measures the calibration

parameters based on the amplifier model. A deterministic digital test signal is injected

to the input of sub-DAC for the proposed calibration. A detailed description of the

calibration scheme and the test signal will be presented in Section 3.3. Finally, Section

3.4 will describe the implementation of the calibration algorithm.

3.2 Spline-Based Nonlinearity Modeling

For the proposed class-AB amplifier, the closed-loop transfer function is given by

the following expression (see Section 2.2.1 for more information).

V G · V CC C · V . (3-1)

In this equation, there are two terms that need to be calibrated, GCL and <<=> . The

first term, GCL, is a nonlinear function of the input, while the second term, <<=> , is a

constant. Therefore, we address the first term using a spline-based nonlinear

calibration and the second term using Karanicolas calibration [31], which are further

discussed in this section.

Figure 3.2 shows the principle of the spline-based calibration scheme. The

amplifier’s nonlinear closed-loop gain function is piecewise modeled by a few low-

degree polynomial functions (four third order polynomial functions in the case of

Figure 3.2). These piecewise polynomials are called splines, and each spline is

modeled separately with a different set of coefficients.


x

y

Spline 1

Spline 2

Spline 3y′1

y′2

y′

x′

y0

y1

y2

x1 x2x0 x′1 x′2

Spline 4

0

0

Figure 3.2: Four-section spline-based model.

The advantage of using this scheme is that each spline can become a weakly

nonlinear function, even though the whole transfer function shows higher order

nonlinearities. Therefore, modeling and digital linearization of a spline are relatively

simple. In our implementation, a spline is modeled using a third order polynomial

function which is given in x′ and y′ coordinate system by

xA f(yA) cE · yA cF · yAF . (3-2)

Here, x′ and y′ are new coordinates, whose transformations are achieved by

xA x xG , yA y yG . (3-3)


The spline function can be also expressed in the x and y coordinate system by

x xG cE · (y yG) cF · (y yG)F . (3-4)

Note that in the spline model, x is expressed as a polynomial function of y, not vice

versa. This eliminates the need for a complicated inverse function of a polynomial as

in [34]. This modeling can be done without incurring large interpolation errors since

splines are weakly nonlinear. The coefficients of a spline function (c1 and c3) can be

estimated using a simple matrix operation given by

HcEcFI JyEA yEA Fy2A y2A FKLE MxEAx2A N . (3-5)

Therefore, measuring the amplifier at three equally-spaced points is sufficient to

characterize a spline function as in Figure 3.2 (nine equally-spaced points in total for

four sections).

Note that this method also deals with the second order nonlinearity in the transfer

function, even though each spline is modeled without a second order component. This

is because the transfer function is divided along the y axis so that the “positive”

portion (spline 3 and 4) and the “negative” portion (spline 1 and 2) are calibrated

separately. As an example, let’s assume that the transfer function of an amplifier is

given by the following polynomial function.

y cE · x c2 · x2 . (3-6)

Then, the positive and negative portions can be expressed as

y cE · |x| c2 · |x|2 , for x P 0, (3-7)

y cE · |x| c2 · |x|2 , for x R 0. (3-8)


From this expression, we see that the first order component affects the two portions in

the opposite direction, while the second order component affects them in the same

direction. By dealing with the two portions separately, the spline-based calibration

makes it possible to accommodate the effect of the second order distortion using the

third order component. This is illustrated in Figure 3.3.

x

y

x

y

+ = x

y

Figure 3.3: Modeling of second order nonlinearity using third order spline functions.

Figure 3.4 shows the effect of the four-section spline-based calibration on the

total harmonic distortion (THD) of amplifiers whose transfer functions are given by,

y x c/ · x/ , for i 2, 3, 5 and 7. (3-9)

The results shown in the figure are labeled c2, c3, c5 and c7, respectively. Assuming

that the THD without calibration is over 40 dB, THD is improved with calibration by

more than 30 dB for c2, c3 and c5 and by more than 20 dB for c7.


Figure 3.4: The effect of the four-section spline-based calibration on THD.

When the even order harmonic distortion of an amplifier’s transfer function is

negligible, spline 2 and 3 (in Figure 3.2) can be combined as in Figure 3.5. In this case,

x′ and y′ can be transformed from x and y by

xEA xF xE2 , x2A xZ xG2 , (3-10)

yEA yF yE2 , y2A yZ yG2 , (3-11)

and the spline function can be expressed in x and y coordinate system by

x x2 cE · (y y2) cF · (y y2)F . (3-12)

For the calibration of residue amplifiers in the experimental ADC described in

Chapter 5, the three-section spline-based calibration scheme is used. This is because

the even order harmonic distortions of the amplifiers turn out negligible based on the

measurement result of the ADC.


x

Spline1

Spline2

Spline3

y′1

y′2

y′

x′

y3

y4

x4x3 x′1 x′2x1

x2, y2

x0

y0

y1

Averaged

0

0

y

Figure 3.5: Three-section spline-based calibration.

After the digital linearization based on the spline calibration, the residue plot

becomes very linear as in Figure 3.6. Note that the three curves, whose corresponding

D1 value is 00, 01 and 10 (D1 is the output of the sub-ADC in the first stage; see

Figure 3.1), are linearized using the same sets of correction coefficients, since their

characteristics are identical.

Now, the <<=> term in Equation (3-1) needs to be further calibration using

Karanicolas calibration. This scheme measures two parameters; h1 and h2 (see Figure

3.6). The parameter h1 is the difference between the quantized representation of the

amplifier output when D1 = 00 and D1 = 01 with VI = –VR/4, and h2 is the difference

between the quantized representation of the output when D1 = 01 and D1 = 10 with VI

= VR/4. These parameters are used to correct the errors in stage gain as follows.

D D[ hE, if DE 00 (3-13)

D D[, if DE 01 (3-14)


D D[ h2, if DE 10, (3-15)

where DX is the backend ADC code after corrected using the spline-based method, and

DO is the final ADC output (see Figure 3.1). Therefore, the Σ block in Figure 3.1,

which is also shown in Figure 3.7(a), is implemented as Figure 3.7(b).

In order to calculate h1 and h2, the amplifier characteristic must be additionally

measured at two more points (one with D1 = 00 and VI = –VR/4 and the other with D1

= 10 and VI = VR/4). Measurement results at the other two points (one with D1 = 01

and VI = –VR/4 and the other with D1 = 01 and VI = VR/4) will be shared with the

spline-based calibration.

VI

VO

D1 = 00 D1 = 01 D1 = 10

h1 h2

VR-VR

Spline1

Spline2

Spline3

Figure 3.6: Residue plot after spline-based nonlinearity correction.

ΣΣΣΣDO

D1

Dx DO

D1

Dx+

MUX -h1

0

h2

(a) (b)

Figure 3.7: Implementation of Σ block in Figure 3.1.


3.3 Deterministic Background Calibration

3.3.1 Overview

In order to calibrate a residue amplifier based on the model described in Section

3.2, the amplifier characteristic must be measured at 11 points in total (nine points for

the spline-based nonlinearity calibration and the additional two points for Karanicolas

calibration). This can be accomplished by providing a deterministic analog test input

at the following nine points (with an appropriate D1 value).

M 48, 38, 28, 18 , 0, 18, 28, 38, 48 N · V_. (3-16)

In our approach, a digital test signal is injected to the input of the sub-DAC,

where it is converted into an analog signal and provided to the residue amplifier.

Section 3.3.2 will discuss this process in more detail. In Section 3.3.3, a deterministic

background calibration scheme that measures the amplifier characteristic without

interrupting its normal operation is proposed. This scheme uses the test signal

injection method discussed in Section 3.3.2. The proposed deterministic background

calibration shows some similarities with a “queue-based” scheme proposed in [33] in

that both techniques sacrifice conversion speed to make it deterministic and

background. However, the proposed calibration scheme doesn’t use two clocks as in

the queue-based scheme.

3.3.2 Providing a Test Signal

In order to provide an analog test input [see (3-16) for the required test input

values], the pipeline stage is modified to have two operation modes, as in Figure 3.8.

During the normal mode, the stage is configured like a conventional pipeline stage. In

the calibration mode, the input of the sub-DAC is switched to a digital test input

(DTest), and the sub-DAC converts the test input into analog. Note that the sub-DAC in

a pipeline stage is utilized as a test input DAC when performing the calibration, so no


additional DAC is needed for the analog test input generation, unlike in [33]. However,

the sub-DAC is slightly modified to perform as a test DAC, and the detailed

implementation of this sub-DAC is explained in Section 3.4.4 and 3.4.5.

+

-

VIN VOUT

DOUT

DTest

+

-

VIN VOUT

DOUT

DTest

[Normal]

[Calibration]

A/D

A/D D/A

+

+

G

G

Utilize sub-DAC

as a test input DAC

D/A

Modified for Calibration

Figure 3.8: Stage’s mode of operation.

3.3.3 Deterministic Background Calibration

As mentioned in Section 3.3.2, the pipeline stage has two modes of operation

(normal and calibration). In the proposed calibration scheme, the stage ping-pongs

between these two modes from cycle to cycle. As a result, the overall stage output is

the time-interleaved version of the outputs in normal and calibration mode (see Figure

3.9 for a conceptual output signal). In this way, the circuit imperfections can be

measured in time intervals between normal conversion cycles, and a deterministic

calibration can be performed in the background. Since it is unnecessary to re-calibrate

the amplifiers in each calibration cycle, the calibration is duty-cycled and the

amplifiers are turned on and dissipate calibration-related power only every eighth

clock cycle. As a result, the power overhead due to this calibration algorithm is

relatively small, compared to the overall ADC power.


Time

Amplifier turned on

every eighth clock cycle

Normal

Calibration

Figure 3.9: Conceptual stage output with the deterministic background calibration.

3.4 Implementation

This section describes the proposed pipelined ADC architecture that employs the

spline-based nonlinearity modeling and deterministic background calibration scheme

previously discussed in Section 3.2 and Section 3.3, respectively. In this section, the

calibration idea is extended so that it can be applied to every pipeline stage in the

ADC.

3.4.1 ADC Architecture

Figure 3.10 shows the block diagram of an ADC featuring the proposed

calibration. The shaded blocks indicate added or modified components for the

calibration of ADC, relative to a conventional pipelined ADC. The calibration control

state machine manages the calibration process and generates the necessary control

signals (DTest, Stage_sel and Frame). The DTest signal provides the digital test input for

the calibration of the residue amplifier in each stage. The Stage_sel signal selects the

stage to be calibrated. The Frame signal provides information that helps the post-

processing block to align the calibration-related ADC outputs according to their test

input values and stage indexes. A DAC in each stage converts the digital test input

into an analog signal and provides it to the residue amplifier for calibration. This DAC


is a modified version of the sub-DAC used in a conventional pipeline stage, as

mentioned in Section 3.3.2. The test output from the stage is further processed by the

backend portion of the ADC. The clock generation block is also modified to provide

the necessary clock signals for calibration. The post-processing block estimates the

calibration parameters and corrects the MDAC’s errors.

DAC

OutputInputStage 1 Stage N

Backend

ADC

DAC

Clocks

CLK

CLKCK11 CK21 CK1N CK2N CK1B CK2B

Additional Blocks

for Calibration

Blocks Modified

for Calibration

processor

Post-

Stage_sel Frame

Calibration Control State Machine

DTest

Figure 3.10: ADC block diagram featuring the proposed calibration.

3.4.2 Stage Calibration Sequence

The Stage_sel signal, which is provided by the calibration state machine [see

Figure 3.11(a)], controls the sequence and timing of the stage calibration. It is an N-bit

signal, where only a single bit is asserted at a time in a round-robin fashion [see Figure

3.11(b)]. The stages are sequentially calibrated based on the signal from stage N to

stage 1. Once stage i is fully calibrated, the algorithm proceeds with the calibration of

stage i-1 and works its way toward the frontend of the converter. Therefore, when

stage i is being calibrated, it assumes that all the proceeding stages are already

calibrated and sufficiently accurate.


111

Stage_sel [1:N]

N

Stage_sel

[1]

Stage_sel

[2]

Stage_sel

[N]

Direction of Calibration

Stage_sel [1]

Stage_sel [2]

Stage_sel [3]

Stage_sel [N]…

Stage Select Timing Diagram

DAC

Stage 1 Stage 2

DAC

Stage N

DAC

(a) (b)

Figure 3.11: Stage calibration sequence. (a) Direction of calibration. (b) Timing

diagram of Stage_sel signal.

3.4.3 Clocking Scheme

As illustrated in Section 3.3.3, the pipeline stage’s conversion cycle in this

calibration scheme is split into two sub-cycles of equal length – one for normal

conversion and one for calibration. This is accomplished by operating the stage based

on two clocks, one of which is duty-cycled (see CK1i and CK2i in Figure 3.10, where

the subscript i indicates the stage index). These two clocks separately control two sub-

cycles. Figure 3.12 shows the detailed timing diagram of the two clocks. In each

conversion cycle, the timing further splits into four clock phases.

During the normal sub-cycle (CK1i), stage i always operates in the normal mode.

However, the stage doesn’t necessarily operate in the calibration mode during the

calibration sub-cycle (CK2i). In order for the stage to operate in the calibration mode,

two conditions must be met: the stage is in the calibration sub-cycle and the

corresponding Stage_sel[i] signal (ith

bit of the Stage_sel signal) is exerted. Figure

3.12 also shows the timing diagram of the stage modes. Note that when Stage_sel[1]

signal is exerted, stage 1 is in the calibration mode during its calibration sub-cycle

(CK21), and all the backend stages are in the normal mode in their respective

calibration sub-cycles. This is because the backend stages need to digitize the


calibration-related residue generated by stage 1. Similarly, when Stage_sel[2] signal is

exerted, stage 2 is in the calibration mode during its calibration sub-cycle (CK22), and

all other stages are in the normal mode during their respective calibration sub-cycles.

N N N N N N N N N N C N

CK12

CK22

Stage1 Mode

Stage_sel[1]

N N N N N NStage2 Mode

Stage_sel[2]

CK11

CK21

N N N N N N N N N N N NStage3 Mode

N C N N N N

Φ1 Φ2 Φ3 Φ4

Φ1 Φ2 Φ3 Φ4

Φ1 Φ2 Φ3 Φ4

Φ1 Φ2

N: Normal

C: Calibration

Figure 3.12: Timing diagram of clocks, control signals and stage modes.

3.4.4 Test Input DAC Implementation

In order to measure the amplifier characteristic at the desired 11 points, the sub-

DAC function of the stage must provide the nine levels in the calibration mode as

described in Section 3.3. This is accomplished by splitting the sampling capacitors CS

and CF into four equal pieces, as shown in Figure 3.13(a). Each one of the unit

capacitors can be charged separately with +VR, 0 or -VR in the sample phase

depending on the digital value of DTest provided by the calibration control state

machine. For example, if three of the unit capacitors are charged to VR, while other


five are charged to 0, the corresponding analog test input voltage is 3/8 ⋅ VR [see

Figure 3.13(a)]. Similarly, this DAC can produce the other eight levels using the

proper combinations of +VR, 0 or -VR for charging the unit capacitors. Figure 3.13(b)

illustrates the sub-DAC output after the capacitor splitting.

CS

CF

VR

VR

VR

0

0000

Sub-DAC

VTest = 3/8 ⋅ VR

[Sample]

To negative half circuitP0

N0

VDD

(a)

VR

VI

-VR 0 4/8 ⋅⋅⋅⋅VR

-4/8 ⋅⋅⋅⋅VR

-3/8 ⋅⋅⋅⋅VR

-2/8 ⋅⋅⋅⋅VR

-1/8 ⋅⋅⋅⋅VR

1/8 ⋅⋅⋅⋅VR

2/8 ⋅⋅⋅⋅VR

3/8 ⋅⋅⋅⋅VR

Conventional sub-DAC output

Additional sub-DAC output

(b)

Figure 3.13: Sub-DAC with capacitor splitting. (a) Circuit schematic. (b) Sub-DAC

output after the capacitor splitting.

3.4.5 Dynamic Element Matching of Unit Capacitors

When an analog test input is used to calibrate an ADC, the input must be much

more linear than the target linearity of the ADC. This imposes stringent accuracy


requirements on a test input DAC. In order to improve the linearity of the test input

DAC levels, the unit capacitors are shuffled from cycle to cycle. This technique is

known as dynamic element matching (DEM) [35]-[39], and is widely used in sigma-

delta modulators and oversampling DACs.

There are a few varieties of DEM based on the shuffling method of the unit

elements [35]. The random averaging approach [36] relies on shuffling the DAC

elements in a random fashion, so that it can translate the harmonic distortion

components caused by mismatch into white noise. The clocked averaging approach

[37] relies on periodically permuting the DAC elements at a given clock frequency.

This technique moves the harmonic distortion components into regions around

multiples of the clock frequency. The limitation of this method arises when a tone

generated upon modulation falls inside the passband of the DAC. This problem can be

addressed by using more advanced approaches such as individual level averaging

(permuting the DAC elements on a per level basis) [38] or data weighted averaging

(permuting the element based on the data sequence) [39].

In our implementation, the clocked averaging approach is used. Figure 3.14 shows

a permutation method of the eight unit capacitors in our DAC. Here, IN1 - IN8

represent the unit capacitors before the permutation, while OUT1 - OUT8 represent the

unit capacitors after the permutation. The order of the unit capacitors change based on

a three-bit counter, which increases every cycle and comes back to initial zero in every

eight cycle. The primary advantage of using clocked averaging is the relatively simple

implementation. In addition, the previously mentioned limitation is not a problem in

our application, since we can freely choose the test input sequence in this DAC such

that the generated tones do not deteriorate the digital test input. In our implementation,

the digital test input changes only once in every 32 cycles and the 32 output results are

averaged. Since the input stays constant during any single averaging cycle, all the

elements are equally used when averaging. Also, the thermal noise in the DAC after

averaging is reduced by √32 (= 5.7).


IN1

IN3

IN2

IN4

IN5

IN7

IN6

IN8

OUT1

OUT3

OUT2

OUT4

OUT5

OUT7

OUT6

OUT8

Figure 3.14: Permutation method of the eight unit capacitors.

One issue in this DEM method occurs due to the nonlinear nature of the amplifier

under test. In a typical DEM, the transfer function from the point of capacitor

shuffling to the point of averaging is assumed linear. This is necessary for the

mismatch errors to perfectly cancel out. However, in our implementation the averages

are formed after passing through the amplifier nonlinearity (see Figure 3.15), and thus

a residual error exists after the DEM.

Test

DAC

DEM

3-bit

counter

G

Backend

ADC

Averaging

Block

Nonlinear

amplifier

Test

input

Test

output

… …

32 samples

Time Time

Averaged for a single

output sample

Figure 3.15: Calibration path diagram.


The attainable precision of this scheme can be analyzed using some assumptions

about the amplifier transfer function and the capacitor mismatch. First, it is assumed

that the third order harmonic distortion dominates the amplifier nonlinearity, and the

transfer function is given by

V GE · V GF · VF, for V 12 ~ 12. (3-17)

Here, we assumed that VI is normalized by VR for simplicity, and the maximum input

value is 1/2 [because the maximum sub-DAC output is 1/2 ⋅ VR as shown in Figure

3.13(a)]. Second, it is assumed that the capacitor mismatch is given by

C/ Cb ∆C/ , for i 1, 2, …8, (3-18)

d∆C/e

/fE 0, (3-19)

where C1 - C8 are the unit capacitors of the DAC, Cu is the nominal value of the unit

capacitor, and ∆C1 - ∆C8 are the mismatch of the unit capacitors.

Based on the above assumptions, the amplifier outputs with and without capacitor

mismatch (after DEM) for the maximum input value of VI = 1/2 are given by,

V,g/8h b8 GE 12 GF 12F (3-20)

V,g/8h 132 · diGE j∑ Cl mn(/=Z·o)pZ/fE 8 · Cb q GF j∑ Cl mn(/=Z·o)pZ/fE 8 · Cb qFrF2

ofE


GE s12 · j∑ C/e/fE8 · Cb qt GF i12 · j∑ C/Z/fE8 · Cb qF 12 · j∑ C/e/fu8 · Cb q

Fr

GE 12 GF 12F i12 · j1 ∑ ∆C/Z/fE4 · Cb qF 12 · j1 ∑ ∆C/e/fu4 · Cb qF r

v GE 12 GF 12F i1 32j∑ ∆C/Z/fE4 · Cb q2 32 · j∑ ∆C/e/fu4 · Cb q2 r

GE 12 GF 12F i1 3j∑ ∆C/Z/fE4 · Cb q2 r (3-21)

Therefore, the residual error due to the amplifier nonlinearity for the maximum input

value is given by

E0x V,g/8h V,g/8h b8V,g/8h b8 GF y12zF s3 ∑ ∆C/Z/fE4 · Cb 2 t

GE y12z GF y12zF

v 34 · GFCE j∑ ∆C/Z/fE4 · Cb q2 (3-22)

v GFCE ∆CC

2 (3-23)

This error is very small since it is a product of G3/G1 (a ratio between first and third

order coefficients of the closed-loop amplifier transfer function) and (∆CS/CS)2 (the

squared ratio of mismatch to the ideal capacitance).


3.4.6 Implementation of Post-Processing Block

The correction and estimation blocks in Figure 3.1 can be implemented as shown

in Figure 3.16 (three-section spline modeling is used). First, the nonlinear coefficient

estimation block calculates the sets of coefficients (ck, x0 and y0) for each spline, and it

supplies them to MUX2. Then, each backend ADC code (DBE) is corrected by the

nonlinearity correction block using a third order polynomial function. In this process,

MUX2 decides on which spline DBE is located, and it chooses the right set of

coefficients for the polynomial correction. After the nonlinear errors are corrected, the

coefficients, h1 and h2, are estimated in the Karanicolas coefficient estimation block,

and they are supplied to MUX1 and the adder for the <<=> term correction [See

Equation (3-1)]. In this correction block, only four additions, four multiplications and

two multiplexing operations are required in total. The correction sub-block operates at

a frequency of 9/8 times the sampling frequency, since it needs to handle the

correction of both normal and calibration ADC outputs. The estimation sub-block runs

at a frequency of 1/8 the sampling frequency and processes only the calibration-related

ADC samples.

Stage 1Backend

ADC

+

0

-h1

h2

MUX1

DX = x0 + c1 ⋅ (DBE - y0) + c3 ⋅ (DBE - y0) 3Correction

Nonlinear Coeff. Est.

KaranicolasCoeff. Est.

MUX2

ck, x0, y0Spline3’s ck, x0, y0

Spline1’s ck, x0, y0

Spline2’s ck, x0, y0

DTest

D1

VI

DO

Estimation

DX DBE

Nonlinearity Correction:

Figure 3.16: Post-processing block diagram.


3.4.7 Calibration of Backend Stages

Since the accuracy in the backend stages is not as critical as in the frontend stages,

it is not necessary to use nonlinear calibration in these stages. Instead, only

Karanicolas calibration is employed. As a result, there are a few differences in the

calibration of the backend stages. First, the amplifier characteristic is measured at four

points (instead of 11 points) to measure h1 and h2. Therefore, the sub-DAC needs to

provide two additional levels, +VR/4 and –VR/4 (see Figure 3.17), and capacitors CS

and CF are split into two equal pieces. For the post-processing of the stage, only

MUX1, an adder and the Karanicolas coefficient estimation blocks are implemented.

VR

VI

-VR 0 2/4

⋅⋅⋅⋅VR

-2/4

⋅⋅⋅⋅VR

-1/4

⋅⋅⋅⋅VR

1/4

⋅⋅⋅⋅VR

Conventional sub-DAC output

Additional sub-DAC output

Figure 3.17: Sub-DAC with capacitor splitting. (a) Circuit schematic. (b) Sub-DAC

output after the capacitor splitting.

3.4.8 Convergence of the calibration

Despite the duty cycling, the proposed calibration algorithm converges quickly,

due to its deterministic nature. For the nonlinear calibration scheme used in this work,

it takes only about 3000 clock cycles. This is because in a single calibration cycle, the

amplifier characteristic is measured at 11 points, 32 times each. With the duty-cycling,

the total number of clock cycles required is 11⋅32⋅8 = 2816. For the linear calibration

scheme used in the backend stages, it takes about 1000 clock cycles (4⋅32⋅8 = 1024) to

converge. When calibrating the whole ADC, the calibration adaptation times for each

stage add due to the sequential nature of the proposed calibration scheme. In order to


calibrate the experimental 12-bit ADC described in Chapter 4, approximately 22,000

cycles are required (3000⋅4+1000⋅10). At the clock frequency of 30 MHz (which is the

case for the prototype ADC), this requires only 0.73 ms, which is much faster than

statistics-based schemes [2], [27].

3.5 Summary

This chapter described a deterministic background calibration scheme for the

residue amplifier proposed in Chapter 2. First, the conceptual overview of the

amplifier calibration in pipelined ADC was presented in Section 3.1. Next, Section 3.2

described a spline-based nonlinearity modeling, where the amplifier’s input and output

closed-loop transfer function is piecewise modeled by a few low-degree polynomial

functions, called splines. In this scheme, each spline can become a weakly nonlinear

function, even though the whole transfer function is significantly nonlinear. Therefore,

modeling and digital linearization of a spline are relatively simple. Based on the

amplifier model, a deterministic background calibration is proposed in Section 3.3.

This scheme measures the circuit imperfections in time intervals between normal

conversion cycles. Since it is unnecessary to re-calibrate the amplifier in each cycle,

the calibration is duty-cycled to reduce the calibration-related power overhead. Finally,

in Section 3.4, the detailed implementation of the proposed calibration scheme is

described.

49

Chapter 4

Pipelined ADC Design

This chapter describes the design of a low-energy 12-bit pipelined ADC in 90-nm

CMOS utilizing the proposed class-AB amplifiers and the deterministic background

calibration scheme. The main purpose of the design is to demonstrate the low power

consumption of the converter afforded by the proposed amplifier. The transistors in

the amplifier are carefully sized to harness the full efficiency benefits of the amplifier,

and all other blocks within the converter are carefully designed so that they don’t

contribute significantly to the overall ADC power consumption. These low-power

design choices are explained in this chapter.

4.1 ADC Architecture

Figure 4.1 shows the block diagram of our 12-bit prototype pipelined ADC. The

target speed of the ADC is 30 MS/s. The core pipeline structure consists of fourteen

stages, all of which use the proposed class-AB amplifier architecture, followed by a

two-bit backend flash ADC. These stages are designed based on typical 1.5 bit per

stage architecture, which has two comparators for the sub-ADC [9]. The stages are

scaled down by a factor of two per stage (sampling capacitors and device widths), up

to stage 5. Stages 6-14 are identical copies of stage 5. The state machine is

implemented on-chip for the proposed calibration scheme, as described in Chapter 3.

The clock and bias blocks are also implemented to provide necessary timing and bias

for the core pipeline stages. The digital circuitry for data alignment and nonlinear error

correction is implemented off-chip.

50 Chapter 4: Pipelined ADC Design

DAC

Dout

Vin

Calibration Control

State Machine

Time Alignment

Stage_selDTest

Stage 1 Stage 14

DAC

1.5b 2b

Nonideality Estimation and Correction

12b

On Chip

Clock

Gen

Bias

Gen

Vref

Vclk AVDD

Backend

ADC

1.5b

DVDD

Frame

Figure 4.1: Block diagram of the 12-bit prototype pipelined ADC.

Master clock and reference voltages are generated off-chip. A low-voltage sine

wave is provided for the master clock input, and it is converted to CMOS using a

buffer chain implemented on chip. The frequency of the input clock is four times the

sampling frequency (120 MHz). This is because one half of the conversion clock cycle

is allocated for amplifier calibration and to generate the non-overlapping four phase

clocking scheme, without any on-chip frequency doubling. A supply voltage of 1.2 V

(both digital and analog supplies) is used for the ADC.

The gain of the residue amplifier in each stage is approximately 1.8 due to the

small loop-gain of the amplifier (see Section 4.2 for more information). Therefore, the

total ADC effectively provides approximately 14-bit quantization [14 ⋅ log2(1.8) + 2 =

13.9 bits]. The extra two bits provide redundant decision levels for the correction of

the ADC [2].

Chapter 4: Pipelined ADC Design 51

The stages are digitally calibrated in a round-robin fashion from stage 14 to stage

1, as discussed in Chapter 3. Stages 1-4 are calibrated for nonlinear gain errors based

on the proposed spline calibration scheme, whereas all other stages are calibrated only

for linear errors using Karanicolas calibration. After the correction, the ADC output is

truncated to 12 bits. Table 4.1 summarizes some of the specifications and design

parameters for the ADC.

Table 4.1: Specifications and design parameters for the ADC.

Parameter Value

Resolution 12 bits

Sampling rate 30 MS/s

Master clock frequency 120 MHz

VDD 1.2 V

4.2 MDAC

The MDAC portion of each stage is implemented as described in Section 2.2.1. In

this section, we will present the device sizes and design parameters of the MDAC

circuit in the first stage, and we will discuss the low-power design choices for this

circuit.

Figure 4.2 shows a half circuit schematic of MDAC (this figure is identical to

Figure 2.5, but repeated here for convenience). The device sizes and design parameters

are listed in Table 4.2. The gate lengths of N0 and P0 are designed 160 nm (the

prototype design is fabricated in a 90-nm CMOS process as mentioned in Chapter 5).

This is to design the gate capacitances much smaller than CS, CF, CBN and CBP, while

maintaining intrinsic gains (gm⋅ro) of approximately 20. The resulting gate

capacitances of N0 and P0 are 0.12 and 0.16 pF, respectively. Such small gate

capacitances allow for an improved feedback factor [see Equation (2-3)].


VI

Φ2

Φ2

VDAC

VCM

VCM


CS

CF

Φ3,4

Φ1,3

Φ1 Φ2e

VCM

Φ4

Φ4

P0

N0

CBN

CBP

Φ1

VBN

Φ1

VBP

Φ1

CL

Φ4

Φ4

To negative

half circuit

Φ4e

Φ1 : Reset

Φ2 : Sample

Φ3 : Compare

Φ4 : Amplify

Bootstrapped

Stage1 Stage2

ID

Figure 4.2: MDAC implementation in the first stage.

Table 4.2: Device sizes and design parameters in the circuit of Figure 4.2.

Device/Parameter Size/Value

P0 120 um / 160 nm

N0 80 um / 160 nm

CS, CF 1 pF

CBP, CBN 1.5 pF

Cggn 0.12 pF

Cggp 0.16 pF

VDD 1.2 V

Quiescent ID 0.15 mA

Full input range 1.8 Vp-p-differential


Since CS and CF are designed equal, the nominal closed-loop gain is equal to two.

The loop gain (T) of the amplifier is about 10 [see Equation (2-2)], causing a static

gain error of approximately 10% in the closed-loop gain [see Equation (2-3)].

Therefore, the closed-loop gain (GCL) is approximately 1.8. Figure 4.3 shows the

closed-loop gain of the first stage, simulated using SPICE.

Figure 4.3: Simulated first stage gain.

In the circuit of Figure 4.2, the maximum load current can be well above the

quiescent point current level since it is a class-AB amplifier. The ratio between the

maximum load current and the quiescent point current depends on three design

parameters: gm/ID, β and VO,Final. Here, gm and ID are the transconductance and the

drain current of the amplifying transistor (P0 or N0 in Figure 4.2), respectively, β is the

closed-loop feedback factor and VO,Final is the final output voltage of the amplifier. The

ratio increases as any of the three parameters increases.

Figure 4.4 shows a SPICE-simulated waveform of the supply and load currents

for the proposed residue amplifier. The supply current waveform is obtained by

measuring the drain current of P0 (in one of the two half circuits), and the load current

waveform is obtained by subtracting the drain current of N0 from the drain current of

P0 (in the same half circuit). The time allocated for the amplify phase is around 4 ns,

and the waveform is shifted in time so that the amplify phase starts at time = 0. The


simulation result shows that the supply current changes very dynamically according to

the load current, delivering most of the supplied charge to the load. The supply current

is about 1.8 mA at its maximum, and it is reduced to about 0.15 mA once it is settled.

The large increase in the current level is the result of large gm/ID values of amplifying

transistors (which are around 20 S/A for both P0 and N0), and the relatively large input

voltage of 1.8 Vp-p (differential). The supply current flowing before the amplify phase

is less than 1 uA, which is the drain current leakage while the amplifier is turned off.

Figure 4.4: Simulated waveform of the supply and load currents.

4.3 SHA-less Frontend

Conventionally, pipelined ADCs have a dedicated frontend sample-and-hold

amplifier (SHA) to sample the input through a single path and to provide a settled

value of the input for the first pipeline stage. This configuration prevents the first

stage’s MDAC and sub-ADC blocks from sampling different values of the input signal.

However, due to the linearity and low noise requirements imposed on the frontend

SHA, it typically consumes a significant amount of overall converter power, which is

not acceptable in our low-energy ADC design.


In order to reduce the overall ADC power, no frontend SHA is used in our design

[6], [40], [41], [42]. Instead, the MDAC and the sub-ADC sampling paths are

carefully designed to match each other, so that the difference between the sampled

input values of the two paths are not significant. This difference is given in the

following equation for an input of A⋅sin(ω⋅t) [40].

V|| | A · ω · l(TE T2) (τ2 τE)p. (4-1)

where, T1 and T2 are the sampling time instances of the MDAC and the sub-ADC

paths, respectively, and τ1 and τ2 are the time constants of the MDAC and the sub-

ADC sampling networks, respectively. In our design, the layout traces of the sampling

clocks for both paths are carefully drawn to match in order to reduce the sampling

timing skew, and a matched input network similar to the one described in [42] is used

to reduce the difference between the bandwidths of the two paths. Analysis and

simulation results showed that these techniques ensure that the maximum error plus

the comparator offset doesn’t exceed the maximum tolerable sub-ADC error allowed

by 1.5 bit per stage architecture. For the stage gain of 1.8 and a differential input range

of 1.8 Vp-p, the maximum tolerable error is ±275 mV as shown in Figure 4.5.

VI

VO

VR-VR

275 mV

Gain = 1.8

Figure 4.5: Maximum tolerable sub-ADC error.


4.4 Comparator

In ADC designs where highly efficient residue amplifiers are used, the sub-ADC

blocks can contribute an appreciable portion of the total converter power. Therefore,

power-efficient dynamic latch comparators are used without any preamplifiers in order

to reduce this power contribution. The comparator design used in this ADC is similar

to the one presented in [43], [44].

Figure 4.6 shows the schematic of the dynamic latch comparator. When the ΦLatch

signal fires, the input pair, M2 and M3, starts to pull the nodes A and B to ground,

respectively. During this process, any small voltage difference between the two nodes

is generated according to the input. Shortly later, the cross-coupled inverter pair (M5-

M8) starts to amplify the difference through regenerative action.

M1ΦLatch

M2 M3

M4

M5 M6

M7 M8M9 M10

ΦLatch

ΦLatch ΦLatch

VIP VIN

VDD

A B

Figure 4.6: Schematic of our dynamic latch comparator.


Since this comparator doesn’t consume static current, the power consumption is

determined by the dynamic power needed to switch the transistors. Therefore, to keep

the comparator power low, small size transistors are used (W = 480 nm for NMOS

transistors and W = 720 nm for PMOS transistors). One drawback of using these

transistors is the large input referred offset of the comparator. Monte Carlo simulations

revealed that the standard deviation of the input referred offset is less than 30 mV.

This offset is small considering the total tolerable sub-ADC error of ±275 mV in our

design.

The input sampling network of the sub-ADC is designed similar to that of MDAC

in order to employ a matched input network technique as described in the previous

section (see Figure 4.7). Two sampling networks (one for each comparator) subtract

either VR/4 or –VR/4 from the input and provide the result to comparators (because of

the 1.5 bit per stage architecture [9]). Here, VR is a differential signal which is

generated using two reference voltages, VRP and VRN (VR = VRP – VRN). In order to

prevent the sub-ADC sampling network from significantly loading of the previous

stage, the sampling switches and the sampling capacitors (in each path of the sub-

ADC) are scaled down by a factor of 20 compared to those in the MDAC. Therefore,

4⋅C is equal to (CS+CF)/20 in Figure 4.7.


3⋅⋅⋅⋅C

C

Φ2e

C

VIP

VIN

Φ2

Φ2

Φ2

Φ2

3⋅⋅⋅⋅C

VRP

Φ1,3,4

Φ1,3,4

VRN

Φ1,3,4

VCM

Φ1

VCM

Φ1

Φ3

Figure 4.7: Sub-ADC schematic (only one out of two comparator channels is shown).

4.5 Reference Generation

In pipelined ADCs, providing stable reference voltages is of great concern. This is

because any noise in the reference voltage directly appears as an error in the stage

residues, degrading the overall ADC performance [46].

The major source of the noise in the reference voltage is due to dynamic

switching of load capacitors in the MDAC, sub-ADC and test input DAC blocks. The

load capacitance varies from phase to phase and from cycle to cycle due to the signal-

dependent modulation in capacitor switching. In order to prevent the performance

degradation, any deviation due to the charging events must settle down within the

allocated time interval.


A stable reference is typically achieved by using an active reference buffer and a

bypass capacitor to handle low and high frequency noise components. Such a

combination can provide the low output impedance of the reference block at all

frequencies, so that any noise can settle quickly. A review of the literature shows that

there are three ways to implement the combination: an internal buffer with an internal

bypass capacitor as in Figure 4.8(a) [45], an internal buffer with an external bypass

capacitor as in Figure 4.8(b) [46], and an external buffer with an external bypass

capacitor (and optional internal bypass capacitor) as in Figure 4.8(c) [47]. There are

pros and cons for internal and external implementations. The use of an internal bypass

capacitor (typically on the range of 0.1 nF) requires a large die area, while the use of

an external bypass capacitor may introduce significant ringing noise on the reference

voltage. This noise is due to the resonant effect between the bond-wire inductor (LBond)

and the load capacitor (CLoad). If such oscillation is large enough to degrade the ADC

performance, a series resistor can be added or an additional on-chip bypass capacitor

can be used as in [47]. The series resistor lowers the Q factor of the resonant circuit,

while the additional on-chip bypass capacitor reduces high frequency current flow

through the bond wire. One caveat in adding the internal bypass capacitor is that the

capacitor may introduce even more ringing noise if it has a high Q factor. Therefore,

the internal capacitor must be properly de-Qed.

In our implementation, an external buffer and an external bypass capacitor are

used as in Figure 4.8(c). Extensive simulations at fs = 30 MHz with the assumption of

LBond = 5 nH are carried out in order to identify the presence of ringing noise in the

network. Fortunately, in our prototype ADC the on-resistance of the switch provides

sufficient damping of the ringing noise. Therefore, unlike [47], no internal bypass

capacitor is added.

The following techniques are also employed in order to further guarantee the

integrity of the reference. Layout techniques are employed to isolate the reference

traces from other noisy traces. For the external bypass capacitor, several capacitors

with various sizes are used in parallel for effective bypassing at all frequencies. These

capacitors are placed right next to the chip to reduce any parasitic inductance from the


PCB traces. The chip die is placed within a QFN package so that the length of bond

wire for the reference voltage is as short as possible.

VR

CBypass CLoad

Internal

buffer

CExt

LBond

Off-chipOn-chip

CLoad

VR

CExt

LBond

Off-chipOn-chip

CLoadCBypass

(Optional)

(a)

(b)

(c)

On-chip

Internal

buffer

VR

External

buffer

Figure 4.8: Reference voltage generation. (a) An internal buffer with an internal

bypass capacitor. (b) An internal buffer with an external bypass capacitor.

(c) An external buffer with an external bypass capacitor (and optional

internal bypass capacitor).


4.6 Supply Regulator

Due to the low loop-gain provided by the proposed amplifier architecture, supply

rejection of the amplifier is poor. As a result, the linearity of the ADC drops quickly as

the supply varies (see Section 5.3.7 for a measurement result). This is especially true

when the supply changes much faster than the time constant of the calibration

algorithm (about 0.73 ms), which makes it impossible for the calibration algorithm to

track the changes. This problem can be resolved by using a dedicated supply regulator

as suggested in [6]. Since the total power consumed by all the supply noise sensitive

blocks (amplifiers and biasing circuitry) is less than 2 mW, building a low-power

supply regulator for such a power level is a manageable task.

4.7 Output Multiplexing and LVDS Signaling

The core pipeline structure, which is comprised of 14 1.5-bit stages and a two-bit

backend flash ADC, generates 30 output bit streams. The bit rate of each bit stream is

2⋅fs, because of the calibration performed in the time interval between normal

conversion cycles. In order to use low-voltage differential signaling (LVDS) in

transferring the data without using an excessively large number of package pins, 30

outputs are first multiplexed to 15 outputs and then transferred through LVDS (see

Figure 4.9). Finally, the 15 bit streams are differentially transferred at the rate of 4⋅fs.

This requires 30 package pins in total.

30 single-ended bits

at 2 ⋅ fs

MUX

2x

15 single-ended bits

at 4 ⋅ fs

LVDS

Transmitter

15 differential bits

at 4 ⋅ fs

Figure 4.9: Output processing.


4.8 Summary

This chapter described the overall design of a low-energy 12-bit 30-MS/s

pipelined ADC utilizing the proposed amplifiers and the calibration scheme. To

further lower the power consumption for the overall ADC, the frontend SHA is

removed and dynamic latch comparators are used. Instead of using a dedicated SHA,

matched sampling networks are employed for the first stage’s MDAC and sub-ADC in

order to make them sample a closely matched value of the input signal. The following

chapter will discuss the test results from the prototype ADC designed based on the

architecture described in this chapter.

63

Chapter 5

Experimental Results

The prototype pipelined ADC was fabricated by UMC (United Microelectronics

Corporation) in a 90-nm CMOS process and occupies an active area of 0.36 mm2

(excluding off-chip voltage generation and I/O). Figure 5.1 shows the die photograph

along with the layout. The active area consists of four parts, which are pipeline stages,

bias, clock and a state machine. The core pipeline structure, which is magnified in

Figure 5.2, shows 14 stages followed by a two-bit backend flash ADC. The raw 30

bits from all 15 stages (two bits from each stage) are further processed in the off-chip

post-processing block, where they are calibrated and truncated to 12 bits for

measurements.

Active Area = 0.36 mm2 Bias Pipeline stagesClock State machine

Figure 5.1: Die photograph and layout.

64 Chapter 5: Experimental Results

Layout of

pipeline stages

Stage index 1 2 3 4 5 6 ~ 14

Relative scale x16 x8 x4 x2 x1 x1

Figure 5.2: Layout of the pipeline stages.

5.1 Prototype Die

The prototype chip has 70 pads in total. Among them, 30 pads are dedicated for

15 differential LVDS bit streams (as explained in Section 4.7). Due to the relatively

large number of required pads, the dimensions of the die are pad-limited to 1.75 mm

by 1.75 mm.

The chips are packaged in a QFN56 (quad flat no lead 56 pins) package, even

though the total number of pads is 70. This was made possible by down-bonding 14

VSS pads directly to the lead frame paddle of the package as in Figure 5.3. This metal

plate is connected to the ground voltage provided from the outside of the package. The

down-bonding makes it possible to reduce the lengths of bond-wire connections

because the QFN56 package is smaller than a QFN72 package, which could have been

used instead.

Down-bonding

Figure 5.3: Down-bonding.

Chapter 5: Experimental Results 65

5.2 Test Setup

A custom-designed four-layer printed circuit board (PCB) was manufactured to

interface the ADC with the test equipment. The QFN-packaged ADC chip is attached

to the board with a tension socket manufactured by Ironwood Electronics. The clock

and input sinusoids are generated by two phase-locked sine wave generators (Model:

HP8644B). The generated input sinusoid is band-pass filtered to reduce the harmonic

distortion components in the signal. When evaluating the ADC using Fast Fourier

Transforms (FFTs), the clock and input frequencies are carefully chosen to ensure that

the signal power is contained within a single FFT bin. This relationship of two

frequencies is often referred to as coherent frequencies, and the condition is given by

f/f N775N: . (5-1)

Sine wave

generator

Sine wave

generator

Phase-locked

BPF

ADC board

Input

Clock

Data

acquisition card

LVDS

PC

Voltage

generators

Supply & reference

Output & frame

Figure 5.4: Test setup.


Here, fin is the input frequency, fs is the sampling clock frequency, Ncycles is the integer

number of input cycles within the sampling window of FFT and NFFT is the integer

number of data points used for FFT. Also, it is further assured that Ncycles is a prime

number so that no two sampled input values within the sampling window are the same.

External voltage sources are used for the supply and reference voltages. The critical

voltages such as the three reference voltages (VRP, VRN and VCM), and the supply

voltages for the core analog components are isolated using separate voltage sources.

All supply and reference voltages are bypassed using combinations of various off-chip

capacitors. The outputs of this ADC are generated in LVDS format and run at four

times the sampling frequency (as explained in Section 4.7). These outputs are captured

using a data acquisition card (Model: NI PXI6562). The captured data are delivered to

a PC for the post-processing and performance analysis. Labview was used to control

the acquisition card and save the data to a PC, and Matlab was used to implement the

post-processing algorithm explained in Chapter 3 and to analyze the data. Table 5.1

summarizes the list of test equipments.

Table 5.1: Test equipment.

Sine wave generator Agilent 8644B

Voltage generator Agilent E3646A

Band-pass filter Mini-Circuits BPF

Data acquisition card National instruments PXI-6562


5.3 Measured Results

5.3.1 Dynamic Linearity

Figure 5.5 shows the output spectrum of the ADC with and without calibration at

fs = 30 MHz and fin = 1 MHz, and Figure 5.6 shows the output spectrum at fs = 30

MHz and fin = 14.8 MHz (near Nyquist frequency). A differential input swing of 1.8

Vp-p is used for the measurements, and 16384 samples are used for the FFT. For the

result without calibration, the nominal stage gain of 1.8 is assumed, and the stage

outputs are time-aligned and linearly summed based on the weight of 1.8. For the

result with calibration, the proposed calibration scheme explained in Chapter 3 is used.

In particular, the three-section spline-based calibration (see Figure 3.5) is employed,

because the even order harmonic distortions of the residue amplifiers turn out

negligible based on the measurement result (SNDR wasn’t improved by using the

four-section spline-based calibration). The measured SNDR/SFDR improves from

45.4/49.3 dB to 65.2/75.9 dB at fin = 1 MHz and from 48.2/52.6 dB to 64.5/78.1 dB at

fin = 14.8 MHz.

Figure 5.7 shows the measured peak SNDR (SNDR with the maximum input

swing) at fs = 30 MHz for input signals at 1 MHz, 10.7 MHz, 12.3 MHz and 14.8 MHz.

These input frequencies are chosen by the pass-band frequencies of the available

band-pass filters. As shown in the figure, the peak SNDR degrades only about 0.7 dB

when the frequency of the input signal changes from 1 MHz to 14.8 MHz. This

degradation is primarily due to increased clock jitter noise.

Figure 5.8 shows SNDR versus Vin,pp (the amplitude of the input sine wave). For

small signal inputs, each amplitude increase in dB results in approximately 1 dB

SNDR increase. This is because the performance is primarily limited by the thermal

noise, which is independent of the input amplitude. However, it is not true for large

signal inputs, since the distortion components become significant. As Vin,pp is

increased near full scale, the SNDR reaches its peak value and starts to decrease when

the distortion is about equal to the noise.



with and without calibration (fs = 30 MHz and fin = 1 MHz).



with and without calibration (fs = 30 MHz and fin = 14.8 MHz).


Figure 5.7: Measured peak SNDR versus input frequency (fs = 30 MHz).

Figure 5.8: Measured SNDR versus input amplitude (fs = 30 MHz and fin = 14.8 MHz).


5.3.2 Static Linearity

Figure 5.9 and Figure 5.10 shows the measured DNL and INL of the ADC

without and with calibration, respectively. Figure 5.11 shows the magnified version of

INL with calibration. The measurements were obtained using a sinusoidal code-

density test with about 300 thousand samples. The measured DNL and INL improve

from +2.10/-1 LSB to +0.82/-0.66 LSB and from +14.0/-14.8 LSB to +1.25/-1.54 LSB

with calibration, respectively. The calibrated DNL values indicate that the ADC has

no missing codes. The measured INL and DNL are primarily limited by the residual

errors after calibration. These residual errors exist because of the following two

reasons. First, the transfer function of a residue amplifier is piecewise modeled by

three third order polynomial functions as explained in Chapter 3. Therefore, part of

distortion components (especially high order distortions) is truncated in this modeling.

Second, each stage is calibrated based on the assumption that the backend stages are

ideal. In reality, the backend stages also have their own residual errors after calibration.

Therefore, calibrating a stage based on such backend stages may result in

accumulation of the uncompensated errors.


Figure 5.9: Measured DNL/INL without calibration.


Figure 5.10: Measured DNL/INL with calibration.

Figure 5.11: Measured INL with calibration (magnified).


5.3.3 Power

The ADC consumes 2.63 mW at fs = 30 MHz, excluding the off-chip reference

and I/O. This power can be broken down to 2.09 mW for amplifiers, comparators and

biasing circuitry and 0.54 mW for the calibration control state machine and clock

circuitry. The estimated power of the off-chip time alignment and digital calibration

logic is 0.32 mW (see Appendix A), yielding a total power of 2.95 mW. Together with

the SNDR measured at fin = 14.8 MHz, this yields a Walden FOM [48] of 72

fJ/conversion-step, which compares favorably to most designs with similar

specifications.

Figure 5.12 shows the measured power consumptions for various sampling

frequencies from 5 MHz to 50 MHz (fin = 1 MHz). The extrapolated y-intercepts show

that the static portion of the power consumption is 1.25 mW for the overall ADC, 1.2

mW for amplifiers, comparators and biasing, and 0.05 mW for the state machine and

clock power. The power for the state machine and clock is almost purely dynamic

(which scales linearly with frequency), while the power for amplifiers, comparators

and biasing has both static and dynamic components. The static portion is consumed

by the residue amplifiers in the amplification phase or bias circuitry, and dynamic

portion is consumed when switching sampling capacitors, turning on/off amplifiers,

and firing comparators.


Figure 5.12: Measured power consumption versus the sampling frequency (fin = 1

MHz).

5.3.4 Calibration Settling

Figure 5.13 shows the convergence of the proposed calibration algorithm at fs =

30 MHz and fin = 14.8 MHz. Each calibration cycle consists of about 22,000 samples

and takes about 0.73 ms at fs = 30 MHz (see Section 3.4.8 for more information). The

solid line shows the calibration settling result when the calibration parameters are

estimated based on the result measured over a single cycle and updated every cycle

(labeled “1-cycle averaging”). The dotted line shows the result when the calibration

parameters are estimated based on the result measured over two previous cycles and

updated every cycle (labeled “2-cycle averaging”). As evident, the result with 1-cycle

averaging tracks the parameters faster, but it dithers more once the system converges.


Figure 5.13: Calibration algorithm settling result (fs = 30 MHz and fin = 14.8 MHz).


5.3.5 Input Common-Mode Variation

Figure 5.15 shows the effect of the input common-mode (CM) variation on the

performance of the ADC at fs = 30 MHz and fin = 1 MHz. The amplitude of the input

sinusoid is set to 75 percent of the full scale, and the input CM is varied from 0.4 to

0.8 V. The figure shows that the peak SNDR is degraded less than 2 dB across the

tested CM input range for the ADC that is calibrated once at 0.6 V. Recalibration

results at each Vin,cm from 0.4 to 0.5 V are also shown for comparison. Note that the

peak SNDR doesn’t improve much with the recalibration. This is because the test

input CM voltage for the calibration scheme is fixed to 0.6 V, and thus, any error

which arises from the input CM deviation cannot be absorbed by the calibration.

Figure 5.14: Measured peak SNDR versus input CM variation (fs = 30 MHz and fin = 1

MHz).


5.3.6 Temperature Variation

In order to test the robustness of the ADC over temperature, the peak SNDR of

the ADC is measured as the temperature is varied from 30 °C to 90 °C. The chip

temperature was controlled either by a heat gun or a cooling spray. The ADC was

operating at fs = 30 MHz for a full-scale analog signal at the frequency of 1 MHz. In

order to estimate the on-chip temperature, an ESD diode is forward-biased using a

constant current, and the base-emitter junction voltage (Vbe) of the forward-biased

ESD diode is measured. Vbe of the diode is converted to the on-chip temperature based

on a look-up table formed using a SPICE simulated behavior of the diode.

Figure 5.15: Measured peak SNDR versus temperature variation (fs = 30 MHz and fin =

1 MHz).


Figure 5.15 shows the effect of temperature on the ADC’s linearity performance

with and without recalibration at each temperature. With recalibration the performance

of the ADC stays almost constant, while without recalibration, the peak SNDR drops

quickly at a rate of approximately -1 dB for each 3 °C increase in temperature. This is

due to the fact that temperature changes the transconductances of the transistors in the

residue amplifiers and in turn the stage gains. However, this change can be absorbed

by the proposed calibration scheme, since the time constant of the algorithm is shorter

than the typical time constant of temperature change.

5.3.7 Supply Variation

In order to test the robustness of the ADC over supply variations, the supply

voltages (both analog and digital supplies) of the ADC are varied from 1 V to 1.4 V.

The ADC was operating at fs = 30 MHz for a full-scale analog signal at the frequency

of 1 MHz. Figure 5.16 shows the measured peak SNDR versus the supply with and

without recalibration. The performance drops fast without recalibration, since changes

in the supply alter the operating points and headroom of the residue amplifiers. With

recalibration at each VDD, the performance stays flat over the supply changes from 1.2

V to 1.4 V, while it drops considerably (but slowly compared to the result without

recalibration) for the supply changes from 1.2 V to 1.0 V. This degradation for the

supply below 1.2 V is due to the reduced headroom of the residue amplifiers. With this

reduced headroom, the full-scale input gets significant distorted near the supply rail,

which makes it impossible to linearize up to the required accuracy even with the

nonlinearity calibration. In general, linearity degradation due to low frequency

changes in the supply will follow the upper curve in Figure 5.16, since most of the

change will be absorbed by the calibration. If the supply changes faster than the time

constant of the algorithm, the degradation will follow the lower curve. The result also

gives a hint about the power supply rejection ratio (PSRR) of residue amplifiers,

which are quite poor. Further robustness in supply variations can be achieved either by

replacing the residue amplifiers with high-PSRR amplifiers or by using a dedicated

supply regulator for the ADC.


Figure 5.16: Measured peak SNDR versus supply variation (fs = 30 MHz and fin = 1

MHz).

5.3.8 Performance Comparison

The performance of the experimental ADC can be compared with the state-of-the-

art pipelined ADC designs by plotting on the energy per conversion versus peak

SNDR plot (see Figure 5.17). In this plot, pipelined converter designs presented at the

International Solid-State Circuits Conference (ISSCC) and the VLSI Circuits

Symposium since 1997 [49] are shown along with the experimental ADC. The designs

within the dotted rectangle represent the state-of-the-art 12-bit pipelined ADC designs,

and this experimental ADC is among those best designs. Table 5.2 compares the

detailed specifications of this ADC with those of the state-of-the-art 12-bit pipelined

ADCs within the dotted rectangle.


Figure 5.17: Energy per conversion versus SNDR for ADCs published at ISSCC and

VLSI from 1997 to 2010.

Table 5.2: Specifications of state-of-the-art 12-bit pipelined ADC designs.

Tech.

(nm)

SNDR

(dB)

Power

(mW)

fs

(MHz)

FOM

(fJ/c-s) Reference

90 62 4.5 50 88 Brooks et al., ISSCC 2009 [50]

90 63.2 6.2 100 53 Chu et al., VLSI 2010 [51]

65 64.4 3.5 50 52 Lee et al., VLSI 2010 [52]

90 64.5 2.95 30 72 This Work

1.E+00

1.E+01

1.E+02

1.E+03

1.E+04

1.E+05

30 40 50 60 70 80 90

P/f

s(p

J)

SNDR (dB)

ISSCC 1997-2009

VLSI 1997-2009

ISSCC 2010

VLSI 2010

This Work


5.4 ADC Performance at fs = 50 MHz

The ADC performance at fs = 50 MHz for an 1-MHz full-scale input signal is

measured in order to identify what limits the performance at such high sampling

frequency. The quiescent point current of the ADC is increased by about 1.7 times so

that residue amplifiers can fully settle within the time interval of the amplify phase at

fs = 50 MHz. The total measured ADC power (excluding off-chip reference, I/O, and

digital post-processing) is 4.6 mW.

5.4.1 Linearity Degradation


without calibration (fs = 50 MHz and fin = 1 MHz).


Figure 5.18 shows the measured output spectrum of the ADC. The measured peak

SNDR is 62.0 dB, which is 3.2 dB lower than the performance at fs = 30 MHz. A

careful examination on the output spectrum reveals that there are seven tones

generated at the frequency of 5.25, 7.25, 11.5, 13.5, 17.75, 19.75 and 24 MHz,

respectively. The origin of these tones is not straight-forward, and rather “strange,”

because the frequencies of the tones don’t coincide with harmonic distortion

frequencies. Also, without these seven tones (see Figure 5.19), the peak SNDR is

improved back to 64.7 dB. This observation indicates that the tones are the dominant

source of the SNDR degradation at fs = 50 MHz. Therefore, in the next section, these

tones are investigated.

Figure 5.19: Output spectrum (16384 point FFT) after removing the seven “strange”

tones shown in Figure 5.18 (fs = 50 MHz and fin = 1 MHz).


5.4.2 Analysis

After the series of output spectrum measurements at fs = 50 MHz for input signals

with various input frequencies, we found out the locations of these error tones (for

both halves of the output spectrum) can be expressed in general as

f8 · k f/ , for k 1, 2, … , 7. (5-2)

The locations of the tones indicate that the error is related to the input signal frequency

and the frequency of calibration activity (which occurs once every eight normal

conversion cycles due to duty-cycling).

Figure 5.20(a) shows the time-domain representation of the error tones. This

waveform is obtained by taking the inverse FFT of the seven tones. We observed that

there are two interesting properties in this time-domain signal. First, the error signal

becomes large once every eight samples [see errors for the sample 1, 9, 18, and so on

in Figure 5.20(a)]. This once again suggests that the error is somehow related to the

duty-cycled calibration activity. So, let’s call this portion of the signal “duty-cycled”

error. Second, this duty-cycled error has the magnitude, which is highly linear to the

input signal shown in Figure 5.20(b). The correlation coefficient between the duty-

cycled error and the corresponding input signal within the FFT window (16384

samples) is -0.9999992. Therefore, this duty-cycled error can be expressed as

Errn enшen, (5-3)

en α · sin 2 · π · f/f · n LSB, for n 1, 2, … , N:, (5-4)

ш&n d δn rN|f/8|

, for n 1, 2, … , N:, (5-5)


where is the amplitude of the duty-cycled error envelope ( = 2.85 for the error

shown in Figure 5.20).

In summary, the duty-cycled error is linearly related to the input signal, and it can

be expressed as (5-3). This type of error can be attributed to the input kickback noise

generated from the frontend of our experimental converter. The next section analyzes

this kickback noise in more detail.

Figure 5.20: Time-domain representation of (a) the error tones and (b) the input signal

(measured using the ADC).


5.4.3 Source of the Error

Whenever the input is sampled by the frontend switched-capacitor stage, a large

kickback noise is generated due to the capacitor switching. This kickback noise must

die down before the next sample gets acquired.

Before investigating this noise further, we need to revisit the behavior of the first

stage. Figure 5.21 shows the sample timing diagram for the first stage (see Chapter 3

for more detailed information on CK1, CK2, Stage_sel and stage’s mode of operation).

When Stage_sel[1] is low (which means the first stage is not under calibration), the

stage is in the normal mode for both CK11 and CK21 sub-cycles. However, when

Stage_sel[1] is high (which means the first stage is currently under calibration), the

stage is in the normal mode for CK11 and the calibration mode for CK21.

N N N N N N N N N N C N

CK11

CK21

Mode1

Stage_sel[1]

Figure 5.21: Timing diagram for the first stage.

As a result, the input signal is sampled at instances depicted in Figure 5.22. This

unusual sampling doesn’t cause a problem as long as the input driver can absorb all

the transient kickback currents that are generated by capacitor switching. This is what

happens for the experimental chip running at fs = 30 MHz. However, at fs = 50 MHz,

the input driver fails to fully settle the transient currents within the allocated time

interval and results in errors (see Kickback noise in Figure 5.22).


Mode1 N N N N N N N N N N C N

Sampling Instance

Kickback noise

Figure 5.22: Sampling instance and behavior of kickback noise.

Because of the duty-cycled nature of the calibration, this residual error from the

kickback noise is also duty-cycled. In addition, the error linearly scales with the input.

Figure 5.23 illustrates the conceptual errors for a sinusoidal input. As can be seen, this

error is similar to the measurement result shown in Figure 5.20.

Sampling Instance

Input

Residual Errors

Figure 5.23: Conceptual errors due to unsettled kickback noise for a sinusoidal input.


Now, let’s think about the configuration of the input driving network (see Figure

5.24). In this setup, a single-ended sine wave is converted to a differential signal using

a balun (Rs ≅ 50 Ω for the matched termination of the input signal). The network

consisting of R1, C1 and C2 is widely used for isolating the balun’s secondary winding

from the ADC transient currents. In general, large R1, C1 and C2 give better isolation

but poor settling transient for the kickback noise, while small R1, C1 and C2 give the

opposite result. There are the optimum values for R1, C1 and C2, which can be

empirically found (R1 = 22 Ω, C1 = 10 pF and C2 = 0 F for the ADC).

C1

R1

R1

Rs

VI

C2

C2

VIP

VIN

ADC ChipVI2

+

-

VCM

Figure 5.24: ADC input driving network.

Using the above input driving network, the residual errors can be simulated using

SPICE. In the simulation setup, a full-scale sinusoidal input at 1 MHz is sampled by

the ADC at fs = 50 MHz. Then, the input values that are sampled in CS and CF of the

first stage are observed. Figure 5.25 shows the simulated spectrum of the sampled

input. This result agrees well with the measurement result in Figure 5.18.


Figure 5.25: Simulated spectrum of the sampled input (fs = 50 MHz and fin = 1 MHz).

5.4.4 Solution to the Problem

In a future design, the problem can be simply solved by changing the first stage

such that it does not sample for the CK21 sub-cycle when Stage_sel[1] is low. Figure

5.26 shows the timing diagram of the first stage’s mode and the sampling instance

after the change (see the dotted rectangle and compare the difference between Figure

5.21 and Figure 5.26). Now, the input has more time to settle, and the kickback noise

is removed from the spectrum of the sampled input (see Figure 5.27).

N N N N N N N N N C N

CK11

CK21

Mode1

Stage_sel[1]

Sampling Instance

Figure 5.26: Timing diagram for the first stage after the modification.


Figure 5.27: Simulated spectrum of the sampled input after the modification (fs = 50

MHz and fin = 1 MHz). Kickback noise component is removed.

5.5 Summary

This chapter presented the test setup and measurement results for a 12-bit 30-

MS/s prototype ADC. The linearity performance shows that the ADC exhibits 12-bit

accuracy even with the small DC loop gains of the proposed amplifiers. The ADC

consumes 2.63 mW, excluding the (off-chip) reference and I/O. The estimated power

of the off-chip time alignment and digital calibration logic is 0.32 mW, yielding a total

power of 2.95 mW. Together with the SNDR measured at fin = 14.8 MHz, this yields a

Walden FOM of 72 fJ/conversion-step, which compares favorably to most designs

with similar specifications. Table 5.3 summarizes the overall performance of the

prototype ADC.


Table 5.3: Performance summary.

Parameter Value

Process 90 nm CMOS

Active area 0. 36 mm2

Full input range 1.8 Vp-p-differential

VDD 1.2 V

Resolution 12 bits

Sampling rate 30 MS/s

Sampling capacitor (Cs)

in the first stage 1 pF

fin = 1 MHz fin = 14.8 MHz

Peak SNDR 65.2 dB 64.5 dB

ENOB 10.5 bits 10.4 bits

FOM [ P/(fs×2ENOB) ] (1) 66 fJ/conv.-step 72 fJ/conv.-step

DNL +0.82/-0.66 LSB

INL +1.25/-1.54 LSB

Measured ADC power (2)

2.63 mW

Estimated digital

post-processing power 0.32 mW

Total power (2)

2.95 mW

(1) Calculated using the total power (2.95 mW)

(2) Excluding reference and I/O


93

Chapter 6

Conclusion

6.1 Summary

This research proposed a low energy pipelined ADC design utilizing efficient

single-stage class-AB residue amplifiers with dynamic power cycling. Nonlinear

errors arising from finite gain of the amplifiers are addressed using the proposed

digital calibration scheme. This combination improves the efficacy of class-AB

amplification.

Chapter 2 has presented the design of the proposed class-AB amplifier, which is

based on a pseudo-differential, single-stage, cascode-free and CMFB-free architecture.

This amplifier exhibits fast turn-on and turn-off times, making it possible to

dynamically switch off the amplifier to save power when the amplifier is not in use.

As a result, the proposed amplifier dynamically adjusts the supply current and delivers

most of the supplied charge to the load. However, the cost of this efficient amplifier

architecture is a significantly degraded DC gain that results in nonlinear errors. This

problem is addressed using a digital background calibration explained in Chapter 3.

The proposed calibration scheme features deterministic background calibration (that

measures the circuit imperfections in time intervals between normal conversion cycles)

and spline-based correction (where the amplifier’s input and output transfer function is

piecewise modeled by a few low-degree polynomial functions, called splines). As a

result, the calibration algorithm runs continuously in the background, tracks the

94 Chapter 6: Conclusion

calibration parameters rapidly (the convergence time is 0.73 ms for the experimental

12-bit 30-MS/s ADC), and handles nonlinear gain errors.

As a proof of concept, a 12-bit 30-MS/s experimental ADC is fabricated in a 90-

nm CMOS technology as described in Chapter 4. As shown from the measurement

results presented in Chapter 5, this ADC exhibits 12-bit linearity performance and

achieves a Walden FOM [48] of 72 fJ/conversion-step, which is among the best

designs with similar SNDR published to date. Our results show that the proposed

class-AB circuit is indeed efficient and it is a viable alternative to the relatively

inefficient, conventional class-A residue amplifiers.

6.2 Future Work

Due to the dynamic consumption of the supply current, the proposed amplifier has

proven highly efficient. However, further optimization is possible to push the

efficiency to the limit. Since the amplifier never slews, one possible extension is to

employ incomplete settling [3]. This will let the amplifier’s output settle only for a

small number of time constants when the supply power is used more efficiently.

However, the proposed amplifier’s settling characteristic is not strictly exponential

especially for the first few time constants due to rapidly changing supply current. As a

result, incomplete settling may introduce more distortion in the amplifier’s transfer

function. So, it will be interesting to see how much more distortion is introduced as the

number of settling time constants decreases. Also, a careful analysis on the effect of

jitter must be carried out as suggested in [3].

Other opportunities exist in trying to push the architecture to higher resolution and

speed. In order to achieve higher resolution, the amplifier may need to be more robust

to supply noise. This can be accomplished by increasing the gate lengths of the

amplifying transistors, thereby increasing the DC gain of the overall amplifier. Also,

the spline-based calibration can be extended to model the amplifier characteristic

using a larger number of splines. This will reduce the interpolation error between the

model and the actual amplifier.

Chapter 6: Conclusion 95

For higher speed, the frontend input sampling network must be redesigned so that

an input driver can interface to the ADC without degrading its performance. Also,

generating the reference internally may help, since dealing with bond-wire inductance

presents a challenge for high speed converters.

The deterministic background calibration scheme presented in this work can be

optimized for even faster tracking. Since the backend stages are not critical in terms of

the overall ADC performance, 32 times averaging may not be necessary for those

stages. It is also possible to calibrate the backend stages less frequently than the

frontend stages. These improvements, combined with higher converter speed, may

lead to a convergence time much faster than that in the prototype ADC presented in

this work.

96 Chapter 6: Conclusion

97

Appendix A

Digital Logic Power Estimation

This appendix discusses how we estimated the power of the off-chip time

alignment and digital calibration logic (see Figure 4.1).

A.1 Time Alignment

Figure A.1 shows the block diagram of the time alignment logic. Note that D1 is

shifted with a D-type flip-flop (DFF) using CK12 OR CK22 clock, so that it is time

aligned with D2 (the operator OR indicates that they are combined using an OR gate;

see Figure 3.12 for more information on CK12 and CK22). Similarly, D1 - D14 are time

aligned with D15 using a total of 210 DFFs [2⋅(1 + 2 + … + 14)]. A factor of two is

multiplied into this calculation, since D1 - D14 are 2 bits each.

A.2 Post-Processing

As mentioned in Section 3.4.6, the correction block requires four additions, four

multiplications and two multiplexing operations. In order to break it down in terms of

full adders (FAs) and multiplexers (MUXs), we first need to know how many bits are

required to represent each parameter (DBE, DX, h1, h2, c1, c3, x0 and y0).

Figure A.2 shows a simplified correction block diagram of stage 1 with the bit

width indicated in each path. Note that all parameters except c3 (DBE, DX, h1, h2, c1, x0

and y0) are 14 bits because the effective number of bits of the backend ADC is 13.02

98 Appendix A: Digital Logic Power Estimation

bits [log2(1.813

) + 2] assuming the stage gain of 1.8. This number rounds up to 14 bits

(the smaller integer which is larger than 13.02). The parameter c3 is chosen to be seven

bits, because we assumed that the maximum magnitude of the third order term [the

term c3⋅(DBE-y0)3] in the nonlinearity correction polynomial function doesn’t exceed

255 (the maximum number that can be represented using seven bits). This assumption

stems from the measurement results showing that the experimental ADC is linear to

about eight bits without calibration (see Figure 5.5 and Figure 5.6). So, we assumed

that the maximum magnitude of the third order term doesn’t exceed 31 (four bits) in

DO and 255 (seven bits) in DX.

…Stage 1 Stage 2 Stage 3Backend

ADCVI

D1 D2 D3 D15

CK11 CK21 CK12 CK22

CK12 OR CK22

CK13 OR CK23

CK14 OR CK24

CK13 CK23

Stage 14

D14

… … …

CK115 OR CK215

CK114 CK214 CK115 CK215

…

…

D1,aligned D2,aligned D3,aligned D15,alignedD14,aligned

2b 2b 2b 2b 2b

Figure A.1: Time alignment block diagram.

+

-h1, 0 or h2

DX = x0 + c1 ⋅ (DBE - y0) + c3 ⋅ (DBE - y0) 3

c1, x0, y0

DO

DXDBE

Nonlinearity Correction:

14b

12b 14b

7b

c3

14b

14b

Figure A.2: Simplified correction block diagram of the first stage.

Appendix A: Digital Logic Power Estimation 99

Based on the above number of bits for parameters, we can calculate how many

full adders (FAs) and multiplexers (MUXs) are required in the post-processing block

of Figure 3.16 (for stage 1). The four 14-bit additions can translate to 56 (14⋅4) FAs.

The one 14-bit and three 7-bit multiplications can translate to 182 (14⋅13) and 126

(3⋅7⋅6) FAs, respectively. These numbers can be reduced to 146 (6 + 7 + … + 14 + 14

+ 14 + 14 + 14) and 108 [3⋅(4 + 5 + 6 + 7 + 7 + 7)], after neglecting some of the least

significant additions (shown within the dotted square in Figure A.3 for the

multiplication of two 7-bit numbers). This reduction is possible since we only take the

seven most significant bits at the output. The MUX1 and MUX2 blocks in Figure 3.16

require 14 and 49 (14⋅3+7) MUXs, respectively.

1 0 0 1 0 1 0

x

+

1 1 1 1 1 1 1

x x x x x x x x x x x x x x

Seven least significant bits will be truncated at the output

1 0 0 1 0 1 01 0 0 1 0 1 0

1 0 0 1 0 1 01 0 0 1 0 1 0

1 0 0 1 0 1 01 0 0 1 0 1 0

1 0 0 1 0 1 0Not significant

Figure A.3: Multiplication of two 7-bit numbers.

Similarly, the correction blocks for stage 2-14 can be also broken down to full

adders and multiplexers. The power of the Estimation block is negligible, because the

calibration parameters are estimated and updated once every 22,000 samples (see

Section 3.4.8).

A.3 Power Estimation

In order to estimate the power of the digital logic, we now need to know the

average power consumption of a D-type flip-flop (DFF), a full adder (FA) and a

multiplexer (MUX). Table A.1 shows the average energy required to switch the output

100 Appendix A: Digital Logic Power Estimation

(VDD of 1.2V) of minimum sized DFF, FA and MUX cells in a UMC 90-nm CMOS

technology. Assuming an activity factor [53] of 0.5, the estimated power of the off-

chip time alignment and digital calibration logic at the clock frequency of 9/8 times 30

MHz (see Section 3.4.6) is 317 uW (see Table A.2 for the power breakdown). Using

VDD of 1V for comparison, the total power is reduced to 220 µW.

Table A.1: Average energy required when the output switches (VDD of 1.2V).

Cell Average energy (uW/MHz)

DFF 0.0155

FA 0.006

MUX (3 inputs) 0.006

Table A.2: Estimated digital post-processing power breakdown.

Function Required Hardware Estimated power

Time alignment 210 DFFs 21 µW

Post-processing

Stage 1 310 FAs, 63 MUXs 87 µW




Stage 5-14 62 FAs, 62 MUXs 22 µW

Total 210 DFFs, 1024 FAs,

284 MUXs 317 µW

101

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