Pipelining

Presented byAjal.A.J

AP/ ECE

Pipelining

Without pipelining

Pipelined Data path

• Interstage buffer B1 feeds the Decode stage with a newly-fetched instruction.

• Interstage buffer B2 feeds the Compute stage with the two operands

• Interstage buffer B3 holds the result of the ALU operation

• Interstage buffer B4 feeds the Write stage with a value to be written into the register file

Performance Evaluation

• where S is the average number of clock cycles it takes to fetch and execute one instruction,

and R is the clock rate in cycles per second and N Is the dynamic instruction count

Instruction throughput

• Non pipelined

• pipelined

Pipelining Issues

Pipelining Issues/Hazards in pipelining

• Any condition that causes the pipeline to stall is called a hazard

1.Data Hazard/Data Dependencies

• Ij and Ij+1, where the destination register for instruction Ij is a source register for instruction Ij+1

• The result of instruction Ij is not written into the register file until cycle 5, but it is needed earlier in cycle 3 when the source operand is read for instruction Ij+1

Data Dependencies

1.1Overcoming data dependencies

• Operand Forwarding

1.2 Handling Data Dependencies in Software

2. Memory Delays

• Cache miss

• compiler can eliminate the one-cycle stall for this type of data dependency by reordering instructions to insert a useful instruction between

• If a useful instruction cannot be found by thecompiler, then the hardware introduces the one-

cycle stall• If the processor hardware does not deal with

dependencies, then the compiler must insert an explicit NOP instruction automatically

3. Branch Delays

• Branch instructions can alter the sequence of execution

• Unconditional Branches• Conditional branchingbranch condition must be tested as early as

possible to limit the branch penalty

The Branch Delay Slot

Branch Prediction

• Still one instruction is fetched

Static Branch Prediction

• assume that the branch will not be taken/Taken

Dynamic Branch Prediction

• use actual branch behavior to influence the prediction

• LT - Branch is likely to be taken• LNT - Branch is likely not to be taken

• ST - Strongly likely to be taken• LT - Likely to be taken• LNT - Likely not to be taken• SNT - Strongly likely not to be taken

3.Resource Limitations

• If two instructions need to access the same resource in the same clock cycle, one instruction must be stalled to allow the other instruction to use the resource. This can be prevented by providing additional hardware.

5.Number of Pipeline Stages

• more potential dependencies between instructions that may lead to pipeline stalls

Superscalar Operation

• Add R2, R3, #100• Load R5, 16(R6)• Subtract R7, R8, R9• Store R10, 24(R11)

• Branches and Data Dependencies• Out-of-Order Execution• Execution Completion• Dispatch Operation

AMIHL'S LAW

Flynn’s classification

Multicomputer /Multiprocessors

Shared memory

Message-Passing Multicomputers• Each node in the system as a complete computer

with its own memory• Other computers in the system do not havedirect access to this memory• Data that need to be shared are exchanged by

sending messages from one computer to another• Parallel programs are written differently for

message-passing multicomputers than for shared-memory multiprocessors

Message passing

Multiprocessorsystems-Interconnection networks

Hardware Multithreading

• Thread-which is an independent path of execution within a program

• it is possible for multiple threads to execute portions of one program and run in parallel as if they correspond to separate programs

• Threads for different programs can also execute on different processors

• Two or more threads can be running on different processors

• coarse-grained• Instead of stalling while the slower main memory

is accessed to service the cache miss, a processor can quickly switch to a different thread and continue to fetch and execute other instructions

• fine-grained or interleaved multithreading• An alternative to switching between threads on

specific events is to switch after every instruction is fetched. This is called fine-grained or interleaved multithreading