37
PISCES: A P4-Enabled OVS Muhammad Shahbaz, Cian Ferriter Princeton, Intel P4
PISCES: A P4-Enabled OVSMuhammad Shahbaz, Cian Ferriter
Princeton, Intel
P4
PISCES: A P4-Enabled OVS
PISCESvSwitch
P4
OVS
Fast Packet IO (or Forwarding)KernelDPDK
Internal Architecture of OVS
OVS
Internal Architecture of OVS
OVS
Packet Processing Logic
Kernel
Parser Match-Action PipelineComplex APIs
DPDK
Kernel
Parser Match-Action Pipeline
DPDK
OVS
Internal Architecture of OVS
Kernel
Parser Match-Action Pipeline
DPDK
OVS
Internal Architecture of OVS
Internal Architecture of OVS
Kernel
Parser Match-Action Pipeline
DPDK
OVS
Road to Protocol Independence
Kernel
Parser Match-Action Pipeline
DPDK
OVS
Domain-Specific Language
Parser Match-Action Pipeline
Compile
Road to Protocol Independence
Kernel
Parser Match-Action Pipeline
DPDK
OVS
Parser Match-Action Pipeline
Compile
P4 is an open-source language.[1]
Describes different aspects of a packet processor:- Packet headers and fields- Metadata- Parser - Actions- Match-Action Tables (MATs)- Control Flow
P4[1]
[1] http://www.p4.org
Road to Protocol Independence
Kernel
Parser Match-Action Pipeline
DPDK
OVS
P4[1]
Parser Match-Action Pipeline
[1] http://www.p4.org
Native OVS
341 lines of code
14,535 lines of code
Compile
Road to Protocol Independence
KernelDPDK
OVS
P4[1]
[1] http://www.p4.org
OVS Forwarding Model
Compile
P4 Forwarding Model
Performance Overhead!
P4 Forwarding Model
PacketParser Match-Action
Tables
PacketDeparser
Ingress Egress
HeaderFields
(Post-Pipeline Editing)
ChecksumVerify
ChecksumUpdate
OVS Forwarding Model
PacketParser
Ingress Match-ActionCache
Egress
Miss
Match-ActionTables
Flow Rule
Slow-path
Fast-path
OVS Forwarding Model
PacketParser
Ingress Match-ActionCache
EgressMatch-ActionTables
Hit
Egress
Slow-path
Fast-path
OVS Forwarding Model
PacketParser
Ingress Match-ActionCache
EgressMatch-ActionTables
Egress
(Inline Editing)
Slow-path
Fast-path
PISCES Forwarding Model (Modified OVS)
PacketParser
Ingress Match-ActionCache
Match-ActionTables
PacketDeparser
Egress
• Supports both editing modes:- Inline Editing- Post-pipeline Editing
ChecksumVerify
ChecksumUpdate
Slow-path
Fast-path
PISCES: Compiling P4 to OVS
Packet
Parser Match-Action
Tables
Packet
Deparser
Ingress Egress
Packet
Parser
Ingress Match-Action
Cache
Match-Action
Tables
Egress
P4
modified
OVS
Checksum
Verify
Checksum
Update
Checksum
VerifyChecksum
UpdatePacket
Depraser
PISCES Forwarding Model (Modified OVS)
PacketParser
Ingress PacketDeparser
EgressChecksum
VerifyChecksum
Update
Match-ActionTables
Match-ActionCache
Slow-path
Fast-path
PISCES Forwarding Model (Modified OVS)
PacketParser
Ingress
Megaflow Cache
PacketDeparser
EgressChecksum
VerifyChecksum
UpdateMicroflow Cache
Match-ActionTables
Slow-path
Fast-path
PISCES Forwarding Model (Modified OVS)
PacketParser
Ingress
Megaflow Cache
PacketDeparser
EgressChecksum
VerifyChecksum
Update
Match-ActionTables
Slow-path
Fast-path
Naïve Compilation from P4 to OVS (L2L3-ACL)
0
10
20
30
40
50
64 128 192 256
Thro
ugh
pu
t (G
bp
s)
Packet Size (Bytes)
Naïve OVS Performance overhead of
~ 40%
Causes of Performance Overhead
Packet
Parser
IngressMegaflow Cache
Match-Action
Tables
Packet
Deparser
EgressChecksum
VerifyChecksum
Update
CPU Cycles per Packet
Cache Misses
Cause: CPU Cycles per Packet
76.5
209.5
379.5
43.6
197.5
132.5
0
100
200
300
400
Parser Cache: Match Cache: Actions
L2L3-ACL (CPU Cycles for a 64 Byte Packet)
Naïve OVS
7.6
13.5
0
5
10
15
Throughput (Gbps)
Factors affecting CPU Cycles per Packet
a. Extra copy of headers
b. Fully-specified Checksum
c. Parsing unused header fields
and more …
76.5
209.5
379.5
29.3
130.8
43.6
197.5
132.5
0
100
200
300
400
Parser Cache: Match Cache: Actions
L2L3-ACL (CPU Cycles for a 64 Byte Packet)
Naïve Inline Inc. Chksm Parsr Spcl Act Spcl Act Coalcng OVS
7.6
13.3 13.5
0
5
10
15
Throughput (Gbps)
Different Optimizations for L2L3-ACL
0
10
20
30
40
50
64 128 192 256
Thro
ugh
pu
t (G
bp
s)
Packet Size (Bytes)
Naïve Optimized OVS
Optimized Compilation from P4 to OVS (L2L3-ACL)
Performance overhead of
< 2%
Cause: Cache Misses
PacketParser
Ingress Match-ActionCache
Match-ActionTables
PacketDeparser
EgressChecksum
VerifyChecksum
Update
Cache Misses
• 3500+ Cycles (50x Cache hit) • Throughput < 1 Mpps
Factors affecting Cache Misses
a. Entropy of packet header fields
b. Stateful operations in the match-action cache (or fast path).
PISCES Forwarding Model (Modified OVS)
PacketParser
Ingress
Megaflow Cache
PacketDeparser
EgressChecksum
VerifyChecksum
UpdateMicroflow Cache
Match-ActionTables
Slow-path
Fast-path
PISCES Forwarding Model (Modified OVS)
Microflow Cache
Internals of the Microflow Cache
Packet in Extract
FieldsHash Fields
P4 File
PacketoutPerform
Lookup
Miss
Hit
Microflow Cache
to MegaflowCache
7.7286.464
Thro
ugh
pu
t (G
bp
s)
Phy-Phy, L3 Router Case, 64B
OVS PISCES
Performance with the Microflow Cache
Cause of Performance Degradation
Cacheline 64 Bytes
0 Metadata
1 MetadataEthernet Header
2 IPv4 (1st 16Bytes) IPv4 + L4 Proto Empty
Simplified “flow” Structure
7.728 8.198Th
rou
ghp
ut (
Gb
ps)
Phy-Phy, L3 Router Case, 64B
OVS PISCES
Performance with the Microflow Cache
Varying the Number of Hash Fields
8.682
8.198T
hro
ugh
pu
t (G
bp
s)
L2 Address (2 Fields) Five Tuple (5 Fields)
Questions?
Disclaimers
Intel does not control or audit third-party benchmark data or the web sites referenced in this document. You should visit the referenced web site and confirm whether referenced data are accurate.
Intel technologies’ features and benefits depend on system configuration and may require enabled hardware, software or service activation. Performance varies depending on system configuration. No computer system can be absolutely secure. Check with your system manufacturer or retailer or learn more at [intel.com].
