PLD Technology Basics

Basic PAL Architecture

D Q

Q

CLK OEFuse

The type of the configuration cell (Memory) defines the technology• Bipolar

– metallic fuse, destroyed by prog., One-Time-Programmable (OTP)• UV erasable (EPROM)

– expensive window package or Plastic OTP, slow erase time• Electrical erasable (EEPROM)

– multiple read/write cycles, In-System programmable,fast prog and erase, non-volatile

• CMOS-Memory Cell– volatile, information lost after power-down, reconfigurable, very fast

prog. Time, Configuration PROM needed• Antifuse, Vialink

– open fuse element, programming forms an electrical connection, OTP, long prog times, low impedance interconnect

Technology

PAL Architecture

Pro

gram

mab

le A

ND

Arr

ay

OR

Gat

es

OutputMacrocells

DedicatedInputs

Clock/Input

I/Os

PAL SPLDs use a programmable AND array andfixed OR array to create several outputs in asum-of-products form. SPLDs are commonlyreferred to as PALs.

D Q

Q

From OR Gate

To AND Array

Clock

I/O

These outputs can be eithercombinatorial or registered in themacrocell.

CPLD Architecture (1)

The CPLD is an array of PAL-like devices, interconnected by a switch matrix.

Ce

ntr

al

Sw

itc

h M

atr

ix PAL Block

PAL Block

Dedicatedinputs

Clock/Inputs

PAL Block

PAL Block

I/Os

I/Os I/Os

I/Os

CPLD Architecture (2)Clock/Input

Clock Generator

Logi

c A

rray

& A

lloca

tor

OutputMacrocell

Out

pu

t S

witc

hM

atr

ix I/OCells

I/O

Input Switch Matrix

Cen

tral

Sw

itch

Mat

rix The CPLD architecture is morecomplex than the typical PAL inorder to fully utilize the increasedlogic capacity and additionalrouting matrices of the device.

FromClock

Generator

From LogicAllocator

To Output/InputSwitch MatrixD Q

Product Term Enable

To Input SwitchMatrix

From Output SwitchMatrix

From ClockGenerator

I/O

DQ

The CPLD macrocell, although relatively similar to thePAL macrocell, has greater flexibility in routing its

output to both the I/O Cells and Central Switch Matrix.The I/O Cell controls the flow of inputand output to and from the device.

MACH 4A Device ArchitectureClock

Generator

Logic Arrayand

Allocator

Output/Buried

Macrocells

OutputSwitchMatrix

I/O Cells

InputSwitchMatrix

PAL Block

PAL Block

Cen

tral

Sw

itch

Mat

rix

PAL Block

Clock/Input Pins

DedicatedInput Pins

I/O Pins

I/O Pins

Macrocell Feedback

I/O Pin Feedback (registered and non-registered)

FPGA ArchitectureConfigurable Logic

Block (CLB)

ProgrammableInterconnect

Routing

I/O Block

FPGAs utilize a channeled routing structure to connect blocks of configurable logic

Applications

RegisterIntensiveFunctions

Combinatorial Functions

Datapath Functions• Register Intensive• Narrow Gating• Pipelined Systems• Dense, Flexible• Low Power• Lower Speed than CPLDs

Control Functions• High Speed• Wide Gating• State Machines• Address Decoding

Variable Grain Architecture Variable Grain ArchitectureFPGA

CPLD

Measurement of Size and Density• SPLD

– Measured by number of input/outputs (22V10)

• ASIC– Available gates measured in 2-input equivalents– Usable gates typically 40 to 60 %

• CPLD– Measured by macrocells (32 -1024)– Typical gate count ranges 1k to 40k

• FPGA– Measured by gate count (1k to 100k)– Usable gates typically 50 to 60 %

Attention!

The Art of Gate Counting

In-System Programming Eases Prototyping

• Easy development• Connect cable to PC, programmer or JTAG tester

• Download software performs the following:• Bulk Erases the device (EE only)

• Serializes the JEDEC (fusemap) file

• “Bypasses” devices not being programmed

• Shifts the JEDEC data into the device

• Programs the JEDEC data into the configuration cells

JTAG-Testing

TCKTMS

TDITDO

CoreLogic

Boundary Scan Control Circuit

TDI

Boundary-Scan Cell (BSC)

TDO

CoreLogic

Boundary Scan Control Circuit

TMSTCK TCK

TMS

TDO

JTAG-Interface