File Name: H:\pluto5\manuals\pluto_5_controller.doc HEBER LTDDocument No. 80-15151 Issue 6
User ManualPluto 5 ControllerDocument No. 80-15151 Issue 6 HEBER LTD
Current Issue :- Issue 6 – 2nd September 2005
Previous Issue :- Issue 5r1 – 14th May 2004
©HEBER Ltd. 2005. This document and the information contained therein is the intellectual property ofHEBER Ltd and must not be disclosed to a third party without consent. Copies may be made only ifthey are in full and unmodified.
File Name: H:\pluto5\manuals\pluto_5_controller.doc HEBER LTDDocument No. 80-15151 Issue 6
HEBER LTDBelvedere Mill
ChalfordStroud
GloucestershireGL6 8NTEngland
Tel: +44 (0) 1453 886000Fax: +44 (0) 1453 885013
Email: [email protected]://www.heber.co.uk
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Document No. 80-15151 Issue 6 HEBER LTD
CONTENTS
1 INTRODUCTION.................................................................................................................... 1
2 NEW IN THIS RELEASE ....................................................................................................... 1
3 OVERVIEW............................................................................................................................ 1
4 CIRCUIT SCHEMATIC DESCRIPTION ................................................................................ 2
4.1 SHEET 1 .................................................................................................................................. 24.2 SHEET 2 .................................................................................................................................. 24.3 SHEET 3 .................................................................................................................................. 24.4 SHEET 4 .................................................................................................................................. 24.5 SHEET 5 .................................................................................................................................. 24.6 SHEET 6 .................................................................................................................................. 24.7 SHEET 7 .................................................................................................................................. 24.8 SHEET 8 .................................................................................................................................. 34.9 SHEET 9 .................................................................................................................................. 34.10 SHEET 10 ................................................................................................................................ 34.11 SHEETS 11, 12 & 13 ................................................................................................................ 3
5 CIRCUIT OPERATION .......................................................................................................... 4
5.1 POWER SUPPLIES..................................................................................................................... 45.2 RESET AND POWER FAIL DETECTION......................................................................................... 45.3 BATTERY BACKUP .................................................................................................................... 55.4 THE MC68340 PROCESSOR..................................................................................................... 5
5.4.1 CPU32 Processor Module ................................................................................................. 65.4.2 SIM40 System Integration Module..................................................................................... 65.4.3 DMA Controller Module ..................................................................................................... 85.4.4 Serial Module ..................................................................................................................... 85.4.5 Timer Module ..................................................................................................................... 9
5.5 FPGA.................................................................................................................................... 105.6 EPROM SOCKETS / EPROM AUTOSELECT FEATURE ............................................................. 105.7 EPROM ADDRESS LINE SCRAMBLING IN 16 BIT MODE............................................................ 11
5.7.1 2*27C040 EPROMs......................................................................................................... 115.7.2 2*27C801 EPROMs......................................................................................................... 11
5.8 MEMORY EXPANSION.............................................................................................................. 135.9 OPEN DRAIN OUTPUTS, OP0-63............................................................................................. 135.10 AUX OUTPUTS, AUX0-7........................................................................................................ 145.11 INPUTS, IP0-31 ...................................................................................................................... 145.12 DIL SWITCHES ....................................................................................................................... 155.13 SOFTWARE CONTROLLED INDICATOR LED............................................................................... 155.14 ON-BOARD PUSH BUTTON ...................................................................................................... 155.15 MULTIPLEXER......................................................................................................................... 155.16 MULTIPLEXED LAMP CURRENT SENSE ..................................................................................... 175.17 SOUND GENERATION.............................................................................................................. 185.18 STEREO AMPLIFIER AND VOLUME CONTROLS........................................................................... 185.19 SERIAL I/O ............................................................................................................................. 195.20 INTERNAL I2C BUS.................................................................................................................. 19
5.20.1 Real Time Clock............................................................................................................... 195.20.2 E2PROM........................................................................................................................... 19
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6 MACHINE OPERATION ...................................................................................................... 20
6.1 DRIVING REELS ...................................................................................................................... 206.2 READING THE DIL SWITCHES.................................................................................................. 206.3 READING THE SWITCH INPUTS................................................................................................. 206.4 INTERFACING TO COIN & NOTE ACCEPTORS ............................................................................ 216.5 INTERFACING TO COIN PAYOUT MECHANISMS.......................................................................... 216.6 DRIVING VACUUM FLUORESCENT DISPLAYS (VFD) .................................................................. 216.7 USING THE EXTERNAL I2C BUS ............................................................................................... 216.8 DRIVING METERS ................................................................................................................... 216.9 MAKING SOUNDS.................................................................................................................... 21
6.9.1 Single Channel/Single Speaker (Mono) Mode ................................................................ 226.9.2 Dual Channel/Dual Speaker (Stereo) Mode .................................................................... 226.9.3 Known DMA Problems..................................................................................................... 22
6.10 USING MULTIPLEXED LAMPS ................................................................................................... 226.11 USING MULTIPLEXED LEDS .................................................................................................... 226.12 USING THE MULTIPLEX EXPANSION CONNECTOR ..................................................................... 236.13 ADDING VIDEO CAPABILITIES................................................................................................... 23
7 SOFTWARE DEVELOPMENT ............................................................................................ 24
8 CONNECTOR TYPES AND PIN OUTS .............................................................................. 25
8.1 SCHEDULE OF CONNECTOR TYPES.......................................................................................... 258.2 P1 – RS232 CHANNEL A ....................................................................................................... 268.3 P2 – DATAPORT (RS232 CHANNEL B).................................................................................... 278.4 P3 – POWER INPUT................................................................................................................ 278.5 P4 – MULTIPLEXED LAMP SINKS ............................................................................................. 288.6 P5 ULTREX – MULTIPLEXED LEDS.......................................................................................... 288.7 P5 BOX HEADER – MULTIPLEXED LEDS.................................................................................. 298.8 P6 – MULTIPLEXED LAMPS SOURCES...................................................................................... 298.9 P7 ULTREX – REELS .............................................................................................................. 308.10 P7 BOX HEADER – REELS ...................................................................................................... 318.11 P8 ULTREX – GENERAL I/O #1 ............................................................................................... 328.12 P8 BOX HEADER – GENERAL I/O #1 ....................................................................................... 338.13 P9 ULTREX – GENERAL I/O #2 ............................................................................................... 348.14 P9 BOX HEADER – GENERAL I/O #2 ....................................................................................... 348.15 P10 – LOUDSPEAKERS........................................................................................................... 358.16 P11 – MULTIPLEX EXPANSION ................................................................................................ 358.17 P12 – AUX OUTPUTS ............................................................................................................. 358.18 P13 – EXTERNAL I2C BUS ...................................................................................................... 368.19 P14 – IO EXPANSION CARD CONNECTOR ............................................................................... 368.20 P15 – MEMORY EXPANSION CARD CONNECTOR...................................................................... 378.21 P16 – BACKGROUND DEBUG MODE CONNECTOR.................................................................... 37
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LIST OF TABLESTable 1. Allocation of MC68340 Pins Controlled by SIM40 Module........................................................ 7Table 2. Allocation of MC68340 Pins Controlled by DMA Module .......................................................... 8Table 3. Allocation of MC68340 Pins Controlled by Serial Module......................................................... 9Table 4. Allocation of MC68340 Pins Controlled by Timer Module......................................................... 9Table 5. Possible EPROM Configurations ............................................................................................ 10Table 6. Re-Mapping of Address Lines in 2*27C040 Mode .................................................................. 11Table 7. Re-Mapping of EPROM Contents in 2*27C040 Mode ............................................................ 11Table 8. Re-Mapping of Address Lines in 2*27C801 Mode .................................................................. 11Table 9. Re-Mapping of EPROM Contents in 2*27C801 Mode ............................................................ 12Table 10. Mapping of Open Drain Outputs (OP0-63) to TPIC6259 Devices ........................................ 13Table 11. Mapping of Inputs IP0-31 ...................................................................................................... 14Table 12. Mapping of DIL Switch Inputs................................................................................................ 15Table 13. I2C Slave Addresses for RTC, U40 ....................................................................................... 19Table 14. I2C Slave Addresses for E2PROM, U37 ................................................................................ 19Table 15. Recommended Reel Stepper Motor Drive Connections ....................................................... 20Table 16. AMP Ultrex Connector Part Numbers ................................................................................... 25Table 17. Tyco Box Header Connector Part Numbers.......................................................................... 25Table 18. AMP MTA-100 Connector Part Numbers.............................................................................. 26Table 19. AMP MTA-156 Connector Part Numbers.............................................................................. 26
LIST OF FIGURESFigure 1 - Schematic Sheet 1 - Root Sheet........................................................................................... 38Figure 2 - Schematic Sheet 2 - CPU ..................................................................................................... 39Figure 3 - Schematic Sheet 3 - FPGA................................................................................................... 40Figure 4 - Schematic Sheet 4 - Memory................................................................................................ 41Figure 5 - Schematic Sheet 5 - Sound .................................................................................................. 42Figure 6 - Schematic Sheet 6 - Outputs ................................................................................................ 43Figure 7 - Schematic Sheet 7 - Inputs................................................................................................... 44Figure 8 - Schematic Sheet 8 - Power Supply ...................................................................................... 45Figure 9 - Schematic Sheet 9 – IO Connectors..................................................................................... 46Figure 10 - Schematic Sheet 10 - Reset/Battery/RS232....................................................................... 47Figure 11 - Schematic Sheet 11 - Lamp Column/LED Digit Drives....................................................... 48Figure 12 - Schematic Sheet 12 - Lamp Row Drives ............................................................................ 49Figure 13 - Schematic Sheet 13 - LED Segment Drives....................................................................... 50Figure 14 - Pluto 5 Component Ident .................................................................................................... 51Figure 15 - Photograph of Pluto 5 with Ultrex Connectors (Pluto 5U)................................................... 52
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1 INTRODUCTION
The Pluto 5 Controller board is a natural progression in the Pluto family of products. It builds on theproven reliability and technical excellence of previous Pluto boards and provides improvedperformance and flexibility at lower cost. This manual covers the detail of the hardware operation ofPluto 5 Controller board, other boards in the system have their own manuals.
2 NEW IN THIS RELEASE
• Section 6.9 has revised audio information.
3 OVERVIEW
The Pluto 5 Controller board is a low cost, high performance single board controller for amusementmachines. An 8 reel machine with 256 lamps, 32 LED digits, Linewriter display, Coin Acceptors, NoteAcceptors and Payout Hoppers can be controlled without any additional boards.
Single channel sound can be played through one or two speakers. Two Channel (mono or stereo)sound is available by plugging in an additional IC.
Pluto 5 boards are supplied with either Ultrex or Box Header connectors.Pluto 5 with Ultrex connectors is referred to as Pluto 5U.Pluto 5 with Box Header connectors is referred to as Pluto 5B.These connectors and all the other connectors on the Pluto 5 board are documented in Section8 - Connector Types and Pin Outs in this user manual.
Add-on boards are available to increase the number of lamps by up to 512, LED Digits by up to 64 aswell as CGA/VGA Video and Memory Expansion.
The numbering system on all Pluto 5 boards is consistent, in that, where Lamps and LEDs areinvolved the product name has a suffix X/Y. X is the number of lamps and Y is the number of LEDdigits that that product drives. The Pluto 5 Controller board is available as a Pluto 5 128/16Controller and a Pluto 5 256/32 Controller.
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4 CIRCUIT SCHEMATIC DESCRIPTION
This section is a walk through of the Pluto 5 Controller board (56-14084) circuit schematics, Figures1-13 of this document. A detailed description is given in Section 5 “CIRCUIT OPERATION”.
4.1 Sheet 1
This sheet shows the interconnection between the remaining sheets of this drawing.
4.2 Sheet 2
This sheet shows the following items:
• Motorola MC68340 Processor.• Pull-up resistors on Address Bus, Data Bus and other Control Signals.• Push Button Switch, SW3.• P16 “BACKGROUND DEBUG MODE” connector.
4.3 Sheet 3
This sheet shows the FPGA.
4.4 Sheet 4
This sheet shows the following memory related circuits:
• Sockets for 1 or 2 EPROMs, U1 and U2• 64Kbytes Battery backed RAM, U3 and U4• P15 “MEMORY EXPANSION” connector for plug-in Memory Cards
4.5 Sheet 5
This sheet shows the following sound related circuits:
• Standard Sound Channel #1, U8 (OKI MSM6585).• Optional Sound Channel #2, U39 (OKI MSM6585).• TDA7057AQ Stereo Audio Amplifier.• P10, “LS” connector for loudspeakers.
4.6 Sheet 6
This sheet shows the 64 Open Drain Outputs, OP0-63.
4.7 Sheet 7
This sheet shows the following circuits:
• External inputs, IP0-31• Two 8 way DIL switches, SW1 and SW2
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4.8 Sheet 8
This sheet shows various Power Supply related functions:
• Current sensing +12V Meter supply• Power fail detection.• Current sensing from Lamp Multiplex.• Fuse and +5V regulator.• Voltage rail overvoltage and transient protection.• P3 “PWR IN” power input connector
4.9 Sheet 9
This sheet shows the following I/O connectors.
• P7 “REELS” carries enough I/O lines to run 6 reels, including a sub set of the lamp multiplexer andpower supplies for the motors.
• P8 “I/O 1” and P9 “I/O 2” are general purpose I/O.• P11 “MULTIPLEX EXPANSION” provides signals for the connection of Multiplex Expansion
boards.• P12 “AUX OUTPUTS” provides 6 open drain TTL outputs, typically for driving VFD displays.• P13 “I2C” provides a connector for external I2C expansion, e.g. E2PROM modules. Note that the
lines used to implement this connector are different to the lines allocated for the internal I2C bus toU40 and U37.
• P14 “I/O EXPANSION” is a position for a daughter board for I/O expansion.
4.10 Sheet 10
This sheet shows the following circuits and connectors:
• Reset circuit and LED.• Battery Backup for RAM and optional Real Time Clock.• Optional I2C Real Time Clock socket, U40, PCF8583.• Optional I2C E2PROM socket, U37, 24C04 (512 bytes) or 24C08 (1024 bytes).• RS232 buffers.• P1 “RS232” is a general purpose RS232 serial communication port.• P2 “DATAPORT” is the BACTA standard Dataport.
4.11 Sheets 11, 12 & 13
These sheets show the Multiplex Lamp and LED drive circuits and connectors.
• Sheet 11 shows the Lamp Columns/Digits Sink drivers.• Sheet 12 shows the Lamp Row/Source drivers• Sheet 13 shows the LED Segment drivers• P4 “LAMP SINKS” is the Lamp Array Column/Sink outputs• P5 “LED” is the connector for the 32 or 16 LED digits.• P6 “LAMP SRC” is the Lamp Array Row/Source outputs
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5 CIRCUIT OPERATIONThis section describes how some elements of the circuit operate and their capabilities and limitations.A subsequent section deals with how the various capabilities of the board are used to implementspecific amusement machine functions.
5.1 Power Supplies
The Power Input to the board is on P3. There are 3 input voltages required, +12V, -12V and 36V or48V for the lamp multiplex.
The +12V supply is fused by F1 (3.15A) as it comes on the board. From the un-fused (input) side, the+12V is distributed to the Reel Connector, P7 where it may be used to provide the supply for theStepper Motors.
From the fused side, the +12V is used for the following:
• Regulated via U15 to provide the Vcc (+5V) supply for the board. This will draw up to 250mA fromthe +12V rail.
• To provide the Power Supply for the Stereo Audio Amplifier, U32. The load current drawn by thiswill depend on the audio volume, etc. but is not likely to exceed an average of about 200mA.
• Monitored by U16B to detect imminent failure of the +5V supply and cause a Level 7 (Non-Maskable) Interrupt, NMI-. The interrupt will occur if the +12V supply drops below approximately7.8V.
• To provide the Power Supply for the multiplexed LED drive circuits. With 32 LED digits fitted andall having all segments illuminated, the current drain is likely to be between 400mA and 550mA.
• Distributed to various connectors, P1, P2, P8, P9, P12 and P14 for optional use by externalcircuits.
When connecting external loads to the Fused +12V outputs on P1, P2, P8, P9, P12 and P14 makesure that the total current drawn is within the rating of fuse F1 (3.15A), making due allowances for theother loads as described above.
The –12V supply input provides the negative supply for the 1488 RS232 Transmitter Buffer, U33, andthe –12V supply required on the DATAPORT Connector, P2.
The Lamp Multiplex supply should be +36V or +48V, depending upon the duty cycle employed by thesoftware. See Section 6.10, “Using Multiplexed Lamps” for more information.
Transient suppressers (Tranzorbs) are fitted on the +12V supply (fused side), -12V supply and Vcc toprotect these lines against any overvoltage.
5.2 Reset and Power Fail Detection
TL7705 device, U17, (see Schematic Sheet 10 - Reset/Battery/RS232), provides the system reset. Atpower up, the system is held in a reset state (RESET- low, RESET high) for about 5 seconds. Thistime is determined by C14. The processor may initiate a full hardware reset at any time by assertingPort B, pin 0 (PB0) low, which will trigger the TL7705 via the RESIN- pin. The RESET lines will also beimmediately asserted by the TL7705 if the Vcc line drops below 4.75V.
While the system is in a reset state, i.e. RESET- is low, a red LED, LD1, is illuminated.
The power fail detection is a simple threshold detection on the 12V rail using one section of the quadcomparator LM339 (U16B), see Schematic Sheet 9 - IO Connectors.
When the +12V input falls below a threshold of approximately 7.8V, the output of the comparator goeslow which causes a Level 7 interrupt (NMI) to the processor. This will occur BEFORE the 7805regulator drops out of regulation and the Vcc line starts to drop, thus giving the processor a period oftime to react before the RESET is asserted by the TL7705, U17. The main purpose of giving the
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processor the NMI in advance of the RESET is to avoid the risk of an incomplete RAM write operationoccurring if the RESET were to be asynchronously asserted while such an operation was beingcarried out.
The time available between the assertion of NMI and the assertion of RESET will depend on the rateof fall of the +12V line, which will obviously be dependent upon the power supply and the loading onthe +12V, but will typically be several milliseconds.
5.3 Battery Backup
A backup battery, BT1, is provided (see - Schematic Sheet 10 - Reset/Battery/RS232) to allow the twoRAMs U3 and U4 to retain data while the board is powered down and to keep the optional Real TimeClock chip, U40, running.
BT1 is a two cell rechargeable NiMH (Nickel Metal Hydride) battery, capacity 70mA/hr. The circuitcomprising BT1, Q2, R43 and R132 provides the battery trickle charge and switchover of the securedpower supply rail, Vbatt.
While Vcc is at 5V, current flows through the base-emitter junction of Q2 through R43 into the battery.On charge, the voltage on BT1 will be about 2.6V so the current through R43 will be (5-VBE-2.6)/3300,about 0.5mA. Thus Q2 will be turned ON and Vbatt will be a VCEsat below Vcc. Current will thereforealso flow through R132 into Vbatt, (5-VCEsat-2.6)/3300, about 0.7mA. Total trickle charge current istherefore 0.5 + 0.7 = 1.2mA. The specification of the cells calls for a trickle charge of between .01Cand .03C. C is 70mA, so the acceptable range is between .7mA and 2.1mA.
When power is removed, Vcc collapses to ground. The base-emitter junction of Q2 is now reversebiased and therefore no current flows through R43 and Q2 is OFF. Vbatt is now connected to thepositive end of BT1 via R132. The discharge current into the RAMs and RTC should not exceed 40µA,which will result in a voltage drop in R132 of less than 0.15V. This gives a worst case battery life inexcess of two months, and in practice much higher.
When on battery backup it is vital that the RAMs are placed in the standby state by ensuring that theCS- line is high. Q1 and R42 achieve this. When the RESET- line goes low, which may occur either asa result of a Reset occurring or Vcc collapsing, Q1 turns OFF causing the CS- lines to the RAMs to bepulled to Vbatt by R42.
5.4 The MC68340 Processor
Full details of the operation of the processor is given in the Motorola MC68340 User Manual [seeAdobe Acrobat File 68340um.pdf, plus Addenda files 68340um_ad.pdf and 68340um_ad2.pdf]
The MC68340 contains the following functional blocks:
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5.4.1 CPU32 Processor ModuleThe CPU32 is a processing core which is basically 68000 code compatible but with a number ofenhancements. For full details of operation please refer to both the Motorola MC68340 User Manualand the Motorola M68000 Family Programmers Reference Manual [see Adobe Acrobat File68kprm.pdf].
All modern 68000 Compilers and Assemblers have various options for the target CPU. Whengenerating code for the Pluto System, the CPU32 option should be used.
If the Compiler/Assembler is old it is possible that it may not have a CPU32 option. In this case, theCompiler (if used) should be run with the 68000 option set. The assembler may be run in 68020 modewhich will allow the use of the MOVES command which is required during initialisation to set up theModule Base Address Register (MBAR) in the MC68340. Care must be taken not to write code thatcalls any other 68020 instructions that may not be implemented on the CPU32.
The Pluto 5 Development Kit includes a suitable C Compiler and Assembler.
5.4.2 SIM40 System Integration ModuleThis module controls various aspects of the operation of the processor, such as configuration, clock,external bus, etc.
When used in the Pluto System, the main considerations in the use of this module are:
5.4.2.1 Module Base Address RegisterSet the Module Base Address Register, MBAR, to a suitable address during initialisation.This sets the base address of all the internal module registers. In the example code it is setin Module “except.asm” to value 0xffff f000. There is nothing magic about this value, butobviously it must be set to an address that is clear of any other devices in the processormemory map. This register must be set before any other module initialisation is attempted.
5.4.2.2 Chip SelectsSet-up the 4 Chip Select outputs, CS0- to CS3-. The Pluto 5 System allocates these asfollows:
CS0 - is used to map the system programme memory. This consists of any EPROM fitted tothe on-board EPROM sockets, U1 and U2 plus any extra EPROM or FLASH devices fitted tothe Memory Expansion Connector, P14. Exact mapping, within the area defined by CS0-, iscarried out be the system FPGA.
CS1 - is used to map the on-board, battery backed RAM and, if fitted, any external RAM ona memory card on connector P15.
CS2 - is used to map both the internal registers of the FPGA and the on-board I/O,
CS3 - is normally spare and is available on the I/O expansion connector, P14. Its main use isfor the selection of the optional add-on CGA/VGA Video Card.
After hardware reset, CS0- will be asserted for memory accesses anywhere in the memorymap which allows the processor to boot. However, the chip selects must be programmedimmediately after Reset and prior to any function or subroutine calls, because until they are,CS1- will not be active and therefore it will not be possible for the processor to access RAM.
Example code for setting up the 4 pairs of Chip Select Base and Mask registers is given inModule except.asm
5.4.2.3 Periodic Interrupt Timer.The “sim40_m.c” Module in the Sample Software sets this timer to provide a high priority1mS interrupt which is normally used by the software to provide basic system timing. Thisfunction is controlled by the PICR and the PITR.
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5.4.2.4 Clock Synthesiser ControlThe SYNCR controls the operation of the main processor clock. The MC68340 is providedwith a 32.768KHz reference to which the main clock is phase locked. After reset, the mainclock defaults to 8.39MHz. The maximum clock frequency of the standard MC68340 is16.77MHz.
5.4.2.5 System ProtectionThe SYPCR controls the bus monitors and software watchdog. Other safeguards in thedesign give adequate protection against programme malfunction as a result of noise, etc.The Software Watchdog feature is disabled, however, it could be used if required.
The Bus Monitor should be enabled and may be left set at its default of 64 clock cycles time-out.
5.4.2.6 SIM40 Module Pin AllocationsPins under the control of the SIM40 module are allocated as follows.
Table 1. Allocation of MC68340 Pins Controlled by SIM40 Module
NAME PIN I/O FUNCTIONPA0/A24- 123 O To I/O Expansion Connector P14, Pin b1, 3K3 pull-up &
RESET to Sound Channel #1, U8PA1/A25/IACK1- 122 O To I/O Expansion Connector P14, Pin b2, 3K3 pull-up &
RESET to Sound Channel #2, U39PA2/A26/IACK2- 121 O To I/O Expansion Connector P14, Pin b3, 3K3 pull-up &
Drive for Indicator LED LD2PA3/A27/IACK3- 120 I To I/O Expansion Connector P14, Pin b4, 3K3 pull-up &
Push Button SW3 InputPA4/A28/IACK4- 117 I/O To I/O Expansion Connector P14, Pin b5, 3K3 pull-up &
SCL line (I2C) to RTC, U40 and E2PROM, U37PA5/A29/IACK5- 116 I/O To I/O Expansion Connector P14, Pin b6, 3K3 pull-up &
SDA line (I2C) to RTC, U40 and E2PROM, U37PA6/A30/IACK6- 115 I/O Drives S1 pin on SFX Channel #2 (U39) 3K3 pull-up &
MPX Lamp Current Sense InputPA7/A31/IACK7- 114 I/O Drives S2 pin on SFX Channel #2 (U39) 3K3 pull-up &
MPX Lamp Short Circuit Sense InputPB0/MODCK 87 O Drive LOW to initiate hardware reset.PB1/IRQ1-/CS1- 2 O CS1- Maps RAMPB2/IRQ2-/CS2- 3 O CS2- Maps FPGA registers and I/OPB3/IRQ3- 4 I Vmeter current sense input.PB4/IRQ4-/CS3- 5 I/O To I/O Expansion Connector P14, Pin a3PB5/IRQ5- 8 I/O To I/O Expansion Connector P14, Pin b15, 3K3 pull-upPB6/IRQ6- 9 I/O To I/O Expansion Connector P14, Pin b16, 3K3 pull-upPB7/IRQ7- 10 I IRQ7-/NMI input from Power Fail Detection CircuitCS0-/AVEC- 1 O CS0- Maps ROM, both on-board U1/U2 and on Memory
Expansion Connector (via FPGA).
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5.4.3 DMA Controller ModuleThe DMA Module provides 2 DMA Channels. On the Pluto 5 these are used for sending sound datafrom the Programme Memory to the OKI MSM6585 Sound Chip(s). DMA Channel 1 is used to senddata to Sound Channel #1, which is fitted as standard to the Pluto 5 Board. DMA Channel 2 is used forthe optional add-on Sound Channel #2 if fitted (IC39).
The DMA channel should be set to work in following modes:
• External request• Dual address• Source address incrementing (Memory)• Destination address not incrementing (FPGA sound register)• Transfer size = byte• Interrupt on completion
Pins controlled by the DMA module are allocated as follows:
Table 2. Allocation of MC68340 Pins Controlled by DMA Module
PIN NO. I/O FUNCTIONDREQ1- 16 I SFX Channel 1 DMA requestDACK1- 15 O No connectionDONE1- 14 IO Not used, 3K3 pull-upDREQ2- 13 I SFX Channel 2 DMA requestDACK2- 12 O No connectionDONE2- 11 IO Not used, 3K3 pull-up
5.4.4 Serial ModuleThe Serial Module provides Asynchronous Comms on 2 Channels, Channel A and Channel B. It isfunctionally very similar to the 1681/68681 range of DUARTs.
Channel A is buffered to RS232 levels and connected to connector P1. Signals RX, TX, RTS and CTSare provided.
Channel B is buffered to RS232 levels and connected to DATAPORT connector P2. Signals RX, TX,RTS and CTS are provided.
The 4 Channel A signals are also made available on the TTL Expansion Connector, P14, at TTLlevels. Thus, alternative interfaces may be provided on an Add-on Board to allow, say, RS485 or MarsHII interfaces to be implemented.
The exact set up of the Serial Module will obviously depend upon the functionality required.
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Pins controlled by the Serial module are allocated as follows:
Table 3. Allocation of MC68340 Pins Controlled by Serial Module
PIN NO. I/O FUNCTIONRXDA 33 I RX DATA Channel A, P1, Pin 2 (RS232 level) &
To IO Expansion Connector P14, Pin c9 (TTL level)TXDA 32 O TX DATA Channel A, P1, Pin 3 (RS232 level) &
To IO Expansion Connector P14, Pin c10 (TTL level)RXDB 25 I RX DATA Channel B, DATAPORT P2 (RS232 level)TXDB 24 O TX DATA Channel B, DATAPORT P2 (RS232 level)OP0/RTSA- 29 O RTS Channel A, P1, Pin 5 (RS232 level) &
To IO Expansion Connector P14, Pin c12 (TTL level)OP1/RTSB- 23 O RTS Channel B, DATAPORT P2 (RS232 level)OP4/RXRDYA- 27 O SFX Channel #1 – U8, Pin S1 (Select Sample Rate)OP6/TXRDYA- 26 O SFX Channel #1 – U8, Pin S2 (Select Sample Rate)CTSA- 28 I CTS DUART Channel A, P1, Pin 4 (RS232 level) &
To IO Expansion Connector P14, Pin c11 (TTL level)CTSB- 22 I CTS Channel B, DATAPORT P2 (RS232 level)
5.4.5 Timer Module
The Timer Module provides 2 General Purpose Timers.
The Pluto 5 Board uses these to provide a variable duty-cycle signals on TOUT1 and TOUT2 that isused to control the volume setting on each channel of the TDA7057AQ Stereo Audio Amplifier.
Timer 1 (TOUT1) controls the volume of Sound Channel #1. Timer 2 TOUT2) controls the volume ofSound Channel #2 if it is fitted. If Sound Channel #2 is not fitted, then Timer 2 may be used for otherpurposes.
See Section 6.9, “Making Sounds” for detailed information on the operation of the Volume Controls.
Pins TGATE1- and TGATE2- are allocated as general purpose inputs which are used to read the SCLand SDA lines on the External I2C Connector, P13.
Pins controlled by the Timer Module are allocated as follows:
Table 4. Allocation of MC68340 Pins Controlled by Timer Module
PIN NO. I/O FUNCTIONTGATE1- 79 I Read External I2C line SCL on P13, Pin 3 (inverted)TIN1 81 I Not Used – Strapped To VccTOUT1 80 O Variable Duty Cycle Volume Control SFX Channel #1TGATE2- 36 I Read External I2C Line SDA on P13, Pin 2 (inverted)TIN2 34 I Not Used - Strapped To VccTOUT2 35 O Variable Duty Cycle Volume Control SFX Channel #2
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5.5 FPGA
The Pluto 5 Controller is fitted with an 84 lead PLCC socket, position U6, into which is plugged anFPGA. The standard FPGA type used is an Actel A40MX04-PL84. The purpose of fitting an FPGA tothe system is twofold. First, to allow the Pluto 5 Controller to be uniquely configured for each user ofthe system to give commercial and software security (see the FPGA SECURITY MANUAL).Secondly, it allows particular advanced features, for example, the EPROM Autoselect and Multiplexdimming, to be economically implemented.
The following main functions are carried out by the FPGA:
• Control automatic EPROM mode selection• Generate control signals for on-board EPROM and RAM• Generate control signals for Memory Expansion Connector P15.• Generate DMA requests and multiplex data for Sound Channels 1 & 2.• Control and drive of data to Multiplex Arrays, both on-board MPX1 and expansion MPX2.• Provide various levels of Software Security.• Form an oscillator with 14.75MHz resonator:• Generate Main Clock, EXTAL for MC68340 Processor @32.768kHz.• Generate clock for MC68340 Serial Module @3.6864MHz.• Generate clock for OKI MSM6585 devices, U8/39 @640KHz.
5.6 EPROM Sockets / EPROM Autoselect Feature
The 2 EPROM positions, U1 and U2, are configured such that 4 possible configurations of programmememory are possible (assuming no external memory expansion via P15):
Table 5. Possible EPROM Configurations
U1 U2 Mode Configuration Total Size Addressesscrambled
27C040 omit 8 bit 512k*8 512Kbyte no27C040 27C040 16 bit 512K*16 1Mbyte yes27C801 omit 8 bit 1024k*8 1Mbyte no27C801 27C801 16 bit 1024k*16 2Mbyte yes
It is not necessary to change any links on the board in order to switch between different memoryconfigurations. All relevant switching is carried out within the FPGA, which contains an “EPROMAutoselect” feature. After Power-up, during the reset period, the FPGA reads the top byte address ofU1. Data contained in this byte defines the memory configuration required and the FPGAsets up the control lines to the EPROM sockets accordingly, so that, at the end of reset, theprocessor is able to read the EPROM(s) correctly.
Thus, after the final linked EPROM software module has been created, prior to being blown intoEPROM, the top location of the memory must be overwritten with suitable data to signify the EPROMconfiguration that will be used.
This is the feature referred to as EPROM Autoselect. A full operational description of this feature isgiven in the User manual for the FPGA in use on the Pluto 5 Controller Board.
As with the Pluto 1 System, in order to facilitate the option to use either 1 or 2 EPROMs, i.e. run in 8bit or 16 bit mode, it is necessary to have some scrambling of the address lines to the EPROMs whenoperating in 16 bit mode. Therefore, prior to blowing 16 bit EPROMs, the data must be re-arranged tocompensate. A software utility is provided with the Pluto 5 Development Kit to carry this out.
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Note that this scrambling of address lines is applicable ONLY to sockets U1 and U2 on the Pluto 5Controller Board. Any EPROM sockets on Memory Expansion Cards are connected 1:1 to theaddress bus and do NOT require any special processing.
5.7 EPROM Address Line Scrambling in 16 Bit Mode
5.7.1 2*27C040 EPROMsIn 16 bit mode, running with 2 * 27C040 EPROMs, the scrambling of the address lines cause thefollowing effect on the memory mapping in the EPROMs. Note that this table applies to the re-mappingthat occurs to the EPROM contents, rather than the actual address lines.
Table 6. Re-Mapping of Address Lines in 2*27C040 Mode
68340 Address Bus EPROM AddressA0 Not Used in 16 Bit ModeA1-A18 A2-A19A19 A1
Thus, for example, addresses will be translated as follows so the contents of the EPROM must be re-arranged to compensate:
Table 7. Re-Mapping of EPROM Contents in 2*27C040 Mode
68340 Access Address Will Read From This Location inEPROM
0000 0000 0000 00000000 0002 0000 00040000 0004 0000 00080000 0006 0000 000C0000 0008 0000 0010
| |0007 FFFC 000F FFF80007 FFFE 000F FFFC0008 0000 0000 00020008 0002 0000 0006
| |000F FFFC 000F FFFA000F FFFE 000F FFFE
5.7.2 2*27C801 EPROMsIn 16 bit mode, running with 2 * 27C801 EPROMs, the scrambling of the address lines cause thefollowing effect on the memory mapping in the EPROMs. Note that this table applies to the re-mappingthat occurs to the EPROM contents, rather than the actual address lines.
Table 8. Re-Mapping of Address Lines in 2*27C801 Mode
68340 Address Bus EPROM AddressA0 Not Used in 16 Bit ModeA1-A18 A2-A19A19 A1A20 A20
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Thus, for example, addresses will be translated as follows so the contents of the EPROM must be re-arranged to compensate:
Table 9. Re-Mapping of EPROM Contents in 2*27C801 Mode
68340 Access Address Will Read From This Location inEPROM
0000 0000 0000 00000000 0002 0000 00040000 0004 0000 0008
| |0007 FFFC 000F FFF80007 FFFE 000F FFFC0008 0000 0000 00020008 0002 0000 0006
| |000F FFFC 000F FFFA000F FFFE 000F FFFA0010 0000 0010 00000010 0002 0010 00040010 0004 0010 0008
| |0017 FFFC 001F FFF80017 FFFE 001F FFFC0018 0000 0010 00020018 0002 0010 0006
| |001F FFFC 001F FFFA001F FFFE 001F FFFA
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5.8 Memory Expansion
Various optional memory cards may be fitted to the Memory Expansion Connector P15. Seven linesfrom the FPGA are included along with 16 data lines and 21 address lines.
The default functionality of the FPGA lines allows memory cards fitted with up to 4 EPROM or FLASHdevices to be accommodated along with a pair of RAM devices with no additional mappingcomponents.
If a memory card is fitted with 5V FLASH devices, then Write facilities are available. EPROMAutoselect is also available with devices fitted on a Memory Card.
5.9 Open Drain Outputs, OP0-63
A block of 64 Open Drain Outputs, OP0-63, are provided by 8 off TPIC6259 devices U22-U29 (seeSchematic Sheet 6 - Outputs).
These are memory mapped as the least significant byte of a block of 8 words of address space. Thechip select for these devices, CS_OP-, is provided by the FPGA. Consult the User Manual of theFPGA being used for exact mapping.
Please note that the chips are bit wide, not byte wide. Thus, Bit 0 of each word drives one device,U22: Bit 1 drives U23, etc.
Table 10. Mapping of Open Drain Outputs (OP0-63) to TPIC6259 Devices
Bit D7 D6 D5 D4 D3 D2 D1 D0Pin U29 U28 U27 U26 U25 U24 U23 U22 Addr.Q7 OP63 OP62 OP61 OP60 OP59 OP58 OP57 OP56 Base+14Q6 OP55 OP54 OP53 OP52 OP51 OP50 OP49 OP48 Base+12Q5 OP47 OP46 OP45 OP44 OP43 OP42 OP41 OP40 Base+10Q4 OP39 OP38 OP37 OP36 OP35 OP34 OP33 OP32 Base+8Q3 OP31 OP30 OP29 OP28 OP27 OP26 OP25 OP24 Base+6Q2 OP23 OP22 OP21 OP20 OP19 OP18 OP17 OP16 Base+4Q1 OP15 OP14 OP13 OP12 OP11 OP10 OP9 OP8 Base+2Q0 OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 Base+0
Basically, the drive capability of these devices is 250mA per output, continuous, with all outputs ON. Ifless than 8 outputs are ON in any one package, or any outputs are operating with a small load, thecapacity of the other outputs increases. For example, at 25°C, the TPIC6259 can sink 400mAcontinuously from 3 outputs. Please refer to the data sheet for the TPIC6259 (tpic6259.pdf) fordetails.
When allocating any output to a load greater than 250mA, consideration should be given to theloading on each device. See Section 6.1, “Driving Reels” for details on driving standard reelmechanism stepper motors.
Note also that, because they are MOSFETs, the outputs are resistive (<2Ω) and do not suffer from theminimum saturation voltage of about 1V which would be the case if they were darlingtons. Therefore,at low currents, they pull down close to Gnd and may be safely used to drive TTL Inputs, SwitchStrobes, Coin Mechanism Enables, etc.
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5.10 AUX Outputs, AUX0-7
8 auxiliary TTL level open drain outputs are provided by U30 (see Schematic Sheet 9 - IOConnectors). U30 is a TPIC6B259 which functions exactly the same as the TPIC6259 devices used todrive OP0-63, but with a lower drive capability (see data sheet “tpic6b259.pdf”).
They are memory mapped as the least significant bit of a block of 8 bytes of address space at anaddress determined by the FPGA fitted to the board. See the appropriate FPGA User Manual fordetails.
They are open drain outputs fitted with 1K pull-up resistors to Vcc.
AUX0-5 are routed to connector P12 “AUX OUTPUTS”.
AUX6-7 are routed to Connector P13 “I2C”.
5.11 Inputs, IP0-31
External inputs are catered for by 32 input lines, IP0-31 (see Schematic Sheet 7 - Inputs). Like theOpen Drain outputs these are memory mapped as the least significant byte of a block of 4 words ofaddress space.
Each input is provided with a 3K3 pull-up resistor to Vcc (+5V) and feeds into a 74HC family device(rather than 74HCT). This give the inputs a low level threshold of <1.5V and a high threshold of>3.5V. The 47K resistor in series with the input protects the 74HC253 devices from noise spikes orhigh voltages on the inputs.
The 1.5V low threshold allows the inputs to be safely driven as a multiplexed array with a diode inseries with each switch with the strobes generated using a number of the Open Drain Outputs, OP0-63, described above.
The 32 inputs are mapped as shown in the following table. The top 4 bits of each word are read as“1”s and bits 8 to 11 contain the DIL Switch Settings (as described in the next section). The baseaddress is defined by the FPGA.
Table 11. Mapping of Inputs IP0-31
D15-12 D11-8 D7 D6 D5 D4 D3 D2 D1 D0Base+6 0xF
DILSW
IP31 IP30 IP29 IP28 IP27 IP26 IP25 IP24
Base+4 0xF IP23 IP22 IP21 IP20 IP19 IP18 IP17 IP16Base+2 0xF IP15 IP14 IP13 IP12 IP11 IP10 1P9 IP8Base 0xF IP7 IP6 IP5 IP4 IP3 IP2 IP1 IP0
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5.12 DIL Switches
The Pluto 5 board is equipped with two 8 way DIL Switches, SW1 and SW2. These are read at thesame addresses as the 32 Inputs (see preceding Section).
Table 12. Mapping of DIL Switch Inputs
D15-D12 D11 D10 D9 D8 D7-D0Base+6 0xF SW2:8 SW2:7 SW1:8 SW1:7 IP31-24Base+4 0xF SW2:6 SW2:5 SW1:6 SW1:5 IP23-16Base+2 0xF SW2:4 SW2:3 SW1:4 SW1:3 IP15-8Base 0xF SW2:2 SW2:1 SW1:2 SW1:1 IP7-0
5.13 Software Controlled Indicator LED
LD2 is a green LED that may be turned on or off under software control (see Schematic Sheet 9 - IOConnectors). The LED may be used to provide an indication that software is running or perhaps forfault diagnosis.
The PORTA2 line from the MC68340 SIM40 Module drives the LED. After reset, the PORTA pins arehigh impedance and pulled high by resistor network N11. This signal passes through the inverter U7Fwhich thus turns ON the LED. Therefore, initially and with no action on the part of the software, theLED will be ON indicating that Vcc is present.
If the software sets PORTA2 pin as an output and drives it low, the LED will go OFF.
The PORTA pins are taken to the I/O Expansion Connector P14. Future I/O Expansion Cards may usethe PORTA2 pin for some other function, in which case this will have to be taken into considerationwhen operating the indicator LED.
5.14 On-board Push Button
A Push Button Switch, SW3, is provided on the board (see Schematic Sheet 2 - CPU). The function ofthis switch is at the discretion of the user of the board.
It is connected so as to pull the PORTA3 line from the MC68340 SIM40 Module to Gnd whenoperated.
The PORTA pins are taken to the I/O Expansion Connector P14. Future I/O Expansion Cards may usethe PORTA3 pin for some other function, in which case the possible interaction with SW3 will have tobe taken into account.
5.15 Multiplexer
The Pluto 5 Controller board provides hardware assistance (within the FPGA) to the Processorallowing two 32*16 Multiplex Arrays (referred to below as MPX1 and MPX2) to be controlled. From a“logical” or software point of view, these arrays are uncommitted and may be configured to be eitherLamp or LED drives, depending on what interface components are fitted. When running the lampsfrom a 48V supply, a 1 in 16 duty cycle is employed on the column strobes (sinks) allowing the fullcapabilities of the two arrays, MPX1 and MPX2 to be utilised. If the multiplexed lamps are run from a36V supply, a 1 in 8 duty cycle must be utilised and the useable size of the two arrays reduces to32*8.
The Pluto 5 256/32 Controller Board is intended for customers who run with a 48V lamp supply andrequire the maximum drive capability of the board. It has ½ of MPX1 configured as a 16*16 (256)Lamp Drive Array and the other ½ configured as a 16*16 (32 seven-segment digits) LED Drive Array.
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The Pluto 5 128/16 Controller Board is intended for users who require less drive capability or whowish to run the lamps at 36V. It has ¼ of MPX1 configured as a 16*8 (128) Lamp Drive Array and theother ¼ configured as a 16*8 (16 seven-segment digits) LED Drive Array.
The other 32*16 Multiplex Array (MPX2) is utilised by adding external low-cost Pluto 5 MultiplexExpansion Boards, wired to Connector P11. Each board only requires 5 signal wires from P11 plusPower Supplies.
Pluto 5 Multiplex Expansion Boards will be available in a number of different sizes, but all based onproviding additional 8*8 blocks of either Lamp or LED drivers. Thus, the basic Pluto 5 configurationmay be expanded externally by another 8 blocks which may be any mix of Lamps or LEDs.
Pluto 5 Multiplex Expansion Boards may also be added to Multiplex Array MPX1 (which is alreadyused by the on-board drivers). Thus, for example, the Pluto 5 128/16 Controller Board, running at48V, could have Expansion Boards added to increase its drive capability to that of the Pluto 5 256/32Controller Board.
The Lamp Multiplex Drive Circuitry is designed to drive 12V, 100mA bulbs. However, it is permissiblefor a small number (up to 16) of positions to drive either a higher power bulb (12V, 180ma) or a pair of100mA bulbs. These "high load" positions should be arranged such that no more than one is on anyone Row or Column drive.
Multiplex Array MPX1 has hardware assistance from the FPGA to enable dimming control. Dimminglevel may be set independently for each of the 16 Column strobes, e.g. the 8 lamps on one ColumnStrobe could be set to one brightness level while the 8 lamps on a different Column Strobe could beset to another brightness. The overall basic timing of the multiplexing remains under software controlallowing “overdrive” of lamps for special effects.
Multiplex Array MPX2 may be optionally configured with its full 32*16 capacity without the availabilityof hardware assisted dimming, or with 16*16 capability with the hardware assisted dimming facilityintact. This option is selected by a bit in the FPGA – see the relevant FPGA User Manual for details.
Dimming is achieved changing the data presented to the Lamp Row/LED Segment drives at anadjustable time within the 1mS strobe time. Thus each lamp/LED has two bits of data associated withit in software – the first bit is the data applied during the first part of the 1mS Strobe period, the secondbit is applied during the second period. The duration of the period that the first bit is applied for may beset in units of 1/16 mS.
The multiplex is software driven. Every 1mS, data for the next strobe is written to the FPGA which inturn formats and serialises the data before clocking out the MPX1 data to the on-board 4094 shiftregisters (U18,U19,U20,U21,U35,U36) and the MPX2 data, via P11, to any Multiplex ExpansionBoards used.
The exact format of the data to be written each millisecond is determined by the design of the FPGAbeing used, but in general it is as follows.
• 32 bits of MPX1 Row/Segment data. First period data.• 32 bits of MPX1 Row/Segment data. Second period data.• 32 bits of MPX2 Row/Segment data. First period data.• 32 bits of MPX2 Row/Segment data. Second period data.• 4 bits defining Column/Digit strobe number to activate.• 4 bits defining First Period duration (units of 62.5S).
Consult the User Manual of the actual FPGA in use for exact details of operation.
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5.16 Multiplexed Lamp Current Sense
A facility is provided to allow the processor to check the 256/128 possible lamp positions of MPX1 todetermine:
a. Is a light bulb present?b. Is there a short circuit in this position?
This facility is intended to be run at power up and, perhaps, as a production test. The facility cannot beused during normal operation of the machine.
A resistance of approximately 24mΩ is implemented, as a copper track on the PCB, between commonsource connection of all the Lamp Column/LED Digit sinks, Q35-50 and Gnd (see Schematic Sheet 11- Lamp Column/LED Digit Drives). The voltage across this resistor is compared against 2 thresholdsformed by resistor chain R124, R125 and R126 by comparators U16C and U16D (see SchematicSheet 8 - Power Supply). These thresholds correspond to nominal currents of about 375mA and 4.8A.
The outputs of the 2 comparators, U16C and U16D are connected to processor lines PORTA6 andPORTA7. The current sensing comparators may be disabled by SFX_CLK being enabled. WhenSFX_CLK, a 640kHz clock, is enabled by setting a bit in the FPGA (see FPGA User Manual), the “+”inputs of the 2 comparators are pulled up to about +5V by D21/C9/C10 which forces the comparatoroutputs (which are open collector) OFF. In this state the lines PORTA6 and PORTA7 are free to beused as outputs driving the S1 & S2 pins of SFX Channel #2 or as required by any card fitted to theI/O Expansion Connector, P14. When the SFX-CLK is turned OFF (and forced low), any voltage onC9/10 is discharged by R127, and the current sensing circuit is enabled.
With no current through the Column/Digit Sinks, both outputs PORTA6/7 will be LOW because V+ < V-on the comparators. When the current through the 24mΩ resistor exceeds a nominal 375mA, PORTA6will go high. When the current exceeds a nominal 4.8A, PORTA7 will also go high.
The sequence of operation to test a lamp is as follows:
• Turn off SFX_CLK in FPGA to enable circuit.• Turn off all Row/Digit drives on MPX1.• Ensure PORTA6 and PORTA7 both read 0• Turn on lamp to be tested on multiplex by writing appropriate data to FPGA.• Start a 1mS timer.• Loop watching lines PORTA6 and PORTA7.• If PORTA7 line goes high, there is a short circuit in this position, so immediately disable the
multiplex drives by turning off Multiplex OE line in the FPGA.• If PORTA6 line goes high but not PORTA7, then there is a light bulb connected and apparently
working.• If 1mS timer times out without either line going high, then either no bulb present or it is open
circuit.• Record result and go on to next bulb.• When complete, act as required on results. Re-enable SFX-CLK to allow Sound Channels to work.
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5.17 Sound Generation
The sound generation circuits are shown on Schematic Sheet 5 - Sound.
U8 and (optionally) U39 are the source of Sound Channel 1 & 2 respectively with the audio outputbeing pin 10, Aout. These OKI MSM6585 devices are 4 bit ADPCM D-A converters capable of runningat sample rates of 4KHz, 8KHz, 16KHz or 32KHz. This rate is selected by software by setting levels onthe S1 and S2 pins. On Channel 1 (U8) these pins are controlled by the OP4 and OP6 lines from theMC68340 Serial Module. On Channel 2 (U39) these pins are controlled by the PORTA6 and PORTA7lines from the MC68340 SIM40 Module.
The VCK- output from the MSM6585 is a square wave at the sampling frequency selected by S1 andS2. The MSM6585 reads the 4 bit sample immediately after the rising edge of VCK-.
The VCK- from the MSM6585 is connected to the FPGA where it is divided by 2 to produce a DMARequest signal to the processor. Sound data is transferred, a byte at a time (1 byte = 2 * 4 bit soundsamples), to the appropriate register within the FPGA by the DMA Module if a sound is being played.The FPGA in turn presents alternately the high and low nibble to the MSM6585 OKI chip.
The sound channel requests a byte of data (via the FPGA) at half the sound sample rate. E.g., if theMSM6585 has been set to run at 16KHz sample rate, the FPGA will issue DMA requests at 8KHz.
These requests are issued continuously to the DMA Module, but in times of silence, the DMAchannels are inactive and therefore no new data is transferred into the FPGA sound register. In thiscase, the user must ensure that the last data written to the FPGA sound register before a period ofsilence is 0x80. This will ensure that, during a silent period, the MSM6585 is being continuously fed arepeated sequence of alternate 0x8 and 0x0 nibbles. This keeps the ADPCM converter in its quiescentstate. If the sound data is generated using the Heber Sound Solutions software, the last byte of thedata is always 0x80, so this condition will automatically be satisfied.
Sound Channel 1 (U8) is fitted as standard and uses DMA Channel 1. Sound Channel 2 (U39) isoptional and uses DMA Channel 2.
The RESET pin of each channel is under individual software control. Pin PORTA0 drives SFXChannel #1 RESET. Pin PORTA1 drives SFX Channel #2 RESET. After Power –Up, these pins willdefault to being inputs and therefore the Resistor network N11 will pull them High, holding both SoundChannels in a RESET state. Before the Sound Channels can be used, these two pins must be set asoutputs by the SIM40.
5.18 Stereo Amplifier and Volume Controls
The Stereo Amplifier is shown on Schematic Sheet 5 - Sound.
U32 is a Philips TDA7057AQ Stereo Audio Amplifier with independent DC volume controls. Note thatthe loudspeaker outputs, on Connector P10, are bridge driven so neither of the loudspeaker wires maybe connected to Gnd.
The DC volume controls of the TDA7057 work over the range 0.4V(min) to 1.2V (Max). The variableduty cycle outputs on pins TOUT1/2 from the two timers in the MC68340 Timer Module are integratedby the combination of two 3K3 resistors and a 1µF capacitor (R108, R109, C45 on Channel 1: R110,R113, C46 on Channel 2) to provide the control voltage needed. The control voltage is given by theformula 2.5*duty cycle where “duty cycle” is the proportion of the time that the TOUT Pin is HIGH.
Normally, Sound Channel 1 (U8, DMA Channel 1) feeds Amplifier Section 1 (volume control - TimerChannel 1) driving LS1. Sound Channel 2 (U39, DMA Channel 2) feeds Amplifier Section 2 (volumecontrol – Timer Channel 2) driving LS2.
A pin on the Loudspeaker Connector, P10, pin 3, which allows the output signal from AmplifierChannel 1 to be fed back into the input of Amplifier Channel 2. This allows various alternative modes
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of operation, for example, if only Sound Channel 1 is fitted, then by linking the LS1+ output to thefeedback pin, the same signal can drive BOTH loudspeakers. See Section 6.9, “Making Sounds”below for a more detailed explanation of the different operational modes that are possible.
5.19 Serial I/O
P1 provides connections to RS232 Channel A, Data Receive & Transmit plus RTS/CTS.
P2 provides connections to RS232 Channel B, Data Receive & Transmit plus RTS/CTS and is in theformat specified by the BACTA standard.
Operation of the above two ports is determined by the operation of the Serial Module in the MC68340Processor. Refer to the Serial Module Section of Motorola MC68340 User Manual for a fullexplanation.
5.20 Internal I2C Bus
An internal I2C Bus is implemented using SIM40 Lines PORTA4 (SCL) and PORTA5 (SDA). This busallows the processor to read and write the optional Real Time Clock chip, U40, and the optionalE2PROM, U37. If neither of these devices is fitted, then these 2 lines are also available on the I/OExpansion Connector P14 and are free for other uses.
5.20.1 Real Time ClockU40 is a position that accepts a Philips PCF8583 I2C Real Time Clock. The standard Pluto 5 Controllerhas a socket fitted in this position along with the 32.768KHz Crystal, X2. However, the PCF8583 IC isNOT fitted as standard but is available as an optional extra or may be fitted by the user.
The I2C Slave Address of the RTC is as follows:
Table 13. I2C Slave Addresses for RTC, U40
READ: 0xA1WRITE: 0xA0
5.20.2 E2PROMU37 position is fitted with a socket that accepts an “Industry Standard” E2PROM, 24C04 (512 bytes) or24C08 (1024 bytes) with pin 7, which serves a different function on devices from differentmanufacturers, connected to GND. The Pluto 5 Controller Boards, as standard, do not have anE2PROM fitted but they are available as an optional extra or may be fitted by the user.
We strongly recommend that, if a user supplies or fits his own devices, that only NM24C04 orNM24C08 devices should be used (manufactured by Fairchild or National Semiconductor). Hebercannot offer Technical Support for the use of devices from alternate manufacturers.
To avoid a clash of I2C addressing between the PCF8583 RTC and the 24Cnn E2PROM, A2 (Pin 3) ofthe E2PROM is strapped to Vcc and A0/A1 to GND and this socket is restricted to accepting devicesno larger than the 24C08. Note, however, that there is no such size restriction on the devices that maybe connected via P13, the External I2C Bus Connector.
The I2C Slave Address of each of the 256 byte “Page Blocks” in the E2PROM, U37, is as follows:
Table 14. I2C Slave Addresses for E2PROM, U37
BLOCK 024C04 or 24C08
BLOCK 124C04 or 24C08
BLOCK 224C08 only
BLOCK 324C08 only
READ 0xA9 0xAB 0xAD 0xAFWRITE 0xA8 0xAA 0xAC 0xAE
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6 MACHINE OPERATION
This section discusses how various standard amusement machine functions can be implemented.
6.1 Driving Reels
Up to six 12V Stepper Motor Reel Mechanisms may be connected to the “REEL” connector, P7. +12Voutputs are available for the motor common connection and GND/Vcc are available for the Optosupply. A 6*6 subset of the Lamp Multiplex is configured so up to 6 lamps per reel may beaccommodated, in either “sinking” or “sourcing” mode (depending on the wiring of the ReelMechanism. 6 inputs, IP0-5, are provided for the Opto Inputs
When driving stepper motor reels, because the maximum (static) current load of each winding is400mA (assuming 30Ω, 12V windings), it is important to connect the motors to distribute the loadevenly amongst the TPIC6259 driver chips.
The recommended method of connection is to wire the reel motors as follows:
Table 15. Recommended Reel Stepper Motor Drive Connections
REEL 1 OP0-3REEL 2 OP4-7REEL 3 OP8-11REEL 4 OP12-15REEL 5 OP16-19REEL 6 OP20-23
This guarantees that a maximum of 3 motor windings are driven simultaneously by any one TPIC6259device which is within the ratings of the device even under the worst case of a reel being stationaryand unchopped. Of course, when the motor is running or is being chopped the average current dropssignificantly.
Extra reels could be connected via pins on the other connectors. Providing the software chops thecurrent to the reels when they are not spinning, an extra 2 reels can be wired to OP24-27 andOP28-31 and should allow the TPIC6259s to remain within their ratings.
NB: The +12V outputs on P7 Pins 45-50 are fed directly from the +12V Input to the Pluto 5 Board onP3, Pin 4. It does not go via Fuse F1 on the board.
6.2 Reading the DIL Switches
The state of the DIL Switches may be read at any time by reading the memory locations as describedin Section 5.12.
6.3 Reading the Switch Inputs
The 32 switch inputs may be read at any time by reading the memory locations as described inSection 5.11 above.
In most applications, these inputs should be debounced in software. A typical debounce algorithmmight be to read the switches every 1mS, but only register a change of state on the input after it hasbeen stable for 3 consecutive readings.
It is possible to implement, say, a 256 multiplexed switch input array by using, 8 of the Open DrainOutputs OP0-63 as strobes and 8 of the Inputs IP0-31. In this case, a diode would need to beconnected in series with each switch.
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6.4 Interfacing to Coin & Note Acceptors
Most Coin or Note Acceptors have open collector (“sink to ground”) outputs. These may be connecteddirectly to any of the Pluto 5 Inputs (IP0-31). Mechanism “Enable” or “Control” inputs may usually bedriven directly from any of the Pluto 5 Open Drain Output lines (OP0-63).
6.5 Interfacing to Coin Payout Mechanisms
Payout Hoppers that require relatively low drive currents, e.g. Coin Controls Universal Hopper, may bedriven directly from an Open Drain Output. Higher current devices, such as 50Vac or 24Vdc PayoutSolenoids, should be driven using Open Drain Outputs via a suitable Triac or Relay Interface Card.Heber produces a number of suitable interfaces.
6.6 Driving Vacuum Fluorescent Displays (VFD)
The standard VFD/Linewriter display used in most Gaming/Amusement Machines is driven by 3 TTLlevel signals, Clock, Data and Reset.
Connector P12 has 6 TTL level outputs which could drive up to 2 display modules.
The mapping of these outputs as the LSB of 6 bytes makes it convenient for the software to implementthe bitwise drive required.
6.7 Using the External I2C Bus
Connector P13 is intended for driving external boards containing I2C Bus components. A common usefor this could be the provision of a removable E2PROM Module for use in Spain or any other countrywith a similar requirement.
Heber have available a small PCB containing a NM24C04 or NM24C08 E2PROM that plugs directly onto P13.
On this connector, the SDA line is driven by the Open Drain Output, AUX7 and may be read by the68340 Timer Module as the (inverted) TGATE2- signal.
Similarly, the SCL line is driven by AUX6 and read by TGATE1.
6.8 Driving Meters
Electromechanical Meters or Counters should be 12V DC parts. The common +12V supply to themshould be the Vmeter+ supply from Connector P9 (“I/O 2”), pin B17 and each should be driven by anOpen Drain Output (OP0-63).
As the meter is pulsed ON, the software should check that the Vmeter Current Sense Input hasoperated, i.e. that pin PORTB4 has gone high.
Because of possible delays in responding to a meter being turned on it is recommended that thesoftware checks the current sense pin immediately before the meter is turned OFF at the end of apulse. To detect tampering or a failure of the current sense circuitry, the software should also checkthat the current sense pin goes LOW when no meter is operated.
6.9 Making Sounds
Loudspeaker outputs on connector P10 are bridge driven, so do NOT connect either connection of aloudspeaker to ground or to any other loudspeaker drive. Ideally 8Ω loudspeaker(s) should be used,but higher impedance components could be used without any risk of damage to the amplifier. The useof 3 or 4ohm loudspeakers should be avoided.
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It is possible to run the sound in the following modes:
6.9.1 Single Channel/Single Speaker (Mono) ModeThis is the lowest cost option, using the standard Pluto 5 Board with a single loudspeaker.
The optional SFX Channel 2, U39, is not fitted and only SFX Channel 1, U8, is operational. A singleloudspeaker is connected to LS1 pins (1 & 2) only. Pins 3,4,5 should be left open.
6.9.2 Dual Channel/Dual Speaker (Stereo) ModeIn Stereo Mode, the optional second channel IC U39 is fitted and 2 loudspeakers are used, connectedto LS1 and LS2 pins. Pin 3 is left open. Channel 1 Volume Control will adjust the level of LS1, Channel2 Volume Control will adjust the level of LS2.
In this mode true stereo sound effects may be reproduced, although the subjective effect heard by theplayer will depend upon the placement of the loudspeakers in the cabinet.
6.9.3 Known DMA ProblemsThe “E” version of the Motorola 68340 mask that is current at the time of this manual being written(MC68340PV16E, Mask # 2G67F) exhibits a DMA fault which can cause audible disturbances on asound effect.
This disturbance occurs when the memory area being transferred to the SFX Register in the FPGAincludes the hexadecimal address range xxx3 FFxx. (x meaning any hexadecimal digit).
Thus, to avoid this problem occurring, precautions should be taken when linking sound effect modulesInto the final EPROM map. We suggest that, programme and EPROM size permitting, the area fromhex 0000 0000 to 0003 FFFF (256Kbytes) be reserved for the executable portion of the code, withsound effects commencing at hex address 0004 0000. If the total EPROM size exceeds 1Mbyte, thenno sound effect should include data in the range 0013 FF00 to 0013 FFFF. Similarly, with largerEPROM maps, regions at 0023 FFxx, 0033 FFxx, etc should also be avoided.There is NO problem with code execution in these areas, the only difficulty occurs when a Sound DMAtransfer passes through these regions.
We believe that these problems are reduced or eliminated when the Function Code Register (FCR)in the DMA Module is initialised to value 0xDD.
6.10 Using Multiplexed Lamps
On all Multiplex lamp outputs, the Column Drives, LC0-15, SINK current to ground and the RowDrives, LR0-15, SOURCE current from the Lamp Supply (+36V or +48V). Thus, any lamps should beconnected between a Row and a Column drive with their series diodes orientated with the cathodetowards the Column Drive.
The choice of operation at 36V or 48V is determined by the Power Supply and the software. Whenrunning at 48V, the software will sequentially drive all 16 Columns, LC0-15, on a 1/16 duty cycle, eachcolumn being ON for 1mS and OFF for 15.
When running at 36V, the software will sequentially drive only the first 8 Columns (LC0-7) on a 1/8duty cycle, each column being ON for 1mS and OFF for 7.
The Lamp Multiplex Drive Circuitry is designed to drive 12V, 100mA bulbs. However, it is permissiblefor a small number (up to 16) of positions to drive either a higher power bulb (12V, 180ma) or a pair of100mA bulbs. These "high load" positions should be arranged such that no more than one is on anyone Row or Column drive.
6.11 Using Multiplexed LEDs
The multiplexed LED drive circuit is intended to be used with Common Cathode digits, either 7segment plus decimal point or 14 segment. The common cathode connection of each digit should be
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connected to a digit drive output, DIG0-15, on connector P5. Each digit drive output can drive two 7Segment Digits, the segment anodes for one connecting to drive SEG0-7 and the other to SEG8-15.By convention, segment “a” would connect to SEG0 or SEG8.
Alternatively, 14 segment starburst digits can be used, in which case each digit output would drive onedigit and the 14 segment anodes should each be connected to one of the segment drive lines, SEG0-13.
The LED Digit drive circuitry shares the same Current Sink transistors as the Lamp Column drives.Thus, if the system is being driven in a 1/8 duty cycle to allow a 36V Lamp Supply, only Digit drivelines DIG0-7 are active (or the board is a Pluto 5 128/16). In this case only 16 Seven Segment LEDdigits may be driven from the controller.
6.12 Using the Multiplex Expansion Connector
The outputs on P11 are all CMOS signals swinging between GND and +12V. These signals may beconnected to Pluto 5 Multiplex Expansion Boards to increase the Lamp and/or LED drive capability ofthe system.
See the PLUTO 5 MULTIPLEX EXPANSION BOARD USER MANUAL for details of connection andoperation.
6.13 Adding Video Capabilities
A Calypso 16 Video Card is available from Heber Ltd. which plugs directly onto the Pluto 5 board viathe 2 DIN41612 connectors P14 and P15.
See the CALYPSO 16 USER MANUAL for details.
The Calypso 16 Video Card supersedes the Pluto 5 CGA/VGA Video Card. For further information onthe Pluto 5 CGA/VGA Video Card refer to the PLUTO 5 CGA/VGA BOARD USER MANUAL.
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7 SOFTWARE DEVELOPMENTA number of options exist for the development and debug of software for use on Pluto 5.
Software will normally be generated using a Cross Assembler, Cross Compiler and Linker package. Asuitable package is included with the Pluto 5 Development Kit.
When software has been successfully compiled, assembled and linked, it may be tested anddebugged using the Background Debug Mode facility built in to the 68340 Processor.
For full details of debugging, refer to the PLUTO 5 DEVELOPMENT KIT QUICK START GUIDE andother documentation supplied with the Development Kit.
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8 CONNECTOR TYPES AND PIN OUTS
8.1 Schedule of Connector Types
There are two types of Pluto 5 Board with either Ultrex or Box Header connectors, and 3 other familiesof connectors:
• Pluto 5 with Ultrex connectors is referred to as Pluto 5U• Pluto 5 with Box Header connectors is referred to as Pluto 5B
Pluto 5U uses the following 4 different families of connectors for connection to the cableform in themachine:
• AMPMTA-100. 2.54mm single in-line headers with friction lock and polarisation.• AMP MTA-156. 3.96mm single in-line headers with friction lock and polarisation.• AMP Ultrex. 2.54mm dual row headers.• 25 way “D” Type
Pluto 5B uses the following 4 different families of connectors for connection to the cableform in themachine:
• AMPMTA-100. 2.54mm single in-line headers with friction lock and polarisation.• AMP MTA-156. 3.96mm single in-line headers with friction lock and polarisation.• Tyco Box Header 2.54mm dual row headers• 25 way “D” Type
The actual part numbers of the board headers fitted to the Pluto 5 PCBs along with the part numbersof suitable mating (cableform) parts are given in the following tables:
Table 16. AMP Ultrex Connector Part Numbers
Ident Description PCB HeaderAMP Part No.
AMP IDC Connector Part Number
28-24 AWG WireP5 32W Ultrex 3-172870-2 3-172866-2P7 50W Ultrex 5-172870-0 5-172866-0P8 40W Ultrex 4-172870-0 4-172866-0P9 34W Ultrex 3-172870-4 3-172866-4
Table 17. Tyco Box Header Connector Part Numbers
Ident Description PCB HeaderTyco Part No.
Tyco IDC Connector Part Number
28-24 AWG WireP5 34W Box Header 7-1437061-5 102387-8P7 50W Box Header 9-1437061-5 102387-0P8 40W Box Header 8-1437061-5 102387-9P9 34W Box Header 7-1437061-5 102387-8
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Table 18. AMP MTA-100 Connector Part Numbers
Ident Description PCB HeaderAMP Part No.
AMP IDC Connector Part Number
24 AWG (0.22mm2)(Colour Natural)
22 AWG Wire(0.35mm2)(Colour Red)
P1 6W MTA-100 640456-6 640621-6 640620-6P4 18W MTA-100 1-640456-8 1-640621-8 1-640620-8P6 16W MTA-100 1-640456-6 1-640621-6 1-640620-6P10 5W MTA-100 640456-5 640621-5 640620-5P11 7W MTA-100 640456-7 640621-7 640620-7P12 8W MTA-100 640456-8 640621-8 640620-8P13 4W MTA-100 640456-4 640621-4 640620-4
Table 19. AMP MTA-156 Connector Part Numbers
Ident Description PCB HeaderAMP Part No.
AMP IDC Connector Part Number
24 AWG (0.22mm2)(Colour Natural)
20 AWG Wire(0.5mm2)(Colour Yellow)
P3 6W MTA-156 640388-6 640429-6 640427-6
The above MTA-100 and MTA-156 IDC Connector Part Numbers are for illustration and are of the“Feed-Through Receptacle without Polarising Tabs” type. A number of alternatives exist that couldalso be used, for example “Closed-End” types. Please consult the relevant AMP information for anexhaustive list. If you have Internet Access, the information is also available on the AMP Web Site athttp://www.amp.com/.
Strain relief covers are also available.
8.2 P1 – RS232 Channel A
Reference: P1Type: Header 6W AMP MTA-100Description: RS232 Channel A
1 GND2 RXA Input to Pluto 53 TXA Output from Pluto 54 CTSA Input to Pluto 55 RTSA Output from Pluto 56 +12V
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8.3 P2 – Dataport (RS232 Channel B)
Reference: P2Type: 25W ‘D’ SocketDescription: BACTA Dataport / RS232 Channel B
nc 114 nc
RXB (Input to Pluto 5) 215 nc
TXB (Output from Pluto 5) 316 nc
CTSB (Input to Pluto5) 417 nc
RTSB (Output from Pluto 5) 518 GND
nc 619 nc
GND 720 nc
nc 821 nc
nc 922 nc
nc 1023 nc
-12V 1124 nc
nc 1225 +12V
nc 13
8.4 P3 – Power Input
Reference: P3Type: Header 6W AMP MTA-156Description: Power
1 -12V Neg supply for RS232 buffers2 GND Ground3 GND Ground4 +12V Main supply5 GND Ground6 Vmpx+ Lamp MPX supply, +36V or +48V
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8.5 P4 – Multiplexed Lamp Sinks
Reference: P4Type: Header 18W AMP MTA-100Description: Lamp Columns/Sinks
1 LC0 Lamp Column/Sink 02 LC1 Lamp Column/Sink 13 LC2 Lamp Column/Sink 24 LC3 Lamp Column/Sink 35 LC4 Lamp Column/Sink 46 LC5 Lamp Column/Sink 57 LC6 Lamp Column/Sink 68 LC7 Lamp Column/Sink 79 LC8* Lamp Column/Sink 8 (PLUTO 5 256/32 only)10 LC9* Lamp Column/Sink 9 (PLUTO 5 256/32 only)11 LC10* Lamp Column/Sink 10 (PLUTO 5 256/32 only)12 LC11* Lamp Column/Sink 11 (PLUTO 5 256/32 only)13 LC12* Lamp Column/Sink 12 (PLUTO 5 256/32 only)14 LC13* Lamp Column/Sink 13 (PLUTO 5 256/32 only)15 LC14* Lamp Column/Sink 14 (PLUTO 5 256/32 only)16 LC15* Lamp Column/Sink 15 (PLUTO 5 256/32 only)17 nc No Connection18 nc No Connection
* Column Sinks LC8-15 are omitted on Pluto 5 128/16
8.6 P5 Ultrex – Multiplexed LEDs
Reference: P5Type: Header 32W AMP UltrexDescription: LED - Drive for 16 or 32 seven-segment LED Digits.
Cathodes, Digit 0 DIG0 A1 B1 DIG1 Cathodes, Digit 1Cathodes, Digit 2 DIG2 A2 B2 DIG3 Cathodes, Digit 3Cathodes, Digit 4 DIG4 A3 B3 DIG5 Cathodes, Digit 5Cathodes, Digit 6 DIG6 A4 B4 DIG7 Cathodes, Digit 7Cathodes, Digit 8 DIG8 A5 B5 DIG9 Cathodes, Digit 9Cathodes, Digit 10 DIG10 A6 B6 DIG11 Cathodes, Digit 11Cathodes, Digit 12 DIG12 A7 B7 DIG13 Cathodes, Digit 13Cathodes, Digit 14 DIG14 A8 B8 DIG15 Cathodes, Digit 15Anodes, Segment 0 SEG0 A9 B9 SEG1 Anodes, Segment 1Anodes, Segment 2 SEG2 A10 B10 SEG3 Anodes, Segment 3Anodes, Segment 4 SEG4 A11 B11 SEG5 Anodes, Segment 5Anodes, Segment 6 SEG6 A12 B12 SEG7 Anodes, Segment 7Anodes, Segment 8 SEG8* A13 B13 SEG9* Anodes, Segment 9Anodes, Segment 10 SEG10* A14 B14 SEG11* Anodes, Segment 11Anodes, Segment 12 SEG12* A15 B15 SEG13* Anodes, Segment 13Anodes, Segment 14 SEG14* A16 B16 SEG15* Anodes, Segment 15
* Common Cathode Drives DIG8-15 are omitted on Pluto 5 128/16
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8.7 P5 Box Header – Multiplexed LEDs
Reference: P5Type: Header 34W Tyco Box HeaderDescription: LED - Drive for 16 or 32 seven-segment LED Digits.
Not Used 1 2 Not UsedCathodes, Digit 0 DIG0 3 4 DIG1 Cathodes, Digit 1Cathodes, Digit 2 DIG2 5 6 DIG3 Cathodes, Digit 3Cathodes, Digit 4 DIG4 7 8 DIG5 Cathodes, Digit 5Cathodes, Digit 6 DIG6 9 10 DIG7 Cathodes, Digit 7Cathodes, Digit 8 DIG8 11 12 DIG9 Cathodes, Digit 9Cathodes, Digit 10 DIG10 13 14 DIG11 Cathodes, Digit 11Cathodes, Digit 12 DIG12 15 16 DIG13 Cathodes, Digit 13Cathodes, Digit 14 DIG14 17 18 DIG15 Cathodes, Digit 15Anodes, Segment 0 SEG0 19 20 SEG1 Anodes, Segment 1Anodes, Segment 2 SEG2 21 22 SEG3 Anodes, Segment 3Anodes, Segment 4 SEG4 23 24 SEG5 Anodes, Segment 5Anodes, Segment 6 SEG6 25 26 SEG7 Anodes, Segment 7Anodes, Segment 8 SEG8* 27 28 SEG9* Anodes, Segment 9Anodes, Segment 10 SEG10* 29 30 SEG11* Anodes, Segment 11Anodes, Segment 12 SEG12* 31 32 SEG13* Anodes, Segment 13Anodes, Segment 14 SEG14* 33 34 SEG15* Anodes, Segment 15
* Common Cathode Drives DIG8-15 are omitted on Pluto 5 128/16
8.8 P6 – Multiplexed Lamps Sources
Reference: P6Type: Header 16W AMP MTA-100Description: Lamp Rows/Sources
1 LR0 Lamp Row/Source 02 LR1 Lamp Row/Source 13 LR2 Lamp Row/Source 24 LR3 Lamp Row/Source 35 LR4 Lamp Row/Source 46 LR5 Lamp Row/Source 57 LR6 Lamp Row/Source 68 LR7 Lamp Row/Source 79 LR8 Lamp Row/Source 810 LR9 Lamp Row/Source 911 LR10 Lamp Row/Source 1012 LR11 Lamp Row/Source 1113 LR12 Lamp Row/Source 1214 LR13 Lamp Row/Source 1315 LR14 Lamp Row/Source 1416 LR15 Lamp Row/Source 15
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8.9 P7 Ultrex – Reels
Reference: P7Type: Header 50W AMP UltrexDescription: Reels - Connector for 6 Stepper Motor Reel Mechanisms
Lamp Column 0 LC0 A1 B1 LC1 Lamp Column 1Lamp Column 2 LC2 A2 B2 LC3 Lamp Column 3Lamp Column 4 LC4 A3 B3 LC5 Lamp Column 5
Lamp Row 0 LR0 A4 B4 LR1 Lamp Row 1Lamp Row 2 LR2 A5 B5 LR3 Lamp Row 3Lamp Row 4 LR4 A6 B6 LR5 Lamp Row 5
GND A7 B7 VCCOpen Drain Output 0 OP0 A8 B8 OP1 Open Drain Output 1Open Drain Output 2 OP2 A9 B9 OP3 Open Drain Output 3Open Drain Output 4 OP4 A10 B10 OP5 Open Drain Output 5Open Drain Output 6 OP6 A11 B11 OP7 Open Drain Output 7Open Drain Output 8 OP8 A12 B12 OP9 Open Drain Output 9Open Drain Output 10 OP10 A13 B13 OP11 Open Drain Output 11Open Drain Output 12 OP12 A14 B14 OP13 Open Drain Output 13Open Drain Output 14 OP14 A15 B15 OP15 Open Drain Output 15Open Drain Output 16 OP16 A16 B16 OP17 Open Drain Output 17Open Drain Output 18 OP18 A17 B17 OP19 Open Drain Output 19Open Drain Output 20 OP20 A18 B18 OP21 Open Drain Output 21Open Drain Output 22 OP22 A19 B19 OP23 Open Drain Output 23
Input 0 IP0 A20 B20 IP1 Input 1Input 2 IP2 A21 B21 IP3 Input 3Input 4 IP4 A22 B22 IP5 Input 5
+12V A23 B23 +12V+12V A24 B24 +12V+12V A25 B25 +12V
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8.10 P7 Box Header – Reels
Reference: P7Type: Header 50W Box HeaderDescription: Reels - Connector for 6 Stepper Motor Reel Mechanisms
Lamp Column 0 LC0 1 2 LC1 Lamp Column 1Lamp Column 2 LC2 3 4 LC3 Lamp Column 3Lamp Column 4 LC4 5 6 LC5 Lamp Column 5
Lamp Row 0 LR0 7 8 LR1 Lamp Row 1Lamp Row 2 LR2 9 10 LR3 Lamp Row 3Lamp Row 4 LR4 11 12 LR5 Lamp Row 5
GND 13 14 VCCOpen Drain Output 0 OP0 15 16 OP1 Open Drain Output 1Open Drain Output 2 OP2 17 18 OP3 Open Drain Output 3Open Drain Output 4 OP4 19 20 OP5 Open Drain Output 5Open Drain Output 6 OP6 21 22 OP7 Open Drain Output 7Open Drain Output 8 OP8 23 24 OP9 Open Drain Output 9Open Drain Output 10 OP10 25 26 OP11 Open Drain Output 11Open Drain Output 12 OP12 27 28 OP13 Open Drain Output 13Open Drain Output 14 OP14 29 30 OP15 Open Drain Output 15Open Drain Output 16 OP16 31 32 OP17 Open Drain Output 17Open Drain Output 18 OP18 33 34 OP19 Open Drain Output 19Open Drain Output 20 OP20 35 36 OP21 Open Drain Output 21Open Drain Output 22 OP22 37 38 OP23 Open Drain Output 23
Input 0 IP0 39 40 IP1 Input 1Input 2 IP2 41 42 IP3 Input 3Input 4 IP4 43 44 IP5 Input 5
+12V 45 46 +12V+12V 47 48 +12V+12V 49 50 +12V
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8.11 P8 Ultrex – General I/O #1
Reference: P8Type: Header 40W AMP UltrexDescription: General Purpose I/O #1
Open Drain Output 24 OP24 A1 B1 OP25 Open Drain Output 25Open Drain Output 26 OP26 A2 B2 OP27 Open Drain Output 27Open Drain Output 28 OP28 A3 B3 OP29 Open Drain Output 29Open Drain Output 30 OP30 A4 B4 OP31 Open Drain Output 31Open Drain Output 32 OP32 A5 B5 OP33 Open Drain Output 33Open Drain Output 34 OP34 A6 B6 OP35 Open Drain Output 35Open Drain Output 36 OP36 A7 B7 OP37 Open Drain Output 37Open Drain Output 38 OP38 A8 B8 OP39 Open Drain Output 39Open Drain Output 40 OP40 A9 B9 OP41 Open Drain Output 41Open Drain Output 42 OP42 A10 B10 OP43 Open Drain Output 43Open Drain Output 44 OP44 A11 B11 OP45 Open Drain Output 45Open Drain Output 46 OP46 A12 B12 OP47 Open Drain Output 47
GND A13 B13 GNDInput 20 IP20 A14 B14 IP21 Input 21Input 22 IP22 A15 B15 IP23 Input 23Input 24 IP24 A16 B16 IP25 Input 25Input 26 IP26 A17 B17 IP27 Input 27Input 28 IP28 A18 B18 IP29 Input 29Input 30 IP30 A19 B19 IP31 Input 31
+12V A20 B20 +12V
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8.12 P8 Box Header – General I/O #1
Reference: P8Type: Header 40W Box HeaderDescription: General Purpose I/O #1
Open Drain Output 24 OP24 1 2 OP25 Open Drain Output 25Open Drain Output 26 OP26 3 4 OP27 Open Drain Output 27Open Drain Output 28 OP28 5 6 OP29 Open Drain Output 29Open Drain Output 30 OP30 7 8 OP31 Open Drain Output 31Open Drain Output 32 OP32 9 10 OP33 Open Drain Output 33Open Drain Output 34 OP34 11 12 OP35 Open Drain Output 35Open Drain Output 36 OP36 13 14 OP37 Open Drain Output 37Open Drain Output 38 OP38 15 16 OP39 Open Drain Output 39Open Drain Output 40 OP40 17 18 OP41 Open Drain Output 41Open Drain Output 42 OP42 19 20 OP43 Open Drain Output 43Open Drain Output 44 OP44 21 22 OP45 Open Drain Output 45Open Drain Output 46 OP46 23 24 OP47 Open Drain Output 47
GND 25 26 GNDInput 20 IP20 27 28 IP21 Input 21Input 22 IP22 29 30 IP23 Input 23Input 24 IP24 31 32 IP25 Input 25Input 26 IP26 33 34 IP27 Input 27Input 28 IP28 35 36 IP29 Input 29Input 30 IP30 37 38 IP31 Input 31
+12V 39 40 +12V
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8.13 P9 Ultrex – General I/O #2
Reference: P9Type: Header 34W AMP UltrexDescription: General Purpose I/O #2
Open drain Output 48 OP48 A1 B1 OP49 Open drain Output 49Open drain Output 50 OP50 A2 B2 OP51 Open drain Output 51Open drain Output 52 OP52 A3 B3 OP53 Open drain Output 53Open drain Output 54 OP54 A4 B4 OP55 Open drain Output 55Open drain Output 56 OP56 A5 B5 OP57 Open drain Output 57Open drain Output 58 OP58 A6 B6 OP59 Open drain Output 59Open drain Output 60 OP60 A7 B7 OP61 Open drain Output 61Open drain Output 62 OP62 A8 B8 OP63 Open drain Output 63
GND A9 B9 GNDInput 6 IP6 A10 B10 IP7 Input 7Input 8 IP8 A11 B11 IP9 Input 9Input 10 IP10 A12 B12 IP11 Input 11Input 12 IP12 A13 B13 IP13 Input 13Input 14 IP14 A14 B14 IP15 Input 15Input 16 IP16 A15 B15 IP17 Input 17Input 18 IP18 A16 B16 IP19 Input 19
+12V A17 B17 Vmeter Current Sensing +12V
8.14 P9 Box Header – General I/O #2
Reference: P9Type: Header 34W Box HeaderDescription: General Purpose I/O #2
Open drain Output 48 OP48 1 2 OP49 Open drain Output 49Open drain Output 50 OP50 3 4 OP51 Open drain Output 51Open drain Output 52 OP52 5 6 OP53 Open drain Output 53Open drain Output 54 OP54 7 8 OP55 Open drain Output 55Open drain Output 56 OP56 9 10 OP57 Open drain Output 57Open drain Output 58 OP58 11 12 OP59 Open drain Output 59Open drain Output 60 OP60 13 14 OP61 Open drain Output 61Open drain Output 62 OP62 15 16 OP63 Open drain Output 63
GND 17 18 GNDInput 6 IP6 19 20 IP7 Input 7Input 8 IP8 21 22 IP9 Input 9Input 10 IP10 23 24 IP11 Input 11Input 12 IP12 25 26 IP13 Input 13Input 14 IP14 27 28 IP15 Input 15Input 16 IP16 29 30 IP17 Input 17Input 18 IP18 31 32 IP19 Input 19
+12V 33 34 Vmeter Current Sensing +12V
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8.15 P10 – Loudspeakers
Reference: P10Type: Header 5W AMP MTA-100Description: Loudspeakers
1 LS1+ Loudspeaker, Channel 12 LS1- Loudspeaker, Channel 13 MIX Channel 2 mixer input4 LS2+ Loudspeaker, Channel 25 LS2- Loudspeaker, Channel 2
WARNING: Loudspeaker outputs are bridge driven and must NOT be connected ground.
8.16 P11 – Multiplex Expansion
Reference: P11Type: Header 7W AMP MTA-100Description: Multiplex Expansion
1 MPX1_DATA_A 12V CMOS Output2 MPX2_DATA_A 12V CMOS Output3 MPX_STR_A 12V CMOS Output4 MPX_STR_B 12V CMOS Output5 MPX_CLK 12V CMOS Output6 MPX_STR 12V CMOS Output7 MPX_OE 12V CMOS Output
8.17 P12 – Aux Outputs
Reference: P12Type: Header 8W AMP MTA-100Description: Aux. Outputs
1 GND2 AUX0 Open drain output, 150mA, 1K pull-up to +5V3 AUX1 Open drain output, 150mA, 1K pull-up to +5V4 AUX2 Open drain output, 150mA, 1K pull-up to +5V5 AUX3 Open drain output, 150mA, 1K pull-up to +5V6 AUX4 Open drain output, 150mA, 1K pull-up to +5V7 AUX5 Open drain output, 150mA, 1K pull-up to +5V8 +12V
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8.18 P13 – External I2C Bus
Reference: P13Type: Header 4W AMP MTA-100Description: External I2C Bus
1 GND2 AUX7/SDA I2C SDA line, TTL Open Collector I/O, 1K Pull-up3 AUX6/SCL I2C SCL line, TTL Open Collector I/O, 1K Pull-up4 +5V
8.19 P14 – IO Expansion Card Connector
Reference: P14Type: DIN41612, C/2 Vertical PlugDescription: Connector for IO Expansion Boards
c b a1 D8 PORTA0 HALT-2 D9 PORTA1 CLKOUT3 D10 PORTA2 CS3-4 D11 PORTA3 RESET-5 D12 PORTA4 BERR-6 D13 PORTA5 A207 D14 A22 A238 D15 AS- A49 RXDA- (TTL) DS- A510 TXDA- (TTL) R/W- A611 CTSA- (TTL) DSACK0- A712 RTSA- (TTL) DSACK1- +12V13 A0 SIZ0 VCC14 A1 SIZ1 VCC15 A2 PB5 GND16 A3 PB6 GND
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8.20 P15 – Memory Expansion Card Connector
Reference: P15Type: DIN41612, C/2 Socket VerticalDescription: Connector for Memory Expansion Boards
a b c1 A4 A5 A62 VCC A7 A83 VCC A9 A104 A3 A11 A125 A2 A13 A146 A1 A15 A167 GND A17 A188 GND A19 A20*9 FPGA0 A21 D1510 FPGA1 D14 D1311 FPGA2 D12 D1112 FPGA3 D10 D913 FPGA4 D8 D714 FPGA5 D6 D515 FPGA6 D1 D316 D0 D2 D4
* NB. - Pin c8, “A20” is in fact the connection to Pin 1 (ROM_P1) of the 2 on-board EPROMs, U1 &U2, and is driven by the FPGA.For all memory accesses, excluding those to the ROM/EPROM area mapped by CS0-, the FPGAroutes A20 to this pin.For all memory accesses to the ROM/EPROM area mapped by CS0-, the FPGA routes either Vcc,A19 or A20 to this pin, depending on the memory mode set in the FPGA.
See Section 5.6, “EPROM Sockets / EPROM Autoselect Feature” for details of operation.
8.21 P16 – Background Debug Mode Connector
Reference: P16Type: 10W Low Profile HeaderDescription: Background Debug Mode Connector
Only fitted to Software Development Boards
DS- 1 2 BERR-GND 3 4 BKPTGND 5 6 FREEZE
RESET- 7 8 IFETCHVCC 9 10 IPIPE
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Figure 1 - Schematic Sheet 1 - Root Sheet
LR[0..15]
PORTA[0..7]
TXDB
© HEBER LTD, 1996-2002
CS3-
SHT 3 - FPGA
15084_3
CS_OP-CS_IP-
R/W-SIZ0DSACK0-EXTAL3.68MHZCS0-CS1-CS2-CS3-CLKOUTDREQ1-DREQ2-
RAM_WL-RAM_WU-RAM_OE-
ROM_OE-ROM_P1
MPX_CLKMPX_STRMPX_OE
MPX1_DATA_AMPX2_DATA_A
MPX_STR_DATA_A
SFX1_VCKSFX_CLK
D[0 ..15]
A[0..23]
RESET
SFX1_D[0..3]SFX2_D[0..3]
SFX2_VCK
ROM_P12
CS_TTL-
FPGA[0..6]
OP[0..63]
RAM_CS-
DSACK1-MPX_REF1
VREF
A[0..23]
PORTA[0..7]
RXDA
SHT 6 - OPEN DRAIN OUTPUTS
15084_6
RESET-CS_OP-
D[0..15]OP[0..63]
A[0..23]SEL[0..2]
RESET-
NMI-
PB5
SHT 12 - LAMP ROW SOURCES
15084_C
CLK_12VSTR_12VOE_12V
MPX1_A_12V
MPX1_B_12VMPX1_C_12VMPX1_D_12V
LR[0..15]
BERR-
SFX1_D[0..3]
SHT 7 - INPUTS/DIL SW
15084_7
D[0..15]
CS_IP-
IP[0..31]
SEL[0..2]
CLKOUT
DS-
EXTAL
MPX_REF1
SFX_CLK
CS_IP-
RESET
TXDA
SFX_CLK
MPX2_DATA_A
PB6
RTSB-
DREQ1-
SHT 13 - LED SEG DRIVES
15084_D
MPX_CLKMPX_STRMPX_OEMPX1_DATA_A
CLK_12VSTR_12VOE_12VMPX1_A_12V
STR_A_12V SEG[0..15]
MPX1_B_12V
MPX1_C_12V
MPX1_D_12V
MPX_STR_DATA_AMPX2_DATA_A
SHT 11 - COL/DIG SINKS
15084_B
CLK_12VSTR_12VOE_12V
STR_A_12V
SEG[0..15]
LC[0..15]MPX_REF1MPX_REF2
CS_OP-
AS-VREF
FC3
TGATE2-
D[0..15]
RTSA- MPX_REF2
SFX2_VCK
MPX_CLK
CS3-
MPX_STR
RTSA-
SIZ1
RXDB
DREQ2-
RESET
SIZ0
TGATE2-PORTA[0..7]
AS-
D[0 ..15]
PB5
A[0..23]
TOUT2
3.68MHZ
MPX_OE
TGATE1-
CS_TTL-
PB0
POP4
MPX_STR_DATA_A
TXDA
PORTA[0..7]
CTSA-
DSACK0-
SHT 2 - MC68340 CPU
15084_2
R/W-SIZ0
DSACK0-EXTAL
3.68MHZCS0-CS1-CS2-CS3-
CLKOUTDREQ1-DREQ2-
D[0..15]
A[0..23]
METER_SENSENMI-
CTSA-RTSA-CTSB-RTSB-
PORTA[0..7]
SEL[0..2]
AS-DS-
DSACK1-SIZ1
FC3
PB5PB6
RXDA
RXDBTXDA
TXDB
TGATE1-TGATE2-
TOUT1TOUT2
POP4POP6
HALT-BERR-
RESET-PB0
PB6
METER_SENSE
CS0-
MPX1_DATA_A
D[0..15]
SIZ1
SHT 4 - EPROM/RAM
15084_4
D[0 ..15]
A[0..23]RAM_WL-RAM_WU-RAM_OE-
ROM_OE-ROM_P1
RAM_CS-
ROM_P12FPGA[0..6]
SHT 10 - RESET/BATT/RS232/I2C
15084_A
VREF
RAM_CS-
RESET
CTSA-RTSA-CTSB-RTSB-RXDATXDARXDBTXDBRESET-PB0
PORTA[0..7]
SEL[0..2]
SHT 5 - SOUND
15084_5
SFX_CLKSFX1_VCK
SFX1_D[0..3]
TOUT1POP6POP4
TOUT2SFX2_D[0..3]
SFX2_VCK
PORTA[0..7]
R/W-
D[0..15]
CS_OP-
CTSA-
CS1-
DSACK1-
A[0..23]
CS_IP-
RESET-
RESET-
R/W-
METER_SENSE
A[0..23]
CTSB-
MPX_REF2
IP[0..31]
FPGA[0..6]
RAM_CS-
POP6
TGATE1-
PORTA[0..7]
HALT-
LC[0..15]
DSACK0-
SHT 9 - CONNECTORS
15084_9
OP[0..63]
RESET-
TXDACTSA-RTSA-
IP[0..31]
AS-DS-R/W-DSACK0-DSACK1-SIZ0SIZ1
CS3-CLKOUT
RXDA
TGATE1-TGATE2-
PB5PB6
LC[0..15]
MPX1_B_12V
MPX1_D_12VMPX1_C_12V
LR[0..15]
BERR-HALT-
A[0..23]D[0..15]
PORTA[0..7]
CS_TTL-
RXDA
NMI-
SEG[0..15]
SHT 8 - +5V/CURRENT SENSE
15084_8
METER_SENSE
NMI-VREF
SFX_CLK
MPX_REF2MPX_REF1
PORTA[0..7]
HALT-
SIZ0
CS2-
56-15084 11r2
PLUTO 5 - ROOT SHEET
HEBER LTD.
Belvedere MillChalford, StroudGloucestershire GL6 8NTTel: 0453 886000 Fax: 0453 885013
A3
1 13Monday, August 11, 2003
Title
Size Document Number Rev
Date: Sheet of
CS_TTL-
DS-
CLKOUT
D[0 ..15]
SFX1_VCK
BERR-
TOUT1 SFX2_D[0..3]
Page 39
Document No. 80-15151 Issue 6 HEBER LTD
Figure 2 - Schematic Sheet 2 - CPU
D13
A8
U7F
74HC14
13 12
32.768KHz
16.77MHz
R103680R
RXDB
PORTA[0..7]
C23100n
VCC
TCK
BERR-
A14
A13
DREQ1-
D11
SW3
SW PUSHBUTTON
N10
3K3*8 SIL
123456789
D1
POP45
GND
D8
A16
RTSB-
D5
C28100n
A7TXDB10
3.68MHZ 3
TCK
A19
LD2
GREEN
RESET-10
TOUT25
R/W-3,9
PB5
D12
BGACK-
NMI-8
A6
A20
RXDA9,10
TOUT15
GND
POP4
PORTA1PORTA7
D15
VCC
TDI
SIZ0
PORTA0
N15
3K3*8 SIL
123456789
PUSHBUTTON
PB0
CS0-
3.68MHZ
VCC
A17
A19
TXDA
DS-9
PORTA4
DREQ2- 3
METER_SENSE8
SIZ19
A5
DONE2-
R45
3K3
A3
A11
A5
DSACK1-
A21
D[0..15] 3,4,6,7,9D5
D14 A22
PORTA3N16
3K3*8 SIL
123456789
D0
A8
VCC
BERR-PP2 PP
GND
GND
A12
PORTA[0..7] 5,8,9,10RTSA-
PORTA5
D7
PP25 PP
LD1
RED
VCC
BKPT
RESET-
A2PORTA2
A20
D3
GND
METER_SENSE
CS1-LED
A11
D11
PB7A10
N17
3K3*8 SIL
123456789
AS-
PP3 PP
DONE1-
CS3-
D6
A23
CTSA-9,10
RESET-
PORTA3
A[0..23] 3,4,6,9
C24
100n
AS-9
PORTA2
A13
R44
3K3
A2
HALT-9
IFETCH
VCC
HALT-
A4
VCC
BR-
TGATE1-9
AS-
RESET-
D4
C32100n
VCC
GND
DSACK0-
PB6
A0
CS3-3,9
D4
TXDB
D8
PP4 PP
R/W-
BGACK-
C26100n
RXDB10
EXTAL3
PB7
A7
VCC
A9
LC3EMC FILTER
1 3
2
DSACK1-9
BACKGROUND DEBUG
TP9PAD
N7
3K3*8 SIL
123456789
CONTROLLED
PB6
BR-
PP1 PP
PORTA4
P16
LOW PROFILE HDR 10WFITTED FOR DEV. ONLY
12345678910
D7
DREQ1-3
PP24 PP
GND
VCC
A12
PB69
GND
VCC
D10
CLKOUT
C29100n
VCC
BG-
A9
A15
POP6
PORTA3
D3
D2
PP5
PP
VCC
D12
TP10PAD
TXDA9,10
GND
RTSB-10
VCC
A0
R/W-
PORTA6
VCC
A1
A22
PORTA5
C30100n
A21
PORTA6
D10
D9
PB5
RXDA
D13
TP13PAD
CS0-3
© HEBER LTD, 1996-2002
D2
A17
A10
C27100n
GND
DS-
PORTA7
TP11PAD
A18
A15
CTSB-10PORTA0
D1
VCC
METER_SENSE
DONE1-
GND
D[0..15]
BKPT
D14
D6
A4
C31100n
D15
TOUT1
VCC
TDO
DONE2-
A16
FREEZE
HALT-
A3
GND
IPIPE
TP12PAD
PB010
IEEE 1149.1 ACCESS
CTSA-
TOUT2
A18
N11
3K3*8 SIL
123456789
CS2-3
CONNECTOR
ON-BOARD
PP23 PP
TGATE2-9
BERR-9
CTSB-
CS1-3
PB5
VCC
PORTA2
SIZ03,9
VCC
A6
PORTA1
N9
3K3*8 SIL
123456789
BERR-
DREQ2-
VCC
GND
DS-
EXTAL
A[0..23]
D9
DSACK0-3,9
A14
RESET LED
SOFTWARE
56-15084 11r2
PLUTO 5 - CPU
HEBER LTD.
Belvedere MillChalford, Stroud, GL6 8NTTel: +44 (0) 1453 886000Fax: +44 (0) 1453 885013
A3
2 13Tuesday , August 12, 2003
Title
Size Document Number Rev
Date: Sheet of
VCC
U5
MC68340PV
144143142141
125124
1133738
48
63646566
123122121120117116115114
69707172
103104107105106
112111
999897
100101102108
87234589
10
1
33322829
2726
25242223
138137136135134133132131128126
39424344454647
515253555657606162
7 19 31 41 50 59 68 74 86 92 94 110
119
130
140
78 77 76 75 83 82 85 84
353436
808179
161514
131211
95
91
89
17
20
2190
93 6 18 30 40 49 54 58 67 73 88 96 109
118
127
129
139
D0D1D2D3
D14D15
A0A1A2
A10
A20A21A22A23
A24/PA0A25/PA1/IACK1A26/PA2/IACK2A27/PA3/IACK3A28/PA4/IACK4A29/PA5/IACK5A30/PA6/IACK6A31/PA7/IACK7
FC0FC1FC2FC3
ASDSR/WSIZ0SIZ1
DSACK0DSACK1
BERRHALTRESET
BRBGBGACKRMC
MODCK/PB0CS1/IRQ1/PB1CS2/IRQ2/PB2IRQ3/PB3CS3/IRQ4/PB4IRQ5/PB5IRQ6/PB6IRQ7/PB7
CS0/AVEC
RXDATXDACTSARTSA/OP0
RXRDYA/OP4TXRDYA/OP6
RXDBTXDBCTSBRTSB/OP1
D4D5D6D7D8D9
D10D11D12D13
A3A4A5A6A7A8A9
A11A12A13A14A15A16A17A18A19
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
TC
KTM
STD
ITD
O
BKPT
FR
EEZE
IPIP
EIF
ETC
H
TOUT2TIN2TGATE2
TOUT1TIN1TGATE1
DREQ1DACK1DONE1
DREQ2DACK2DONE2
CLKOUT
EXTAL
XTAL
X1
X2
SCLKVCCSYN
XFC
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
POP65
VCC
A1
D0
N8
3K3*8 SIL
123456789
CLKOUT3,9
GND
SIZ1
A23
R102680R
RESET-
C25100n
VCC
VCC
CS2-
RTSA-9,10
VCC
TMS
PB0
Page 40
Document No. 80-15151 Issue 6 HEBER LTD
Figure 3 - Schematic Sheet 3 - FPGA
ROM_P12
D[0..15]2,4,6,7,9
FPGA[0..6] 4
FPGA5FPGA4
GND
FPGA2
A21
SFX1_D0
ROM_OE- 4
MPX_OE 13
SFX2_VCK 5
X1
14.7456MHz
SFX1_D3
GND
SFX1_D[0..3]
N14
3K3*8 SIL
123456789
SFX1_D1
D11
VCC
D9
MPX_STR 13
SFX_CLK5,8
ROM_P12 4
CS_TTL- 9
A6
U6
FPGA
121314151617181920212223242526272829303132
747372717069686766656463626160595857565554
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75
NCI/OI/OI/OI/OI/OGNDGNDI/OI/OI/OI/OI/OVCCVCCI/OI/OI/OI/OI/OI/O
I/OI/OI/OI/OI/OI/O
VCCVCC
MODEI/O
I/O(CLK)I/OI/O
GNDGND
I/OI/OI/OI/OI/OI/O
VCC
I/O I/O I/O I/O I/O I/O GN
DI/O I/O I/O I/O I/O VC
CI/O I/O I/O I/O I/O I/O I/O
I/O I/O I/O I/O I/O I/O I/OVC
C I/O I/O I/O I/O I/OG
ND I/O I/O I/O I/O I/O I/O I/O
FPGA2
R105
680R
CS_OP- 6
A[0..23]
RAM_OE- 4
SIZ02
FPGA6
GND
VCC
MPX2_DATA_A 13
FPGA0
A5
SFX2_D[0..3]
RAM_WL- 4
VCC
FPGA4
RAM_WU- 4
DREQ2-2
R/W-2
A0
C35100n
A1
SFX2_D3
R104
10M
CS2-2
DREQ1-2
GND
GND
A3
56-15084 11r2
PLUTO 5 - FPGA
HEBER LTD.
Belvedere MillChalford, Stroud, GL6 8NTTel: +44 (0) 1453 886000Fax: +44 (0) 1453 885013
A3
3 13Tuesday , August 12, 2003
Title
Size Document Number Rev
Date: Sheet of
VCC
FPGA0
A23
CS0-2
MPX_CLK 13
GND
SFX2_D0
SFX1_VCK5
RESET10
SFX1_D[0..3]
SFX2_D1
GND
VCC
FPGA3
VCC
GND
FPGA1
VCC
SFX2_D2
FPGA[0..6]
A7
GND
MPX1_DATA_A 133.68MHZ2
C3733p
A2
SFX1_D2
C33100n
A4
D8
D[0..15]
FPGA5
FPGA1D15
A20
CS_IP- 7
FPGA3
CS1-2
GND
CLKOUT2
EXTAL2
© HEBER LTD, 1996-2002
A19
D13
C36100n
CS3-2
GND
FPGA6
A22
GND
SFX2_VCK
D14
C34100n
MPX_STR_DATA_A 13
GND
D12
ROM_P1 4
D10
A[0..23]2
VCC
C3833p
VCCVCC
CS_TTL-
DSACK0-2,9
SFX2_D[0..3]
VCC
Page 41
Document No. 80-15151 Issue 6 HEBER LTD
Figure 4 - Schematic Sheet 4 - Memory
ROM_P1
D9
U4
HM62256BLFP
109876543
25242123
226
1
272022
1112131516171819
1428
A0A1A2A3A4A5A6A7A8A9A10A11A12A13A14
WRCEOE
O0O1O2O3O4O5O6O7
GN
DVD
D
RAM_CS-10
OUT
A5
D12
D[0..15]
VCC
D5
A9
U2
EPROM
121110
98765
27262325
42829
32
3031
2422
32
1314151718192021
16
1
A0A1A2A3A4A5A6A7A8A9A10A11A12A13A14A15A16A17A18
OECE
VCC
D0D1D2D3D4D5D6D7
GND
VPP
A17
CS0-
56-15084 11r2
PLUTO 5 - MEMORY
HEBER LTD.
Belvedere MillChalford, Stroud, GL6 8NTTel: +44 (0) 1453 886000Fax: +44 (0) 1453 885013
A3
4 13Tuesday , August 12, 2003
Title
Size Document Number Rev
Date: Sheet of
VCC
A2
D4
D7
A9
MEM_CARD_PRESENT-
A1
0
D15
D13
FPGA0
A15
ROM_OE-
D9
P15B
DIN41612-48WTYPE "C/2" VERT SKT
B1
B3B4
B2
B5B6B7B8B9
B10B11B12B13B14B15B16
B1
B3B4
B2
B5B6B7B8B9B10B11B12B13B14B15B16
D8
P15C
DIN41612-48WTYPE "C/2" VERT SKT
C1
C3C4
C2
C5C6C7C8C9
C10C11C12C13C14C15C16
C1
C3C4
C2
C5C6C7C8C9C10C11C12C13C14C15C16
RAM_CS-10
VBATT
D0
OUT
U3
HM62256BLFP
109876543
25242123
226
1
272022
1112131516171819
1428
A0A1A2A3A4A5A6A7A8A9A10A11A12A13A14
WRCEOE
O0O1O2O3O4O5O6O7
GN
DVD
D
D1
A10
D2
U1
EPROM
121110
98765
27262325
42829
32
3031
2422
32
1314151718192021
16
1
A0A1A2A3A4A5A6A7A8A9A10A11A12A13A14A15A16A17A18
OECE
VCC
D0D1D2D3D4D5D6D7
GND
VPP
D6
A9
A14
FPGA1
GND
D14
----------------------------------- MEMORY EXPANSION CONNECTOR ----------------------------------------
A8
D[0 ..15]2,3,6,7,9
1
A3
A6
A13
RAM_WU-3
A7
A1
A10
1
ROM_OE-
A20
A13
D10
A11
A18
OUT
GND
FPGA4
READ 2*27C040
GND
A9
ROM_MAP_2
D12
A7
ROM_P13
ROM_MAP_1
A20
D8
D11
A14A14
A17
FPGA3
GND
A13
D7
A19
A4
NAME
A10
A4
A10
A14
0 A0
OUT
D4
A12
D15
OUT
A10
A19
C22100n
RAM_OE-3
FPGA[0..6]
P15A
DIN41612-48WTYPE "C/2" VERT SKT
A1
A3A4
A2
A5A6A7A8A9
A10A11A12A13A14A15A16
A1
A3A4
A2
A5A6A7A8A9A10A11A12A13A14A15A16
READ 1*27C801
D9
A4
D14
D5FPGA5
GND
A13
A18
ROM_OE-3
GND
FPGA1
A0
FPGA2
A4
A16
D3
GND
D15
A11
A5
D[0..15]
x
A2
A6
A1
OUT
A21
FPGA5
C21100n
A12
D14
VCC
D2
PINS 1,12 SET BY FPGA
A16
D11
A0/A19
A[0..23]
FUNCTION
READ 1*27C040
D10
LINES FPGA0-6 HAVE THE FOLLOWING DEFAULT FUNCTIONSA3
VBATT
GND
D11
1
GND
D5
A6
RAM_WL-3
A[0..23]2
D0
D2
A8
A11
A15
WU- (WRITE HIGH BYTE)
A3
A15
FPGA[0..6]3
GND
U3/U4 - 32K*8 STATIC RAMS, SOP
FPGA6
MODE
© HEBER LTD, 1996-2002
A15
VCC0
ROM_P1
A4
A11
A1
A15
EPROMS - 2*27C040 OR 2*27C801
NON-ROM CYCLE
D3
A1
A7
A8
A11
A7
D3
A7
A16
A5
FPGA2
A[0..23]2
A5
D7
A3
D13
A12
FPGA4
VBATT
A18
D10
ROM_P12
A12
A3
A17
D13
FPGA0
FPGA6
ROM_P12
A14
ROM_P1
D8
C19100n
(A20)
VCC
D0
0
D12
D6
RAM_CS- (CS- FOR EXPANSION RAM)A22
ROM_P13
A2
FPGA3WL- (WRITE LOW BYTE)
C20100n
GND
D1
A12
A5
ROM_P1
ROM_P123
I/O
VCC
A19
A6
A2
RAM_OE-3
RESET
A6
A9
D[0..15]2,3,6,7,9
VCC
A8
IN
VBATT
A2
A8
READ 2*27C801
D6
ROM_OE-3
A19
A13
D1D4
A[0..23]
Page 42
Document No. 80-15151 Issue 6 HEBER LTD
Figure 5 - Schematic Sheet 5 - Sound
PORTA0
C39
100nSFX1_D[0..3]
+12V
SFX_CLK3
R1093K3
R11147K 2%
SFX_CLK
SFX1_S2
SFX2_D0GND
56-15084 11r2
PLUTO 5 - SOUND
HEBER LTD.
Belvedere MillChalford, Stroud, GL6 8NTTel: +44 (0) 1453 886000Fax: +44 (0) 1453 885013
A3
5 13Tuesday , August 12, 2003
Title
Size Document Number Rev
Date: Sheet of
C451/50
R11222K
PORTA[0..7]2,8,9,10
LS CONNECTOR
LS2-
GND
PORTA6
GND
C461/50
SFX2_S2
GND
POP4
U39
MSM6585
4567
12
15
121338
189
16
17 14
10
11
D0D1D2D3
S1S2
RESET
T1T2T3T4
VDD
GN
D
XT
XT VCK
AOUT
DAO
SAMPLED SOUND CHANNEL #1
POP42
SFX2_VCK
C4410n
LS2+
SFX1_D3
GND
SFX1_VCK
SFX2_D1
GND
R13122K
C50
220/16
TOUT1 2
PORTA[0..7]SFX1_S1
LS1+
SFX_CLK
GND
R108
3K3
PORTA7
R1133K3
POP62
C47
1/50
GND
R129
22K
PORTA[0..7]
SFX2_D[0..3]
GND
R110
3K3
SFX1_VCK3
SFX2_D[0..3]
PORTA1
POP6
C5110n
C48
1/50
PP6
PP
C43
100n
C49
1/50
© HEBER LTD, 1996-2002
SFX2_D2
LS1-
C40
100n
SFX2_S1
CH2_MIX
SFX1_D1
SFX_CLK3
GND
P10
HDR 5W AMP MTA-100
12345
R13047K 2%
GND
PP7
PP
SAMPLED SOUND CHANNEL #2
SFX2_VCK3
VCC
U8
MSM6585
4567
12
15
121338
189
16
17 14
10
11
D0D1D2D3
S1S2
RESET
T1T2T3T4
VDD
GN
D
XT
XT VCK
AOUT
DAO
SFX1_D[0..3]
SFX2_D3
TOUT2 2
+
-
+
-
+
U32
TDA7057AQ
4
13
11
8
10
3
1
5
7
129 6
VCC
SFX1_D0
SFX1_D2
Page 43
Document No. 80-15151 Issue 6 HEBER LTD
Figure 6 - Schematic Sheet 6 - Outputs
GND
SEL2
U27
TPIC6259
18 45
3 68 7
12 1415
13 1619 17
11011209
2
D Q0Q1
S0 Q2S1 Q3S2 Q4
Q5G Q6CLR Q7
PGNDPGNDPGNDPGNDGND
VCC
GND
GND
OP4
RESET-10
D7
© HEBER LTD, 1996-2002
SEL1
GND
OP52
SEL0
SEL[0..2] 7
GND
OP12
SEL1
OP61
OP25
D6
U25
TPIC6259
18 45
3 68 7
12 1415
13 1619 17
11011209
2
D Q0Q1
S0 Q2S1 Q3S2 Q4
Q5G Q6CLR Q7
PGNDPGNDPGNDPGNDGND
VCC
OP[0..63] 9
GND
GND
SEL0
SEL1
OP42
OP59
OP11
VCC
OP19
56-15084 11r2
PLUTO 5 - OUTPUTS
HEBER LTD.
Belvedere MillChalford, Stroud, GL6 8NTTel: +44 (0) 1453 886000Fax: +44 (0) 1453 885013
A3
6 13Tuesday , August 12, 2003
Title
Size Document Number Rev
Date: Sheet of
OP43
U22
TPIC6259
18 45
3 68 7
12 1415
13 1619 17
11011209
2
D Q0Q1
S0 Q2S1 Q3S2 Q4
Q5G Q6CLR Q7
PGNDPGNDPGNDPGNDGND
VCC
SEL1
A[0..23]
GND
OP35
GND
OP2
GND
SEL2
C4100n
D4
OP36
SEL2
GND
OP49
GND
GND
D3
OP39
C3100n
U7C
74HC14
5 6
GND
OP57
SEL1
OP50SEL0
VCC
SEL0
OP46
OP29
OP14
U7A
74HC14
1 2
GND
GND
OP10
OP60
OP16
OP26
GND
SEL2
OP6
GND
U24
TPIC6259
18 45
3 68 7
12 1415
13 1619 17
11011209
2
D Q0Q1
S0 Q2S1 Q3S2 Q4
Q5G Q6CLR Q7
PGNDPGNDPGNDPGNDGND
VCC
SEL2
OP45
VCC
OP5
SEL0
VCC
OP20
SEL1
A3
GND
GND
GND
OP17
OP22
SEL0
OP44
OP7
OP28
OP41
GND
OP8
SEL2
GND
D1
SEL2
OP40
VCC
A[0..23]2
VCC
GND
OP21
OP[0..63]
VCC
D2
OP18
OP55
SEL1
U23
TPIC6259
18 45
3 68 7
12 1415
13 1619 17
11011209
2
D Q0Q1
S0 Q2S1 Q3S2 Q4
Q5G Q6CLR Q7
PGNDPGNDPGNDPGNDGND
VCC
GND
U26
TPIC6259
18 45
3 68 7
12 1415
13 1619 17
11011209
2
D Q0Q1
S0 Q2S1 Q3S2 Q4
Q5G Q6CLR Q7
PGNDPGNDPGNDPGNDGND
VCCGND
D[0..15]2,3,4,7,9
GND
OP58
SEL0
GND
OP62
OP31
OP9
OP30
OP51
OP32
OP27
U29
TPIC6259
18 45
3 68 7
12 1415
13 1619 17
11011209
2
D Q0Q1
S0 Q2S1 Q3S2 Q4
Q5G Q6CLR Q7
PGNDPGNDPGNDPGNDGND
VCC
GND
OP0
GND
SEL1
OP38
D[0..15]
CS_OP-3
GND
GND
D5
OP1
D0
GND
A2
GND
GND
SEL2
A1
OP3
OP24
OP53
OP54
VCC
OP33
SEL2
GND
GND
GND
U7B
74HC14
3 4
VCC
SEL1
OP13
SEL[0..2]
VCC
GND
OP56
OP15OP23
U28
TPIC6259
18 45
3 68 7
12 1415
13 1619 17
11011209
2
D Q0Q1
S0 Q2S1 Q3S2 Q4
Q5G Q6CLR Q7
PGNDPGNDPGNDPGNDGND
VCC
GND
OP63
GND
C1100n
GND
OP47
VCC
OP48
SEL0
VCC
GND
OP34
GND
SEL0 OP37
C2100n
Page 44
Document No. 80-15151 Issue 6 HEBER LTD
Figure 7 - Schematic Sheet 7 - Inputs
R19
47K 2%
D0
SEL0
IP2
N33K3*8 SIL
123456789
U14
74HC253
67543
109111213
142115
1C01Y1C11C21C3
2C02Y2C12C22C3
AB
1G2G
VCC
R30
47K 2%
IP10
IP31
R7
47K 2%
R21
47K 2%
R11
47K 2%
R20
47K 2%
SW1
8W DIL SW
12345678
161514131211109
N123K3*8 SIL
12 3 4 5 6 7 8 9
IP9
SEL1
IP30
D8
56-15084 11r2
PLUTO 5 - INPUTS
HEBER LTD.
Belvedere MillChalford, Stroud, GL6 8NTTel: +44 (0) 1453 886000Fax: +44 (0) 1453 885013
A3
7 13Tuesday , August 12, 2003
Title
Size Document Number Rev
Date: Sheet of
D3
IP8
SEL1
GND
SEL0
U12
74HC253
67543
109111213
142115
1C01Y1C11C21C3
2C02Y2C12C22C3
AB
1G2G
GND
IP28
VCC
R12
47K 2%
R23
47K 2%
R1
47K 2%
IP29
R14
47K 2%
R27
47K 2%
D10
CS_IP-3
IP26
IP22
IP6
SEL1
R8
47K 2%
SEL1
R22
47K 2%
U13
74HC253
67543
109111213
142115
1C01Y1C11C21C3
2C02Y2C12C22C3
AB
1G2G
IP20
VCC
GND
IP12
R25
47K 2%R28
47K 2%
IP21
IP[0..31] 9
VCC
D4
GND
R31
47K 2%
D2
R32
47K 2%
N43K3*8 SIL
123456789
D6
D[0 ..15]
R24
47K 2%
R2
47K 2%
SEL0
R26
47K 2%
VCC
IP27
IP4
D1
IP13
N23K3*8 SIL
123456789
IP7
R9
47K 2%
N13K3*8 SIL
123456789
R4
47K 2%
IP0
IP19
D11
IP15
N133K3*8 SIL
12 3 4 5 6 7 8 9
SW2
8W DIL SW
12345678
161514131211109
IP23D7
SEL0
IP11
D5
© HEBER LTD, 1996-2002
D9
VCC
IP18
D[0 ..15]2,3,4,6,9
R29
47K 2%
IP16
IP5
U11
74HC253
67543
109111213
142115
1C01Y1C11C21C3
2C02Y2C12C22C3
AB
1G2G
SEL[0..2]
R6
47K 2%
R15
47K 2%
U9
74HC253
67543
109111213
142115
1C01Y1C11C21C3
2C02Y2C12C22C3
AB
1G2G
VCC
IP[0..31]
IP25
IP14
R18
47K 2%
SEL1
U10
74HC253
67543
109111213
142115
1C01Y1C11C21C3
2C02Y2C12C22C3
AB
1G2G
VCC
C5100n
SEL0
R16
47K 2%
IP24
NOTE: SEL0-2 ARE INVERTED A1-3
SEL[0..2]6
IP17
IP1
IP3
R10
47K 2%
C6100n
SEL1
R5
47K 2%
R3
47K 2%
R13
47K 2%
R17
47K 2%
SEL0
Page 45
Document No. 80-15151 Issue 6 HEBER LTD
Figure 8 - Schematic Sheet 8 - Power Supply
+12V_IN
F1
3.15A F 20*5MM
R3422K
GND
GND
VCC
METER_SENSE2
TP6PAD
PP12
PP SENSE
PP8
PP
R3547K 2%
-12V
© HEBER LTD, 1996-200256-15084 11r2
PLUTO 5 - POWER SUPPLY
HEBER LTD.
Belvedere MillChalford, Stroud, GL6 8NTTel: +44 (0) 1453 886000Fax: +44 (0) 1453 885013
A3
8 13Tuesday , August 12, 2003
Title
Size Document Number Rev
Date: Sheet of
R1251K
D3SA15
U15LM7805VI
GN
D
VO
TP7PAD
VMETER+
GND
PP9
PP
VCC
R36
47K 2%
GND
R126120R
TP8PAD
VMOT+
MPX_REF2
PP11
PP
Threshold 2 - Lamp short cct.
REGULATED +5V
GND
+12V
R3747K 2%
C947p
GND
+12V
R404K7
PP10
PP
+
-
U16D
LM339
11
1013
MPX_REF1
R40 revisions:3k3 -> 10k Feb 199810k -> 4k7 Jul 2003
PORTA[0..7]
MPX_REF1 11
VMPX+VCC
D20SA15
MPX_REF2 11
C1047p
VSS
LC1EMC FILTER
1 3
2
PP13
PP
METER DETECTION
R12447K 2%
R3847K 2%
R3347R
D21
1N4148
POWER FAIL DETECTION
P3
HDR 6W AMP MTA-156
123456
C71/50
SFX_CLK 3
+
-
U16C
LM339
9
814
VREF 10
GND
+12V_IN
MPX CURRENT
+12V
Threshold 1 - Lamp present
TP5PAD
METER_SENSE
GND
C81/50
VCC
GND
PORTA7
R3947K 2%
GND
PORTA6
MPX_GND
GND+
-
U16A
LM339
5
42
312
POWER IN
D2SA5
PORTA[0..7]2,5,9,10
+12V_IN
NMI-2
+12V
GND
SFX_CLK
+12V
LC2EMC FILTER
1 3
2
D1UF4002
R127
22K
+
-
U16B
LM339
7
61
MPX_GND
-12V
GND
Page 46
Document No. 80-15151 Issue 6 HEBER LTD
Figure 9 - Schematic Sheet 9 – IO Connectors
GND OP0
A23
GND
VMOT+
OP11
IP1
PB5
A[0..23]
REELS
RTSA-
IP27
OP54
OP16
I
CS_TTL-
IP15
IP4
PORTA4
P14A
DIN41612-48WTYPE "R/2" VERT MALE
A1
A3A4
A2
A5A6A7A8A9
A10A11A12A13A14A15A16
A1
A3A4
A2
A5A6A7A8A9A10A11A12A13A14A15A16
R107
22K
D15
GND
LR[0..15]
I/O EXP.
LC0
IP7
A7
BERR-2
OP30
OP1
OP63
RXDAA6
+12V
DSACK1-2
OP58
IP14
AS-
OP25
IP26
LR2OP48
P12
HDR 8W AMP MTA-100
12345678
56-15084 11r2
PLUTO 5 - CONNECTORS
HEBER LTD.
Belvedere MillChalford, Stroud, GL6 8NTTel: +44 (0) 1453 886000Fax: +44 (0) 1453 885013
A3
9 13Tuesday , August 12, 2003
Title
Size Document Number Rev
Date: Sheet of
IP31
CLKOUT
U7E
74HC14
1110
OP40
LR5
+12V
LC1
VMOT+
IP21
TXDA
LC[0..15]
GND
OP56
P8
HDR 40W
A1A2A3A4A5A6A7A8A9
A10A11A12
B1B2B3B4B5B6B7B8B9B10B11B12B13A13
A14A15A16
B14B15B16
A17 B17A18A19A20
B18B19B20
A1A2A3A4A5A6A7A8A9A10A11A12
B1B2B3B4B5B6B7B8B9
B10B11B12B13A13
A14A15A16
B14B15B16
A17 B17A18A19A20
B18B19B20
IP16
CS3-
OP34
IP11
OP62
GND
A1
I/O 1
LC3
IP2
OP[0..63]
LC4EMC FILTER
13
2
R106
22K
VCC
OP26OP28
OP43
OP9
PORTA1
R/W-
OP41
OP7
D9
IP22
OP57
VCC
VMOT+
IP23
P14B
DIN41612-48WTYPE "R/2" VERT MALE
B1
B3B4
B2
B5B6B7B8B9
B10B11B12B13B14B15B16
B1
B3B4
B2
B5B6B7B8B9B10B11B12B13B14B15B16
OP21
PP17
PP
OP35
IP8
IP0
PP16
PP
GND
IP20
IP10
VMOT+
P9
HDR 34W
A1A2A3A4A5A6A7A8A9
A10A11A12
B1B2B3B4B5B6B7B8B9B10B11B12B13A13
A14A15A16
B14B15B16
A17 B17
A1A2A3A4A5A6A7A8A9A10A11A12
B1B2B3B4B5B6B7B8B9
B10B11B12B13A13
A14A15A16
B14B15B16
A17 B17
OP23
PORTA5
D[0..15]
LC4
OP60
LR[0..15]12
OP24
OP45
OP13
OP42
OP4
PORTA0
R/W-2
CS3-2
GND
GND
A0
IP30
OP2
PP14
PP
OP51
IP13
A20
OP6
IP9
SIZ1
C
VMOT+
OP36
OP12
CTSA-2,10
PORTA3
AS-2
OP33
OP10
D[0 ..15]2,3,4,6,7
IP[0..31]7
TXDA2
D12
SIZ02
OP19
D8
LR4
OP3
GND
OP32
IP24
IP29
BERR-
A5
DSACK0-2,3
CS_TTL-3
IP12
PORTA2
U7D
74HC14
98
DS-2
GND
VCC
OP31
OP18
IP5
HALT-2
GND
OP29
A4
N201K0*8 SIL
12 3 4 5 6 7 8 9
HALT-
LC5EMC FILTER
1 3
2
RESET-10
LR1
DS-
A3
D8
IP25
IP28
P14C
DIN41612-48WTYPE "R/2" VERT MALE
C1
C3C4
C2
C5C6C7C8C9
C10C11C12C13C14C15C16
C1
C3C4
C2
C5C6C7C8C9C10C11C12C13C14C15C16
LC5
OP17
D10
GND
IP6
IP19
RTSA-2
GND
LC2
IP3
P13
HDR 4W AMP MTA-100
1234
RESET-
A[0..23]2
OP37
OP52
LC[0..15]11
+12V
OP46
OP8
A1
PP15
PP
TGATE1-2
OP22
CTSA-
VCC
OP44
D11
P7
HDR 50W
A1A2A3A4A5A6A7A8A9
A10A11A12
B1B2B3B4B5B6B7B8B9B10B11B12B13A13
A14A15A16
B14B15B16
A17 B17A18A19A20
B18B19B20
A21A22A23A24A25
B21B22B23B24B25
A1A2A3A4A5A6A7A8A9A10A11A12
B1B2B3B4B5B6B7B8B9
B10B11B12B13A13
A14A15A16
B14B15B16
A17 B17A18A19A20
B18B19B20
A21A22A23A24A25
B21B22B23B24B25
+12V
VMOT+
OP50
SDA
OP14
PB6
2
OP27
SCL
OP15
OP59
A2
IP[0..31]
PB62
LR0
IP18
SIZ0
VMETER+
D13
I/O 2
GND
GND
PORTA[0..7]2,5,8,10
OP38
D14
OP47
OP53
Heber Ltd. 1999
OP[0..63]6
VCC
LR3
IP17
A0
U30
TPIC6B259
18 45
3 68 7
12 1415
13 1619 17
11011209
2
D Q0Q1
S0 Q2S1 Q3S2 Q4
Q5G Q6CLR Q7
PGNDPGNDPGNDPGNDGND
VCC
TGATE2-2
© HEBER LTD, 1996-2002
CLKOUT2
OP49
+12V
A2
RESET-
PB52,10
OP20
A22
DSACK0-RXDA2,10
TTL I/O
OP61
DSACK1-VCC
OP39
PORTA[0..7]
GND
OP55
OP5
SIZ12
Page 47
Document No. 80-15151 Issue 6 HEBER LTD
Figure 10 - Schematic Sheet 10 - Reset/Battery/RS232
GND
PP19
PP
BATTERY BACK-UP
VCC
Q2FMMT717
SM
C12100n
BT12.4V NiMH
P1
HDR 6W AMP MTA-100
123456
DATAPORT
TP14PAD
RXDB2
POWER-ON RESET
GND
TXDA2,9
PORTA[0..7]
SCL
GND
PORTA5
Q12N7002
VCC
GND
RESET-
VREF8
VCC
R433K3
R114
3K3
R423K3
TP15PAD
VBATT
SDA
U17
TL7705
84
7
2
3
5
6
1
VCC
GN
D
SENSE
RESIN
CT
RESET
RESET
REF
GND
+12V
R413K3
P2
25W D SOCKET
1325122411231022
921
820
719
618
517
416
315
214
1
TXDB2
GND
TP16PAD
56-15084 11r2
PLUTO 5 - RESET/BATTERY/RS232
HEBER LTD.
Belvedere MillChalford, Stroud, GL6 8NTTel: +44 (0) 1453 886000Fax: +44 (0) 1453 885013
A3
10 13Tuesday , August 12, 2003
Title
Size Document Number Rev
Date: Sheet of
GND
EEPROM
C5222p
R115
3K3
-12V
VBATT
R132
3K3
RTSB-2
CTSA-2,9
(PORT A)
VCC
© HEBER LTD, 1996-2002
U40
PCF8583
1234
8765
OSCIOSCOA0GND
VDDINT
SCLSDA
RESET3 PB0 2
+12V
RESET
RTSA-2
INTERNAL I2C BUS
R160
120RR161
120R
VCC
U38
1489
147
1
4
10
13
3
6
8
11
VCC
GN
D
RXA
RXB
RXC
RXD
A
B
C
D
PORTA[0..7] 2,5,8,9
GND
PORTA4
X232Khz
RESIN-
PP18
PP
GND
U37
24C04/24C08
1234
8765
A0A1A2GND
VCCTSTSCLSDA
VCC
U33
1488
32
45
910
1213
6
8
11
7
14 1
TXAA1
B1B2
C1C2
D1D2
TXB
TXC
TXD
GN
D
V+ V-
RESET-
GND
VCC
VCC
C13100n
+12V
C53100n
RTC
-12V
GND
RXDA2,9
RS232C111/50
RAM_CS- 4
CTSB-2
VCC
GND
C14220/16
(PORT B)
GND
RESET-2,6,9
GND
Page 48
Document No. 80-15151 Issue 6 HEBER LTD
Figure 11 - Schematic Sheet 11 - Lamp Column/LED Digit Drives
SEG10
DIG2
LC8
DIG11
SEG12
*
DIG3
R101
680R
Q47BUK552
Q48BUK552
LC0
LC8
LC15
D11UF4002
*
LC3
DIG9
*
LC12
SEG9
LC4
DIG5
MPX_GND
LC3
LC10
LC13
D14UF4002
LC15
P4
HDR 18W AMP MTA-100
123456789
101112131415161718
D10UF4002
*
MPX_REF1
D12UF4002
56-15084 11r2
PLUTO 5 - LAMP COLUMN/LED DIGIT DRIVES
HEBER LTD.
Belvedere MillChalford, Stroud, GL6 8NTTel: +44 (0) 1453 886000Fax: +44 (0) 1453 885013
A3
11 13Tuesday , August 12, 2003
Title
Size Document Number Rev
Date: Sheet of
*
LC1
LC14
Q35BUK552
THESE COMPONENTS OMITTED
LC5
OR 14 SEG LED DRIVE (16 DIGIT)
LC5*
SEG8
R100
680R
C17100n
Q50BUK552
LC9
LC6
DIG4
OE_12V13
or HDR 34W BOX HEADER(Pins 33/34 - no connection)
DIG12
CLK_12V13
Q49BUK552
*
N183K3*8 SIL
12 3 4 5 6 7 8 9
LC10
STR_A_12V13
LAMP COLUMNS(SINKS)
Q36BUK552
GND
LC5
DIG13
*
DIG15
LC[0..15] 9
*
LC6
D18UF4002
SEG7
*
R120
680R
*
LC9
R96
680R
U20
4094
123
15
456714131211
9108
16
STRDCLKOE
Q1Q2Q3Q4Q5Q6Q7Q8
QSQSGND
VDD
LC8
DIG6
© HEBER LTD, 1996-2002
DIG5
N193K3*8 SIL
12 3 4 5 6 7 8 9
*
LC1
LC12
D16UF4002
SEG[0..15]
R121
680R
D5UF4002
SEG2
*
DIG7
LC7
SEG5
R117
680R*
GND
SEG6
R97
680R
*
*
DIG1
DIG0
SEG14
U21
4094
123
15
456714131211
9108
16
STRDCLKOE
Q1Q2Q3Q4Q5Q6Q7Q8
QSQSGND
VDD
DIG11
SEG0
D19UF4002
DIG8
Rsense24 milliohmsCopper Track
LC3
Q43BUK552
DIG12
D4-D19 Changed from 1N4005 to UF4002March, 2003
Q44BUK552
LC0
R118
680R
R119
680R
LC10
Q42BUK552
DIG7
DIG13
DIG14
DIG0
DIG4
*
*
LC6
DIG1
Q37BUK552
D4UF4002
R98
680R
MPX_REF1 8
D8UF4002
+12V
C18100n
D15UF4002
LC7
DIG10
D7UF4002
+12v
DIG3
LC7R122
680R
D6UF4002
LC4
MPX_REF2
R94
680R
*
*
*
LC2
DIG2
DIG[0..15]
DIG8
DIG10
MPX_REF2 8
LC9
R99
680R
7 SEG LED DRIVE (32 DIGIT)
LC4
LC14
D13UF4002
(DRIVE FOR LC8-15/DIG8-15)
GND
Q45BUK552
LC12
*
LC0
LC13
R123
680R
Q41BUK552
DIG6
R95
680R
*
GND
LC11
SEG3
SEG15
Q39BUK552
LC11
DIG14
LC13D17
UF4002
LC11
LC[0..15]
STR_12V13 LC1
+12v
P5
HDR 32W AMP ULTREX
A1A2A3A4A5A6A7A8A9
A10A11A12
B1B2B3B4B5B6B7B8B9B10B11B12B13A13
A14A15A16
B14B15B16
A1A2A3A4A5A6A7A8A9A10A11A12
B1B2B3B4B5B6B7B8B9
B10B11B12B13A13
A14A15A16
B14B15B16
Q46BUK552
LC2
ON PLUTO 5 128/16.
SEG13
*
LC14
LC15 DIG15
GND
Q40BUK552
*
SEG[0..15]13
*
LC2
DIG9
R116
680R
Q38BUK552
D9UF4002
SEG1
+12V
* -
GND
SEG4
SEG11
Page 49
Document No. 80-15151 Issue 6 HEBER LTD
Figure 12 - Schematic Sheet 12 - Lamp Row Drives
GND
MPX1_A_12V13
R50
22K
R85
3K3
MPX1_C_12V13
VMPX+
VMPX+
Q4
BC846
LR9
Q30TIP126
R91
3K3
LR15
Q6
BC846
Q34TIP126
R88
3K3
R48
22K
C16100n
GND
MPX1_D_12V13
C15100n
LAMP ROWS(SOURCE)
R54
22K
R78
3K3
Q18
BC846
R93
3K3
GND
GND
R56
22K
LR8
LR14
R87
3K3
Q22TIP126
R59
22K
R83
3K3
LR3
PP22PP
GND
© HEBER LTD, 1996-2002
GND
LR11
Q10
BC846
LR[0..15] 9
VMPX+
Q13
BC846
LR1
R61
22K
VMPX+
LR7
N63K3*8 SIL
12 3 4 5 6 7 8 9
Q19TIP126
GND
LR4
Q11
BC846
U19
4094
123
15
456714131211
9108
16
STRDCLKOE
Q1Q2Q3Q4Q5Q6Q7Q8
QSQSGND
VDD
LR4
N53K3*8 SIL
12 3 4 5 6 7 8 9
LR12
GND
+12V
LR13
Q20TIP126
Q15
BC846
LR2
GND
LR10
Q23TIP126
GND
Q17
BC846
Q3
BC846
R79
3K3
Q27TIP126
STR_12V13
LR7
LR5
Q31TIP126
R90
3K3
VMPX+
GNDLR6
LR13
OE_12V13
R86
3K3
VMPX+
LR0
R49
22K
LR0
R80
3K3
CLK_12V13
Q5
BC846
Q32TIP126
GND
MPX1_B_12V13
GND
Q7
BC846
VMPX+
LR14
LR12
PP20PP
R53
22K
Q25TIP126
R55
22K
Q24TIP126
GND
Q26TIP126
VMPX+
R57
22K
Q33TIP126
VMPX+
U18
4094
123
15
456714131211
9108
16
STRDCLKOE
Q1Q2Q3Q4Q5Q6Q7Q8
QSQSGND
VDD
R60
22K
LR5
LR15
LR11
R52
22KQ9
BC846
R84
3K3
GND
VMPX+
Q12
BC846
R81
3K3LR1
+12V
GND
LR8
Q21TIP126
R89
3K3
R46
22K
VMPX+
LR6
PP21PP
VMPX+
GND
R58
22K
GND
Q28TIP126R92
3K3
VMPX+
+12V
VMPX+
Q14
BC846
LR3
LR9
Q16
BC846
VMPX+
GNDR51
22K
56-15084 11r2
PLUTO 5 - LAMP ROW DRIVES
HEBER LTD.
Belvedere MillChalford, Stroud, GL6 8NTTel: +44 (0) 1453 886000Fax: +44 (0) 1453 885013
A3
12 13Tuesday , August 12, 2003
Title
Size Document Number Rev
Date: Sheet of
VMPX+
LR10
P6
HDR 16W AMP MTA-100
123456789
10111213141516
+12V
LR[0..15]
Q29TIP126
GND
VMPX+
LR2
R47
22K
VMPX+
Q8
BC846
R82
3K3
Page 50
Document No. 80-15151 Issue 6 HEBER LTD
Figure 13 - Schematic Sheet 13 - LED Segment Drives
R63
150R
Q51BC337
MPX_OE3
+12V
SEG3
MPX1_A_12V
U36
4094
123
15
456714131211
9108
16
STRDCLKOE
Q1Q2Q3Q4Q5Q6Q7Q8
QSQSGND
VDD
Q53BC337
R69
150R
CLK_12V
MPX_STR3
Q52BC337
MPX1_B_12V12
GND
OE_12V 11,12
R66
150R
SEG4
U34
4504
3 25 47 69 10
11 1214 15
13
1
16
8
AI AOBI BOCI CODI DOEI EOFI FO
MODE
VCC
VDD
GND
STR_12V 11,12 SEG0
OE_12V
MPX1_C_12V12
GND
OE_12V
U31F
4069
13 12
R65
150R
+12V
SEG11
GND
CLK_12V 11,12
Q54BC337
MPX_CLK3
Q63BC337
+12V
SEG5
LC8
1 3
2
LC9
1 3
2
Q61BC337
U35
4094
123
15
456714131211
9108
16
STRDCLKOE
Q1Q2Q3Q4Q5Q6Q7Q8
QSQSGND
VDD
STR_A_12V
STR_12V
56-15084 11r2
PLUTO 5 - LED SEGMENT DRIVES
HEBER LTD.
Belvedere MillChalford, Stroud, GL6 8NTTel: +44 (0) 1453 886000Fax: +44 (0) 1453 885013
A3
13 13Tuesday , August 12, 2003
Title
Size Document Number Rev
Date: Sheet of
SEG10
U31A
4069
1 2
GND
SEG9
MPX1_DATA_A3
R72
150R
MPX1_A_12V 12
VDD
SEG12
R73
150R
+12V
LC7
1 3
2
SEG15
R75
150R
Q57BC337
C42100n
CLK_12V
MPX2_A_12V
SEG8
SEG[0..15] 11
MPX_STR_DATA_A3
Q65BC337
U31D
4069
9 8
Q59BC337
R71
150R
Q55BC337
LC11
1 3
2
GND
+12V
GND
STR_A_12V
SEG7
R64
150R
R74
150R
STR_A_12V 11MPX2_DATA_A3
VCC
U31B
4069
3 4
U31C
4069
5 6
Q64BC337
SEG1
SEG6
SEG13
VCC
GND
R68
150R
Q58BC337
© HEBER LTD, 1996-2002
+12V
MPX1_A_12V
R76
150R
GND
MPX2_A_12V
Q56BC337
+12V
C41100n
GND
MULTIPLEX EXPANSION
SEG14
LC10
1 3
2
Q60BC337
R70
150R
MPX1_D_12V12
GND
GND
Q66BC337
U31E
4069
11 10
SEG2
R62
150R
LC6
1 3
2
+12V
STR_12V
GND
Q62BC337
R67
150R
SEG[0..15]
R77
150R
P11
HDR 7W 0.1 KK
1234567
Page 51
Document No. 80-15151 Issue 6 HEBER LTD
Figure 14 - Pluto 5 Component Ident
Page 52
Document No. 80-15151 Issue 6 HEBER LTD
Figure 15 - Photograph of Pluto 5 with Ultrex Connectors (Pluto 5U)