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E3VBEducation Engagement Electrical Validation

Board Experiment Description

Sep 2013

Intel Contacts: Dennis Griffit! "i#e $nderson! %on& "uilen'urg

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()er)ie*

#he Eucation Engagement Electrical !aliation Boar was create as part o% an

initiative calle &ntel Learning Company 2)3 to engage with university an help teach

stuents electrical valiation concepts) #he 'oar is mae up o% several circuits

esigne %or hans4on experiments that can 'e conucte using a low 'anwith

oscilloscope) #hese experiments emonstrate the importance o% ahering to goo

esign practices when laying out an routing signals on a 'oar) #he 'oar is

con%igura'le using sockets an 5umpers so that the stuent can see the i%%erence in

signal integrity when %ollowing or violating goo esign practices) #he physical 'oar is

shown in 6igure 1)

+igure 1: E3VB 'oard

Scematic ()er)ie*

#he schematic is availa'le in $D6 %ormat7 with the experiments groupe in one or two

pages) #en main experiments are liste7 though many more signal integrity concepts

can 'e emonstrate) 6igure 2 shows an example schematic circuit iagram) See

appenix 1)8 %or the schematic contents)

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+igure 2: Scematic diagram example from te ,corners and )ias- experiment

.a&out ()er)ie*

#he 'oar %ile can 'e opene using (llegro %ree physical viewer) #he tool can 'e use to

search %or components7 signals7 integrate circuits7 etc) ( snapshot o% the top layer is shown in

6igure + with signal routing visi'ility isa'le) ( snapshot o% each o% the layers is availa'le in

appenix 1)2)

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+igure 3: %op la&er of te EV 'oard

/outing Examples

6igure . an 6igure / show examples o% routing on the 'oar) "any o% the signal traces are

very long7 route too close to others7 or violate routing practices) #hese characteristics are ieal

%or emonstrating common signal integrity issues)

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+igure : .a&er Signal 1

+igure : .a&er Signal 2

Cloc#s

#wo sets o% clocks are use to %ee the ten experiments) #he clock %re9uency %or the %irst %ive

experiments an experiment are riven %rom the %irst set) #his clock is selecte an ena'le

'y populating one 5umper on each o% two heaer pin sets) #he %irst set is la'ele :/.7 an is

shown in 6igure 0 with 1 "; selecte) #he secon set is la'ele :17 an provies the clock

signal %or the remaining experiments) 6our %re9uencies are availa'le incluing* 1 ";7 2 ";7

. ";7 an 8 ";) See (ppenix 1)1 %or more in%ormation a'out how the clocks are

generate)

+igure : %e 1 "45 cloc# is selected using a 6umper

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Experimental Setup

$ower %or the 'oar is provie using mini ,SB) #he ca'le can 'e plugge into a wall aapter7

or laptop computer) Signals are measure using an oscilloscope with a recommene

'anwith o% /33 "; or more) Signals are pro'e using normal oscilloscope pro'es7 or a

B


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+igure ;: Experiment Bloc#s

Crosstal# Circuit 1

#he %irst experiment was esigne to show the e%%ects o% crosstalk) ( signal is riven own a

long trace that has two traces route closely to it on either sie) #he trace in the mile is

calle the victim trace7 an the traces next to it are calle aggressors) 6igure 13 shows the

victim trace routing) 6igure 11 an 6igure 12 show the aggressors)

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+igure 10: Victim trace

+igure 11: $ggressor 1 trace

+igure 12: $ggressor 2 trace

Each o% the three traces can 'e con%igure inepenently to 'ehave in one o% three ways*

toggle7 stay high7 or stay low) =hen in toggle moe7 the clock is route to the signal) #he e%%ect

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the aggressor traces have on the victim can 'e viewe an measure using an oscilloscope)

6igure 1+ shows the schematic iagram %or the victim trace) #he aggressors schematic 'locks

look the same) #he signal comes into a heaer that is esigne to provie three selecta'le

inputs* igh7 Low7 an #oggle) 6or the victim trace7 the heaer is la'ele :+3) #he 'oar also

has a la'el >!? next to this heaer) #he aggressors can 'e con%igure similarly using heaers

:2. an :28 @also la'ele (1 an (2A)

+igure 13: Victim scematic diagram

6igure 1. shows where the experiment is locate on the 'oar @circle in whiteA)

+igure 1: Crosstal# circuit 1 location

#he inverting 'u%%er chips la'ele ,0 an ,+ are sockete so i%%erent chips can 'e trie an

compare %or this experiment) Both sockets shoul 'e stu%%e as shown in 6igure 1/)

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+igure 1: In)erting 'uffer integrated circuit stuffed in soc#et


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+igure 19: $ggressors surrounding te )ictim signal =green dased line>

#he location o% the circuit %or this experiment is shown in 6igure 1- circle in white)

+igure 1;: Crosstal# circuit 2 location

Similar to the %irst experiment7 pattern selection heaers are provie to set the signals high7

low7 or to toggle) =hen in toggle moe7 the clock is route to the trace) #he 5umpers use to

select the pattern are as %ollows*

(ggressor 1* :./

(ggressor 2* :..

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!ictim* :.0

#o set the signal low7 leave the 5umper unpopulate) $opulating the 5umper on pins 1 an 2 will

set the signal high7 an stu%%ing 2 an + will set the signal to toggle up an own)

Outputs can 'e measure at the %ollowing pins*

!ictim Output* :+2

(ggressor 1 Output* :+

(ggressor 2 Output* :0

Exercise

,nlike the previous experiment where the victim signal was re%erence to groun7 the positive

victim signal will 'e re%erence to the negative victim signal in this exercise) 6igure 23 shows

how the i%%erential signal is 'uilt) #he top signal is the positive leg o% the signal7 pro'e %rom

:0. to groun) #he signal in the center is the negative signal pro'e %rom :0/ to groun) #he

'ottom signal is the com'ine i%%erential signal pro'ing %rom :0/ to :0.)


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#o see the e%%ects o% crosstalk on the signal7 ena'le the aggressor traces an set them to toggle)

#o ena'le the aggressor traces7 populate 5umpers :0+ an :.2)


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#he ecoupling circuit can 'e %oun on the mile le%t sie o% the experiment 'oar @circle in

white in 6igure 2+A)

+igure 23: Decoupling circuit

Decoupling Exercise

#he output %or this experiment can 'e measure at the heaer 'lock la'ele* Lo # # # # i @:.8

:/+A) #he outputs la'ele # look similar to each other)

Capture wave%orms at the output %or the case where !CC&< is populate7 an compare the

output to the case where the 5umper is not populate) =hat is the i%%erence in circuit 'ehavior

rouning Exercise

#he groun provie %or the inverting 'u%%er goes through a long high impeance trace when

5umper :0- is remove) 6igure .1 shows the routing %or this trace)

+igure 2: 4ig ? %race to Ground

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"easure the impeance %or this trace with the 5umper remove)

(ing the 5umper :0- connects the point irectly to groun)

ow oes the signal compare when the heaer la'ele S


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+igure 27: C% %race =o)er t*o la&ers>

#he circuit is pretty simple) #he clock signal comes in7 goes through an inverting 'u%%er7 own a

trace7 an through another inverting 'u%%er) #he general circuit topology is shown in 6igure 28)

#here are test points at the 'eginning o% the trace7 the en7 an at the output)

+igure 29: General circuit topolog&

6igure 2- shows where the location o% the experiment on the 'oar)

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+igure 2;: Corners and )ias experiment location

#he test points inclue*

!#$ start* :/8 !#$ en* :/0 !out* :03

C#$ start* :/- C#$ en* :. Cout* :.

#L#$ start* :/ #L#$ en* ::01 #Lout* :02

Exercise

Compare the rising an %alling clock eges %or the three signals)

ow o the eges compare when pro'ing at the start o% the trace7 an the en o% the trace)


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6igure +3 shows the location o% the circuit components an trace selector on the top o% the

'oar)

+igure 30: "&ster& traces exercise location

(ing a 5umper to eaer :1. will ena'le the clock on one o% eight traces7 each o% which is

route i%%erently) 6igure +1 shows an example o% the rising ege o% the corrupte signal7 an

how the trace length can 'e etermine 'y the uration the signal stays at one level) &n this

example7 there are three i%%erent segments each with i%%erent impeance) #he impeance can

'e etermine 'y the voltage level7 an the trace with can 'e calculate %rom this) #he routing

is shown in 6igure +2 )

+igure 31: "&ster& trace example

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+igure 32: %race routing

#o measure the signal7 a B


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+igure 33: Circuit Diagram

#he layer7 si;e7 an time %or each o% the traces are capture in the %ollowing ta'le*

#race 1 #race 2 #race +

Experiment Layer Si;e@milA

#ime@nSA Layer

Si;e@milA

#ime@nSA Layer

Si;e@milA

#ime@nSA

1 S1 .3 2 S2 23 2 S+ 0 2

2 S2 0 + S+ 23 2

+ S1 23 2 S. 8 .

. S2 13 +

/ S1 23 2 S. 0 2 S2 .3 2

0 S+ 0 .

S1 .3 2 S. 0 2 S2 12 28 S2 .3 2 S+ 0 +

(itional pro'e points are availa'le an outlines in the appenix uner the mystery traces

section)

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Simultaneous S*itcing (utputs

=hen multiple outputs switch simultaneously7 it is i%%icult %or power istri'ution to keep up) #he

groun potential %or the evice 'rie%ly raises compare with the system groun) #his e%%ect is

known as simultaneous switching noise7 or groun 'ounce) &nuction in the 'oar7 traces7 an

components keep power %rom 'eing elivere instantaneously)

#his exercise is esigne using counters that %ee a river so that many eges line up only

some o% the time) #he location o% the exercise on the 'oar is shown in 6igure +.)

+igure 3: Simultaneous s*itcing exercise location

#he circuit %or this exercise is mae up o% eight signals that %ee a river) #wo counters provie

seven s9uare waves that %ee seven o% the signals) #he eighth signal is DC voltage with the

level controlle 'y a potentiometer la'ele C= LO=ER @esignator ,23A) #he threshol can 'e

change 'y turning the screw on the potentiometer7 an measure at heaer :88)

Exercise

#o 'egin this exercise7 ena'le the counters 'y populating heaer :8 @next to the potentiometerA

with a 5umper) #he output o% each o% the seven signals is mae availa'le at heaer :132) Each

output is a s9uare wave with twice the perio o% the preceing as shown in 6igure +/) #he clockwas capture along with the signals %or comparison @:-+A)

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+igure 3: Dri)er outputs! and cloc# in

=hen the 1 "; signal is selecte %or the clock7 the %re9uency o% each output is as %ollows*

Output 6re9uency @k;A

3 2/3

1 12/

2 02)/

+ +1)+

. 1/)0

/ )8

0 +)-

=hen the 8 "; signal is selecte7 each clock %re9uency increases 'y a %actor o% 8)

Every 128 clock cycles all seven o% the counter signals switch at the same time) #his creates a

spike on the output signal) #he same thing can happen even when only a %ew o% the signalsswitch7 though the amplitue o% the istortion will 'e smaller)

"easure the output7 hit run an stop on the oscilloscope many times to view i%%erent noise

pro%iles7 or set the trigger level high to view spikes create 'y switching)

Compare the signal with the clocks ena'le an isa'le)

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Ena'le persistence on the oscilloscope to see what the output looks like over many

superimpose cycles)

.C/ %ransmission .ine

6or this experiment7 a clock signal is sent own a transmission line that can 'e lengthene

using 5umpers7 or out%itte with resistors7 inuctors an capacitors to mimic trace characteristics

%or high spee signals) Clock %irst goes through an inverting 'u%%er7 then has a connection %or

a B


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6igure +8 shows the routing %or the transmission line)

+igure 39: %ransmission line routing

Exercise

#o 'egin7 take a look at how the signal changes ue to lengthening the trace) #he transmission

line is mae as short as possi'le 'y removing the %our 5umpers that exten the transmission

line* #L17 #L27 #L+7 an #L. with esignators* :207 :1137 :27 an :111) Compare what the

signal looks like when each o% the next stages are ena'le)

"any con%igurations can 'e explore 'y aing resistors an capacitors to the legs rather than

5ust extening them with 5umpers) 6igure +- shows three examples) #he &S& exercise has

another example o% a possi'le 'lock in the circuit @an inuctor an capacitorA)

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+igure 3;: %ree possi'le configurations

Dri)er Circuit

#his circuit provies an environment to compare river technology) Relatively inexpensive

rivers exist that cannot switch as 9uickly as the more expensive ones) Some rivers can

switch the rising ege 9uickly7 'ut not the %alling ege7 etc) Sockets are provie on the 'oarso that the river chips can 'e swappe out) ere is a recommene list o% chips to try*

Chip Description

74C04 Inexpensive weak driver74HC04 edi!" #peed

74$04$as% rising edge& s'ow fa''ingedge

74(C04 $as% on )o%* edges

#he circuit is similar to that use in the crosstalk exercise7 an is shown in 6igure .3) #he trace

la'ele S#$ @slotte groun test pointA is route over a slot in the groun plane7 making it

more suscepti'le to noise) 6igure .1 an 6igure .2 show the routing) #est points are availa'le

at the 'eginning o% the trace7 the en7 an at the output a%ter going through the inverting 'u%%er)

#he sockets provie %or the inverting 'u%%ers are la'ele ,18 an ,1)

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+igure 0: Dri)er Circuit

+igure 1: /outing for Signal SG% =in 'lue>

+igure 2: /outing for signal % =in 'lue>

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6igure .+ shows the section o% the S#$ trace that is route over a slot in the groun plane)

+igure 3: SG% signal routed o)er a slot in te ground plane

Exercise

#o 'egin this exercise7 compare the .(C3. chip to the .63. chip when use as a circuit

river) "easurements can 'e taken at the en o% the transmission line %or 'oth the #$ trace an

the S#$ trace) 6igure 8 shows the location o% the circuit %or this exercise on the 'oar)

+igure : Dri)er Circuit .ocation

#he %irst measurement can 'e taken %or signal #$ at heaer :2)

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ac#age Differences

#his exercise was esigne to show i%%erences in signal 9uality ue to package type use) #he

chips are all solere own to the 'oar7 so %our circuits are provie which are the same)

6igure 82 shows one o% these %our circuits) #he input signal @the clockA goes through the chip7

then own a long transmission line) #he traces o% interest are la'ele >6ar? an are

route i%%erently) "easurement points are provie at the start an en o% the transmission

line) #he measurement points close to the start o% the traces %or the %our circuits are as %ollows*

$ro'e points at the start o% the#ransmission line

Signal >6ar?

-F1 D1 -F1 D2

-F2 D1 -F2 D2

-F+ D1 -F+ D2

-F. D1 -F. D2

"easurement points at the end o% the traces are*

$ro'e points at the end o% the#ransmission line

Signal >6ar?

-F1 S1 -F1 S2

-F2 S1 -F2 S2

-F+ S1 -F+ S2

-F. S1 -F. S2

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+igure : ac#age Difference Circuit %opolog&

#he package type an si;e use in this exercise are as %ollows*

#he circuit %or this experiment is locate on the 'ottom o% the 'oar7 circle in 6igure .0 in

white)

+igure : ac#age Difference Circuit .ocation

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Routing %or the SO&C chip is shown in 6igure . %or the >%ar? signal7 an 6igure .8 %or the >near?

signal)

+igure 7: S(IC ,+ar- %race +igure 9: S(IC ,8ear- %race

Exercise

6or this exercise7 signals are riven with %our chips each o% which has a i%%erent package) #he

signal can 'e compare %or each package type)

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Inters&m'ol Interference

&ntersym'ol inter%erence signal istortion is a result o% previous sym'ols inter%ering with the

current sym'ol) (s an example7 this coul a%%ect the uty cycle)

#o create this e%%ect7 this exercise uses a counter which %ees into shi%t registers) #he output is

then riven own a circuit similar to the river circuit7 'ut with an inuctor an capacitor7 as

shown in 6igure .-) #hese elements help simulate what the circuit response woul look like i% a

high spee inter%ace was use)

+igure ;: ISI Circuit Design

Switches are provie which the shi%t registers use to create the signal See 6igure /3)

+igure 0: DI S*itces

Experiment

#he circuit %or this exercise is locate in the center 'ottom portion o% the 'oar7 an is circle inwhite) See 6igure /1)

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+igure 1: ISI Circuit .ocation

#hree pro'e points are provie %or this experiment*

&n* :8-

Out* :80

#Line* :82

Exercise

Con%igure the ip switches to create i%%erent patterns7 an o'serve the e%%ect the patterns have

on %uture signals) Duty cycle is one area o% interest when o'serving signal integrity impacts) (s

an example o% what to expect %rom toggling the switches7 an example con%iguration is shown in

6igure /27 along with the signal in 6igure /+)

+igure 2: @umper configuration for te ISI exercise

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#o trigger with the oscilloscope7 it is use%ul to use output 2 o% heaer :132 @%rom the

simultaneous switching exerciseA) #his output allows %or triggering on a 02)/ k; signal when

the clock is at 1";7 an a /33 k; signal when the clock is set to 8 ";) #his is ieal to

capture wave%orms %or this exercise)

+igure 3: In )s %line )s (ut using te 1 "45 cloc#

Compare the input to output signal7 an to the transmission line) Does the input always

%ollow the ouput

$ppendix

1A1: Cloc# Design

#he clock was esigne using a 'inary counter) Each o% the %our outputs is e9uivalent to a clock

with a i%%erent %re9uency) 6igure (1 shows an example)

6igure (1* Binary counter outputs

1A2: Board .a&ers

Each o% the layers with signals route can 'e seen in the %ollowing %igures

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6igure (2* #op Routing

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6igure (+* Bottom routing

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6igure (.* Signal 1 routing

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6igure (/* Signal 2 Routing

1A3: Cloc# Dri)ers

Dri)er


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.* Simultaneous Switching

/* Crosstalk circuit 1

* Decoupling

Dri)er


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1A: "&ster& %races

/outing

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ro'e oints

$ro'e $oint

#race 1 2 +

1 :11 :/ :12

2 :11 :

+ :- :8. :-1

/ :0 :11. :2

0 :13

:110 :1+ :.

8 :10 :11/

1A: Integrated Circuits

#$S-031DCG.* ,L#R(LO=4


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10) $ackage Di%%erences 4 SO&C J #SSO$1) $ackage Di%%erences 4 D&$ J .(C112.318) &ntersym'ol &nter%erence1-) &ntersym'ol &nter%ace 4 Output M Spares23) "ounting holes 4 #DR #est $oint

1A7: Experiment 4eaders

Experiment 1* Crosstalk 1:1* (ggressor 1 transmission line test point @'eginningA:18* (ggressor 1 output test point:1-* !ictim transmission line ena'le:23* !ictim transmission line test point @'eginningA:21* (ggressor 2 transmission line test point @'eginningA:22* (ggressor 2 output test point:2.* (ggressor 1 pattern select

:28* !ictim pattern select:2-* (ggressor 1 transmission line ena'le:+3* (ggressor 2 pattern select:+1* (ggressor 1 transmission line test point @enA:+/* !ictim transmission line test point @enA:+8* (ggressor 2 transmission line test point @enA:.1* (ggressor 2 transmission line ena'le:.+* !ictim output test point

Experiment 2* Crosstalk 2

:00* (ggressor 1 transmission line start test point:+* (ggressor 1 output test point:0.* !ictim transmission line start test point @positiveA:0/* !ictim transmission line start test point @negativeA:.3* (ggressor 2 transmission line start test point:0* (ggressor 2 output test point:..* (ggressor 2 pattern select:./* (ggressor 1 pattern select:.0* !ictim pattern select:0+* (ggressor 1 transmission line ena'le:++* (ggressor 1 transmission line en test point

:+0* !ictim transmission line en test point @positiveA:+-* !ictim transmission line en test point @negativeA:08* (ggressor 2 transmission line en test point:.2* (ggressor 2 transmission line ena'le:+2* !ictim output test point

Experiment +* Decoupling

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:8* !CC&< ecoupling ena'le:3* Clock in test point:0-* S


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Experiment 8* Driver comparison an slotte groun:81* slotte groun transmission line test point @'eginningA:/* slotte groun transmission line test point @enA:0* slotte groun output test point:* transmission line test point @'eginningA

:2* transmission line test point @enA:.* output test point

Experiment -* $ackage i%%erences:13/* -F1FS1 4 test point @'eginningA:130* -F1FS2 4 test point @'eginningA:-8* -F1FD1 4 test point @enA:--* -F1FD2 4 test point @enA:13.* -F2FS1 4 test point @'eginningA:13+* -F2FS2 4 test point @'eginningA:-* -F2FD1 4 test point @enA

:-0* -F2FD2 4 test point @enA

:131* -F+FS1 4 test point @'eginningA:-.* -F+FS2 4 test point @'eginningA:83* -F+FD1 4 test point @enA:-* -F+FD2 4 test point @enA:8+* -F.FS1 4 test point @'eginningA:8.* -F.FS2 4 test point @'eginningA:138* -F.FD1 4 test point @enA:11+* -F.FD2 4 test point @enA

Experiment 13* &ntersym'ol inter%erenceS1* Dip switchesS2* Dip switches:8-* &n test point:82* #ransmission line test point @'eginningA:80* Output test point

Other Clock %re9uency selectors:/.* Block 1:1* Block 2

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