Potential PCI Express Signaling Beyond 16GT/s...Title PCI-SIG® DEVCON 2015 UPDATE Author Office...

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Copyright © 2016 PCI-SIG® - All Rights Reserved

Potential PCI Express®

Signaling Beyond 16GT/s

o Mehdi M. Mechaik

o Senior Technical Staff Member

o IBM Corporation


Copyright © 2016 PCI-SIG® - All Rights ReservedPCI-SIG Developers Conference 2016

Disclaimer

2

Presentation Disclaimer: All opinions, judgments, recommendations,

etc. that are presented herein are the opinions of the presenter of the

material and do not necessarily reflect the opinions of the PCI-SIG®.



Authors

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o Authors:

• Mehdi M. Mechaik, Ph.D.

Senior Technical Staff member

IBM Corporation

Email: [email protected]

• Daniel M. Dreps

IBM Interface Design Engineer and DE

IBM Corporation

Email: [email protected]

mailto:[email protected]

mailto:[email protected]



Overview

o This analysis provides a comparison of NRZ

and PAM4 electrical performance for

operating a PCIe® interface topology at

32GT/s speed

o The analysis compares frequency domain

losses and eye diagrams at the end of a

lossy PCIe channel

o The channel is representative of a general

PCIe 4.0 topology connecting a CPU to an

End Point device

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Overview (continued)

o Analysis is done for these cases:

• NRZ signaling scheme:

• with error corrections

• without error corrections

• PAM4 signaling scheme:

• with error corrections

• without error corrections

o The channel is composed of one victim pair

and eight aggressor pairs

o All pairs have 85 ohm impedance

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Jitter and Noise Values

o Jitter assumptions used in simulations:

• NRZ

• TX: Rj: 0.52 %UI (rms), Sj: 6 %UI (pk-pk), DCD: 1.3 %UI

• RX: Rj: 0.77 %UI (rms), Sj:18 %UI (pk-pk)

• RX: AM: 10, 5, 2, AN: 4, 3, 2, 1

• PAM4 (case 1)

• TX: Rj: 0.26 %UI (rms), Sj: 3 %UI (pk-pk), DCD: 0.65 %UI

• RX: Rj: 0.39 %UI (rms), Sj: 9 %UI (pk-pk)

• RX: AM: 10, 5, 2, AN: 4, 3, 2, 1

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Jitter and Noise Values

(continued)

• PAM4 (case 2)

• TX: Rj: 0.52 %UI (rms), Sj: 3 %UI (pk-pk), DCD: 0.65

%UI

• RX: Rj: 0.77 %UI (rms), Sj: 9 %UI (pk-pk)

• RX: AM: 10, 5, 2, AN: 4, 3, 2, 1

• AM: is the minimum latch overdrive pk-pk voltage (mV)

level. AM is swept across three values: 10, 5, and 1

• AN: is the Gaussian amplitude noise rms voltage (mV). AN is swept across four values: 4,3,2, and 1

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Channel Topology

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Channel Loss:

PCIe® 4.0 Speed

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IL (dB) = 27.9 dB @ 8GHzS/XT (dB) = 18.2 dB @ 8GHz



Channel PCIe 4.0

Eye Diagram

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EW = 30.2 %UIEH = 20 mV

TX: Preset: 8Voltage: 0.8V3-Tap FFERj: 0.57%UISj: 12%UITXDCD: 3.125%

RX: CTLE: 7DFE: 2Rj: 0Sj: 0



Channel Summary

o The channel topology satisfies the draft PCIe

4.0 compliance criteria:

• Eye Width > 30%UI

• Eye Height > 15 mV

• Channel loss < 28dB

o Next: Operate channel at 32GT/s

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Channel @ 32GT/s

o Simulate same channel topology for 32GT/s

speed:

o Look at:

• Channel Loss

• Channel performance with NRZ signaling:

• Without error correction

• With error correction

• Channel performance with PAM4 signaling:

• Without error correction

• With error correction

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Channel Loss @ PCIe 32GT/s

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IL (dB) = 27.9 dB @ 8GHzS/XT (dB) = 18.2 dB @ 8GHz

IL (dB) = 50 dB @ 16GHzS/XT (dB) = 12.4 dB @ 16GHz



Eye Diagram

(NRZ without FEC)

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AM = 2 mVAN = 1 mVEW = 10 %UIEH = 1.7 mV

AM = 5 mVAN = 2 mVEW = 6.8 %UIEH = 0 mV

AM = 5 mVAN = 4 mVEW = 0 %UIEH = 0 mV




Eye Diagram (NRZ with FEC)

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AM = 5 mVAN = 2 mVEW = 37 %UIEH = 5.7 mV

AM = 5 mVAN = 4 mVEW = 35.8 %UIEH = 4.6 mV




NRZ Eye Diagram Summary

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Eye is closed for high values of AM and AN (without FEC) FEC opens eye even for high AM and AN FEC fixes the excessive channel loss for NRZ signaling



NRZ Eye Diagram Summary

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Eye is closed for all values of AM and AN (without FEC) NRZ FEC opens eye for small and mid values of AM and AN FEC fixes the excessive channel loss for NRZ signaling



Eye Diagram

(PAM41 without FEC)

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Eye Diagram

(PAM41 with FEC)

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PAM4-1 Eye Diagram

Summary

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Eye is closed for all values of AM and AN (without FEC) PAM4 FEC opens eye even for high values of AM and AN FEC fixes the channel loss for PAM4 signaling



PAM4-1 Eye Diagram

Summary

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Eye Diagram

(PAM42 without FEC)

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Eye Diagram

(PAM42 with FEC)

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PAM4-2 Eye Diagram

Summary

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PAM4-2 Eye Diagram

Summary

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Eye is closed for all values of AM and AN (without FEC) PAM4 FEC opens eye even for high AM and AN FEC fixes the channel loss for PAM4 signaling



Conclusion

o The channel topology in this analysis meets

the draft PCIe 4.0 specifications

o The same topology has excessive losses

32GT/s speed as a future generation candidate

o NRZ signaling results in closed eye for all

values of AM and AN if FEC is not used

o However the electrical performance of the

lossy channel can be improved by using

Forward Error Correction. FEC opens the eye

diagram for NRZ signaling

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Conclusion

o PAM4 signaling also results in closed eye for all values of AM and AN if FEC is not used

o FEC opens the eye diagram for PAM4 signaling for small and high values of AM and AN

o Increasing Rj values by 100% has small effect on the eye (< 8%)

o Both NRZ and PAM4 signaling need FEC to open the eye at the end of a very lossy channel

o Serial Interface channels like those for PCIe@25GT/s or 32GT/s can operate with good margins if NRZ or PAM4 signaling are used with Forward Error Correction

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Potential PCI Express Signaling Beyond 16GT/s...Title PCI-SIG® DEVCON 2015 UPDATE Author Office...

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