Power

© Digital Integrated Circuits2nd Inverter

POWERPOWER

Introduction to Low PowerIntroduction to Low Power VLSI DesignVLSI Design

Dr Anu Mehra


Where Does Power Go in CMOS?Where Does Power Go in CMOS?

• Dynamic Power Consumption

• Short Circuit Currents

• Leakage

Charging and Discharging Capacitors

Short Circuit Path between Supply Rails during Switching

Leaking diodes and transistors


Power dissipation can be

• dynamic

• due to capacitive switching

• short circuit power due to crowbar currents

•Glitches in output waveform

•Static

• leakage currents –

sub threshold current + reverse bias

• standby current –pseudo nmos


Dynamic Power

Charging and discharging of capacitors due to logic switching event


Each time the input switches from 0to 1 or 1 to 0 power is consumed.

PART IS DISSPATED in charging and discharging the capacitor

PART IS STORED in the load capacitor


Dynamic Power DissipationDynamic Power Dissipation

Energy/transition = CL * Vdd2

Power = Energy/transition * f = CL * Vdd2 * f0 to1 or 1 to 0

Need to reduce CL, Vdd, and f to reduce power.

Vin Vout

CL

Vdd

Not a function of transistor sizes!

iVDD

f0 to1 or 1 to 0 is the frequency of transition


2

000

)( DDL

VDD

outDDLout

LDDDDVDDVDD VCdvVCdtdt

dvCVdtVtiE

2)(

2

000

DDLVDD

outoutLoutout

LoutVDDC

VCdvvCdtv

dt

dvCdtvtiE

Half the energy stored in the Capacitor, the other half is lost !


Node Transition Activity and PowerNode Transition Activity and PowerConsider switching a CMOS gate for N clock cycles

EN CL Vdd 2 n N =

n(N): the number of 0->1 transition in N clock cycles

EN : the energy consumed for N clock cycles

Pavg N lim

ENN

-------- fclk= n N

N------------

N lim

C

LVdd

2fclk

=

0 1

n N N

------------N

lim=

Pavg = 0 1 C

LVdd

2 fclk


Transistor Sizing for Minimum EnergyTransistor Sizing for Minimum Energy

A quick review of delay


Delay FormulaDelay Formula

Cint = Cgin with 1f = Cext/Cgin - effective fanoutCext=fCgin

R = Runit/W ; Cint =WCunit

tp0 = 0.69RunitCunit

Let tp=0.69 Req(Cint+Cext)=0.69 ReqCint(1+Cext/Cint)=tp0(1+Cext/Cint)=tp0(1+f/)


Transistor Sizing for Minimum Transistor Sizing for Minimum EnergyEnergy

Goal: Minimize Energy of whole circuit Design parameters: f and VDD

tp tpref of circuit with f=1 and VDD =Vref

1Cg1

In

fCext

Out

TEDD

DDp

pp

VV

Vt

f

Fftt

0

0 11


Delay as a function of VDelay as a function of VDDDD

0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.41

1.5

2

2.5

3

3.5

4

4.5

5

5.5

VDD

(V)

t p(nor

mal

ized

)


Total Capacitance of inverter chain is

Cg1+Cint1+Cext1+Cint2+Cext2

=Cg1+Cg1+fCg1+fCg1+FCg1

=Cg1(1+ffF)E=VDD

2(total capacitance)


Transistor Sizing (2)Transistor Sizing (2) Performance Constraint (=1)

Energy for single Transition

13

2

3

2

0

0

F

fF

f

VV

VV

V

V

F

fF

f

t

t

t

t

TEDD

TEref

ref

DD

refp

p

pref

p

F

Ff

V

V

E

E

FfCVE

ref

DD

ref

gDD

4

22

112

12


f

Fftptp

110

f

Fftp 2

1

Let for a reference device f=1


ref

DD

TEDD

TEref

TEref

ref

TEDD

DD

V

V

VV

VV

reftp

tp

VV

Vreftp

VV

Vtp

Freftp

fF

ftp

tpref

tp

Freftptpref

0

0

0

0

30

20

30


1 2 3 4 5 6 70

0.5

1

1.5

2

2.5

3

3.5

4

f

vdd

(V

)

1 2 3 4 5 6 70

0.5

1

1.5

f

no

rma

lize

d e

ne

rgy

Transistor Sizing (3)Transistor Sizing (3)

F=1

2

5

10

20

VDD=f(f) E/Eref=f(f)


Short Circuit CurrentsShort Circuit Currents

Also called crowbar currents Refers to direct path from

VDD to VGND during switching events

scr is short circuit rise time

And scf is short circuit fall time

PSC is short circuit power consumption

ISC is the short circuit current consumed

Δtsc is the duration for which the short circuit current flows

ISC,avg is the average crowbar current during rise and fall.


Csc is short circuit capacitance

clkfT

1


Short Circuit CurrentsShort Circuit Currents- another approach- another approach

• Rise/Fall time of input wave is greater than 0, so short circuit current will flow

•Let VTn=VTp=VT

•Consider 0 to 1 transition. Initially when Vin was 0, pmos was on and nmos was off

•As point 1 approaches nmos is turned on as Vin =VT. pmos is still on

•Short circuit current flows from VDD to GND

•Current increases to maximum when both devices enter saturation

•As point 2 approaches, pmos shuts down, crowbar current stops flowing

VT

VDD-VT

1 2 time

voltage


Direct Path currents contd.Direct Path currents contd.

Area of an equilateral triangle is 1/2base. perpendicularP=VI, E=Pt


f0 to1 or 1 to 0 is

switching frequency

ts is 0 to 100% transition time

tr(f) is 10 to 90% transition time


How to minimize crowbar currents?How to minimize crowbar currents?• Consider a CMOS inverter with a 0 to 1 transition at the input

•Let CL be very large

•Thus, output will make a a 1 to 0 transition tf=0.69RNCL

•This delay will also be large

•Assume that input rise time is very small

•Input will change through transition before output changes

•Vs of pmos is at VDD

•VD of pmos will be approximately at VDD

•Thus VDS of pmos is approx 0

•Device shuts off before delivering any current


How to minimize crowbar currents?How to minimize crowbar currents?• Consider again a CMOS inverter with a 0 to 1 transition at the input

•Let CL be very small

•Thus, output will make a a 1 to 0 transition tf=0.69RNCL

•This delay will also be small

•Assume that input rise time is very large

•Input will change through transition slowly

•Vs of pmos is at VDD

•VD of pmos will be approximately at 0

•Thus VDS of pmos is approx VDD

•Maximum short circuit current is

delivered


Short Circuit CurrentsShort Circuit Currents

Vin Vout

CL

Vdd

I VD

D (m

A)

0.15

0.10

0.05

Vin (V)5.04.03.02.01.00.0


How to keep Short-Circuit Currents Low?How to keep Short-Circuit Currents Low?

Short circuit current goes to zero if tfall >> trise,but can’t do this for cascade logic, so ...

Input slope is fixed


Conclusion…Conclusion…

•Large CL may mean less short circuit power, but it will also mean longer delays

• Will lead to short circuit currents in fan out gate as their tin will be slow!!

•Local Optimization pointless!

•To minimize power consumption in a global way

Match rise/fall times of input and output waveforms


Minimizing Short-Circuit PowerMinimizing Short-Circuit Power

0 1 2 3 4 50

1

2

3

4

5

6

7

8

tsin

/tsout

Pno

rm

Vdd =1.5

Vdd =2.5

Vdd =3.3


Notice in the previous graph that when tsin/tsout=1 Power Dissipation is minimum

Reducing VDD leads to lower power consumption

Point 1 is VTn Point2 is VDD-VTP If 2 lies before 1 short circuit power consumption is 0! However circuit will be slower

VT

VDD-VT

1 2 time

voltage


Dynamic Power -GlitchesDynamic Power -GlitchesGlitches are caused by arrival time of two separate input signals. If a given input signal arrives first and causes the output to switch, later another input signal arrives and causes the output to switch back to original value.

Undesired Power dissipation ! Glitches propagate thought the fanout gate and cause further unintended transitions


To reduce glitches,

•Signals should be made to arrive at roughly the same time

• Certain architectures and logics are made glitch free inherently


Static Power Consumption Static Power Consumption

Caused by leakage currents due to

•Reverse biased Source and drain junctions

•Subthreshold currents and ie currents that flow when VGS is less than VT


LeakageLeakage

Vout

Vdd

Sub-ThresholdCurrent

Drain JunctionLeakage

Sub-Threshold Current Dominant FactorSub-threshold current one of most compelling issuesin low-energy circuit design!


Reverse-Biased Diode LeakageReverse-Biased Diode Leakage

Np+ p+

Reverse Leakage Current

+

-Vdd

GATE

IDL = JS A

JS = 1-5pA/m2 for a 1.2m CMOS technology

Js double with every 9oC increase in temperature

JS = 10-100 pA/m2 at 25 deg C for 0.25m CMOSJS doubles for every 9 deg C!


Junction Leakage currents are caused by thermally generated carriers. Their value increases with increasing temperature. At 85 degrees Celsius, (upper bound for junction temperature) their value increases by 60 times over room temperature value.


Subthreshold Leakage ComponentSubthreshold Leakage Component


Sub threshold Leakage issuesSub threshold Leakage issuesCloser VT is to 0 V, larger is the static power dissipation as ID becomes larger

L is getting smaller as source and drain are getting closer

Supply voltages are being scaled while keeping VT

constant. This leads to increase in delay –see next slide. As Supply voltage goes down to 2VT,,

performance goes down substantially.

If VT is lowered, performance improves, sub threshold leakage becomes an issue

i.e. Trade off between power and delay!


Delay as a function of VDelay as a function of VDDDD

0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.41

1.5

2

2.5

3

3.5

4

4.5

5

5.5

VDD

(V)

t p(nor

mal

ized

)

VT=0.5V


Static Power ConsumptionStatic Power Consumption

Vin=5V

Vout

CL

Vdd

Istat

Pstat = P(In=1).Vdd . Istat

• Dominates over dynamic consumption

• Not a function of switching frequency

Wasted energy …Should be avoided in almost all cases,but could help reducing energy in others (e.g. sense amps)


Principles for Power ReductionPrinciples for Power Reduction

Prime choice: Reduce voltage! Recent years have seen an acceleration in

supply voltage reduction Design at very low voltages still open question

(0.6 … 0.9 V by 2010!)Reduce switching activityReduce physical capacitance

Device Sizing: for F=20– fopt(energy)=3.53, fopt(performance)=4.47


Modification for Circuits with Reduced Swing

CL

Vdd

Vdd

Vdd -Vt

E0 1 CL Vdd Vdd Vt– =

Can exploit reduced swing to lower power(e.g., reduced bit-line swing in memory)


Power EquationPower Equation

Static power loss in pseudo nmos only half the time!


POWER DELAY TRADE OFFPOWER DELAY TRADE OFF

We want low power and small delay. Why not minimize the product?

Pavg is average Power consumed

tp is average delay

Only dominant term in Power Equation

Assume Gate switches at maximum possible rate so rise and fall


To Reduce PDPTo Reduce PDP

•Reduce Load Capacitance

•Reduce Supply Voltage

•PDP does not capture the fact that reducing Supply Voltage lowers Power consumption, but increases delay

•New metric Energy Delay Product is defined (EDP)

•EDP=PDPtp


Differentiating EDp w.r.t. VDD and putting the result equal to 0


VDD(V)

VT=0.5V

© Digital Integrated Circuits2nd InverterLPVD Lecture-1

Three components :

• Dynamic Capacitive (Switching) Power:- Charging and Discharging the capacitance.- Still dominant component in current technology.

• Short-circuit Power:- Due to current flow from Vdd to GND.- Worst in case of slow transition.

• Leakage Current:- Diodes Leakage around transistor and N-well.- Increases 20 times for each new technology.- Becoming insignificant to the dominant factor.

SOURCES OF POWER DISSIPATIONSOURCES OF POWER DISSIPATION


• Reduced switching voltage:

- P=CfV2 Saving in power but performance is lost. - Transistors become slow due to low Vt, leakage

current increases. Noise margins problem increases. • Reduced leakage and Static Current:

- Can be reduce by transistor sizing, layout techniques, and careful circuit design.

- Circuit models can be turned off if not in used.• Use Standby Mode :

- Clock disabling and power-off of selected logic blocks.

LOW POWER APPROACHESLOW POWER APPROACHES


• Reduced Switching Capacitance:

- Can not reduce blindly. Reduce product of cap and switching frequency.

- Signals with high switching frequency are routed with minimum parasitic cap.

- Node with large Capacitance are not allowed to switch at high frequency.

-capacitance reduction is achieved at different level. Material, technology, physical design, circuit technique.


Reduced switching Frequency:

- Eliminate logic switching that is not necessary for computation to reduce the frequency.

- Change the logic family, use different coding method, number representation system. They can alter the switching frequency of the design

•Adiabatic Computing :

- Avoid gain / loss of heat during computing.


Thank you ………….Thank you ………….

Date post:	21-Jun-2015
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