Power Conversion Using Freescale Digital Signal...

External Use

TM

Power Conversion Using Freescale

Digital Signal Controllers and Kinetis

V Series Microcontrollers

FTF-SDS-F0038

A P R . 2 0 1 4

Charlie Wu | Senior Member of Technical Staff

Mark Houston | Product Marketing Manager

TM

External Use 1

Agenda

• Objective: Review challenges of digital power control systems and show how digital signal controllers are helping to meet the growing requirements.

• Agenda: − Digital Power Trends and Landscape

− Digital Signal Controller Product Overview

− Kinetis V Series MCUs Overview

− Key Peripherals for Digital Power

− Resonate Converter Introduction

− Application Example: Digital Control of LLC Resonant Converter

− Q&A

TM

External Use 2

Next Generation Energy Landscape

• Mobile Power Adapter

• Low End Wireless

Charger

• Ceiling Fans

• Hand Held Tools

•25-35 MHz core

•High Res PWM

•Low power consumption

•12-bit ADC @ 1uS

•Small memory

•Very cost sensitive

•35-50 MHz core

•High Res PWM

•Reduced power consumption

•12-bit ADC @ 1uS to 500nS

•Mid size memory

•Cost sensitive

•60 MHz core

•High Res PWM

•12-bit ADC @ <700nS

•System integration

•80 MHz core

•High Res PWM

•12-bit ADC @

<500nS


• Improved math

features

•100 MHz core

•Very High Res

PWM

•12-bit ADC @

<500nS

•Flash >128kB


• Improved math

features

Application Complexity

• Power Factor

Correction

• Offline Solar Inverter

• Single Motor Control

• Micro Inverter

• Wireless Charger

• Battery Inverter

• Digital Power –

1-phase

• Sensorless Motor

Control

• Server Power Supply

• Micro Inverter

• Induction Hob –

2 burners

• Dual Motor Control

• Industrial Motor

Control

• Induction Hob – 4

burners

• Digital Power - 3ph

• Multilevel Inverter

• Online UPS

• Grid Tied Solar

Inverter

TM

External Use 3

Where Is Digital Power Conversion Applied ?

• “Digital power Conversion” is a power system that is controlled by digital circuits, in much the same way as would be with analog circuits, to monitor, supervise, communicate and control looping. A fully digitally controlled power system includes both digital control and digital power management.

• Digital Control − The control feedback or feed-forward loop, which is controlled by the digital circuit

or programmable controller, regulates the output of the power system by driving the power switch duty cycle using pulse width modulation techniques.

− The control circuits combine A/D conversion, Pulse Width Modulation, and Communication interfaces, operating entirely or mostly in digital mode.

• Digital Power Management − A Digital circuit or programmable controller provides the functions

of configuration, tracking, monitoring , protection, supply sequencing,

and communication with the environment.

TM

External Use 4

Comparison of Analog and Digital Power Control System

R

C

REF

SCALE

Analog

Compensator

Network

Analog

Compensator

Network

Voltage

Current

Power

Switch

LC

Filter

PWM

Generator

CLK

C

Voltage

Ramp

Network

DC Input DC Output

DC Input

Voltage

SCALE

Power

Switch

LC

Filter

DC Output

SCALE

Digital

PWM

Generator

A to D Converter

Current

Serial Interface

DSP Controller

Tempe

-rature

Fan

GPIO

Full Digital Control System Analog Control System With Digital Management

Fan

A to D Converter

Voltage

Current

Temperature

Serial Interface

GPIO

Shut

Down

Microcontroller

Both MCU and Analog PWM controller

Is replaced by one DSC

TM

External Use 5

Analog Control vs. Digital Control - Transient Response Comparison

Vout

Iout

Constant Voltage

Constant Power

Constant Current

• No OV and no OC during transient

because of the smooth loop

transition

• Output profile is programmable

Advanced Digital control

Power Fold Down

Iout

Vout Constant Voltage

Constant Power Over current during load step-up

Over voltage during load step-down

Traditional Analog control Constant Current

TM

External Use 6

Digital vs. Analog Control Loop

Benefit of digital control:

1. 1) Optimize feedback loop to meet application requirements

2. 2) Runtime changes to compensation parameters according to operating conditions

Vref Vout

Linear compensation Power stage

+ -

4

4

3

3

2

2

1

10

4

4

3

3

2

210

SBSBSBSBB

SASASASAAK

211

)1(

SS

S

A typical control loop implemented by an analog circuit

A digital control loop implemented by Digtal Signal Controller (DSC)

Vref Vout

Adaptive compensation Power stage

+ -

Nonlinear

compensation

Operation condition

4

4

3

3

2

210

4

4

3

3

2

210

SSSS

SSSS

Software Implementation

211

)1(

SS

S

TM

External Use 7

The differences between hard switch and soft switching

Benefits of soft switching

• Greatly reduce over-all electro-magnetic emissions over a wide

frequency spectrum

• Higher system efficiency and less heat dissipation will result in

increasing the power density of the system

Soft Switch Technology

Hard Switching Soft Switching

Fast transition rate during on-off transition Moderate transition rate during on-off transition

Overlaps between transitions of voltage

and current Either zero voltage switching or zero current switching

High noise generation and switch loss Low noise generation and very low switch loss

TM

External Use 8

Transfer Function Of Control Loop

V*o is the reference;V0is the output; Kvs is the feedback gain.

Control loop includes a PID controller and a power stage model.

PID controller is a dynamic error regulator

PID transfer

function

Power Stage

transfer function

S S ) ( G VEA ) ( G vh

vs K

o v *

o V

*

f V

TM

External Use 9

• Continuous ( Analog) Expression

• Difference ( digital ) Expression

-

+

Command Xi(t)

Feedback Xf(t) Output M(t)

M(t) = Kp*e(t) + Ki*e(t)dt + Kd * ---- e(t) d dt

e(t) = Xi(t) – Xf(t) ----- (1)

----- (2)

n m(n) = Kp e(n) + Ki e(i) t + Kd ----------------

t

e(n) – e(n-1)

i=0

m(n)= m(n-1) + Kp [e(n)-e(n-1)] + Ki e(n) t + Kd [---------------- - ------------------- ] e(n) – e(n-1)

t t

e(n-1) – e(n-2)

- (3)

- (4)

Where -- e(t): Error signal; Kp: Proportional Gain; Ki: Integral Gain; Derivative Gain

Control Law Processor - PID Controller (Proportional-Integral-Derivative)

TM

External Use 10

1

1

1

)(

1

)]([&)()]1([

tionTransformaZToConversion

z

zEn

i

nezzEznez

tKKtKivKKK didippv ;;:Where *

)5()1(1)(

)()(

(4)EquationFrom

1*

1

**

zK

z

KK

zE

zMzVEAG idpv

iv

Digital PID Controller

*pvK

)1( 1* zKiv

)1( 1* zKid

+ +

+

)(zE

e(n)

)(zM

m(n)

Design of Control Feedback Loop In Digital Domain PID Regulating Loop

TM

External Use 11

Power stage Z-transformation function

)(SGv

S

e SST1

)(SGvh

( ) ov

vo o

v KG S

v SCV

)1(]

)([)1())(()( 1

zCV

TK

S

SGZzSGZzG

o

Svvhvh

Vo and Vvo are values of output and loop output ~ ~

Design Of Control Feedback Loop In Digital Domain Model Of Power Stage Transfer Function

TM

External Use 12

vssT

vhsT

VEAsT

openv KeGeGeG sss )()()(

vsvhVEAopenv KzGzGzG )()()( ssT

ez

Measurement criteria for a stable closed loop system - Phase margin should be greater than 45°at open loop cross frequency

- Gain margin should be greater than one at the frequency where the phase shift is -180°

1)(45180)( scsc Tj

openvTj

openv eGwhereateG

) ( Z G VEA ) ( Z G

vh

vs K

o v *

o V

T

180)(1)(1 scsc Tj

openvTj

openv eGwhereateG

PID Parameter Design For Feedback Loop Control

TM

External Use 13

Analog Control Digital Control

Control Circuit Complex, Bulky Simple, Programmable,

Integrated

Flexibility Bad Good

Design Continuity Bad Good

Sample Mode Continuous Digitialization Error

Processing Continuous Control Delay

Compare Digital Control To Analog Control

TM

External Use 14

EMI

Filter PFC

Option

High Voltage

Buck or Boost

Synch

Rectifier

Output

Filter

Switching

Regulator

MOSFET

PWM

Isolator

Opto

Coupler Primary side

Digital Controller

Secondary Side

Digital Controller

PWMs PWMs PWMs PWMs Vdd ADCs ADCs

Back Panel Connector

GPIOs

AC

IN

DC

Out

Switching

Regulator

Vdd

Digital Controlled Power Supply

TM

External Use 15

Benefits of Digital Power

• Free from the effects of component tolerance, parametric drift, aging, etc.

• Configurable feedback loop structure for specific application requirements

• Adaptive control to meet changing operating conditions

• Flexible Pulse Width Waveform-generation module

• Programmable relationships among PWM outputs

• Upgradeable with new features without hardware changes

• Retainable operational data for diagnostic and record keeping

• Diverse communications capabilities

• Reduced component count and cost

• Higher power density due to over all integration

• Shorter R&D cycle, fewer turns of board prototyping

• Portable Projects for faster reuse

• Defendable firmware–protects IP and differentiating technology

TM

External Use 16

8/16/32 bit MCU and DSC

FSL Solutions

Power MPU

i.MX MPU

RF/Wireless

Freescale Power Conversion Solutions

TM

External Use 17

Digital Signal Controller Product

Overview

TM

External Use 18

High Performance

DSC Core

Intelligent

Peripherals

Compelling Roadmap

Outstanding Enablement

• Ease of use of a microcontroller (MCU) and the processing power of a digital signal processor (DSP)

• Reduced complexity and latency with simplified memory structure, shadowed register set, interrupt prioritization and cache

• 32-bit core improves precision without compromising performance

• Portfolio scales to exactly fit the applications needs

• Flexible cores scale from 32MHz to 100MHz

• Flash extends from 12kB to 256kB with additional Flex Memory

• Packages range from 28pins to 100pins

• Enhanced customer experience via integrated tools and reference designs

• Code reusable across the complete portfolio

• Extensive S/W libraries provide quick project ramp up

• Very high speed ADCs capture events real time

• High resolution PWMs improve switching efficiency and control performance

• Flexibility with the crossbar to simplify pin out and peripheral inter-connection

• DMA to reduce CPU overhead

Winning with Freescale DSC in Digital

Power Conversion & Motor Control

TM

External Use 19

What is Digital Signal Controller?

• Specialized microprocessor whose architecture contains a core engine capable of competitively performing both microcontroller and digital signal processor functionalities

• Core processing capability applicable to many types of system solution

• Common basic features: − MAC, single instruction cycle allowing several memory accesses, address generation

units, algorithms for efficient looping

• Specialized cost effective, high performance on-board interfaces utilized in implementing embedded control applications: − PWM; multifunction timer; high speed ADCs; DACs; Comparators; SCIs (UART);

SPIs; CANs and I2Cs, etc.

• Embedded nonvolatile memory: − Flash memory, ROM or EEPROM

• Easy to use development tools

TM

External Use 20

Traditional

Microcontroller

• Designed for Controller Code

• Compact Code Size

• Easy to Program

• Inefficient Signal Processing

Traditional DSP

Engine

• Designed for DSP Processing

• Designed for Matrix Operations

• Complex Programming

• Less Suitable for Control

• Instructions Optimized for Controller Code, DSP, Matrix Operations

• Compact Assembly and “C” Compiled Code Size

• Easy to Program

• Additional MIPS Headroom and extended addressing space

56800/E Family Combining Signal Processing

and Controller Functionality

TM

External Use 21

DSP56800E Core Features

CPU MIPS # Interrupt

Priorities Registers Data Types Program Memory

Adr Space

Data Memory

Adr Space Technology

DSP56800E 120 from RAM

60 from Flash

5 7 Data

8 Address 8-bit, 16-bit

32-bit 4 MB 32 MB

Fully Synthesizable and Scanable

Multiplier - Accumulator (MAC)

Single And Dual Parallel Move Instructions

No Overhead Hardware Looping

Nested Looping Capability

Nested Interrupt with HW priority

Fast Interrupt Support

Modulo arithmetic (For Circular Buffers)

Integer and Fractional Arithmetic Support

56800/E DSP Functionality 56800/E MCU Functionality

True Software

Stack and Pointer

General Purpose Register Files and Orthogonal

Instructions to Data and Address Register Files

20 Addressing Modes and Atomic

Read-Modify-Write Instructions

Full Set of Bit and Bitfield Manipulation

Instructions and 16- and 32-bit Shifting

16-bit Program Word

Superfast Interrupt

TM

External Use 22 22

Operations Performed:

• Multiply-Accumulate

• 3 Memory Accesses

• 2 Address Additions

DATA

ALU

A B C D

Y0 Y1 X0

MAC and ALU

Multi-bit Shifter

R0

R1

R2

R3

R4

R5

N

SP

AGU ALU1 ALU2

M 01

BIT

MANIPULATION

UNIT

EOnCE / JTAG

TAP

XAB1

XAB2

PAB

PDB

CDBW

CDBR

XDB2

Program

Memory

Data

Memory

IP-Bus

Interface

External

Bus

Interface

N 3

PROGRAM

CONTROLLER

INSTRUCTION

DECODER

LOOPING

UNIT

INTERRUPT

UNIT

PC LA LA2

HWS FIRA FISR

SR

LC LC2

OMR

2nd Data Access:

XAB2 - 24 bits XDB2 - 16 bits

1st Data Access:

XAB1 - 24 bits CDBR - 32 bits

Instruction Fetch:

PAB - 21 bits PDB - 16 bits

Mapping the Architecture to DSP Algorithms

Common Operation in DSP

MAC X0, Y0, A X:( R4)+, Y1 X:( R3)+, C

Arithmetic Op 1st Read 2nd Read

TM

External Use 23

MC56F84xxx Core Improvements

New instructions, providing full 32-bit compatibility

• 32 x 32 -> 32/64 Multiply and MAC Instructions

− MAC32 - Integer Multiply-Accumulate 32 bits x 32 bits -> 32 bits

− IMPY32 - Integer Multiply 32 bits x 32 bits -> 32 bits

− IMPY64 - Integer Multiply 32 bits x 32 bits -> 64 bits

− IMPY64UU - Unsigned Integer Multiply 32 bits x 32 bits -> 64 bits

− MAC32 - Fractional Multiply-Accumulate 32 bits x 32 bits -> 32 bits

− MPY32 - Fractional Multiply 32 bits x 32 bits -> 32 bits

− MPY64 - Fractional Multiply 32 bits x 32 bits -> 64 bits

− Multi-Bit Clear-Set instruction to improve flexibility of peripheral register handling

Other features

• Bit reversed address mode for FFT algorithms

• Swap all address generation unit registers with shadowed registers to reduce interrupt context switch latency

TM

External Use 24

• Continuous ( Analog) Expression

• Difference ( digital ) Expression

-

+

Command Xi(t)

Feedback Xf(t) Output M(t)

M(t) = Kp*e(t) + Ki*e(t)dt + Kd * ---- e(t) d dt

e(t) = Xi(t) – Xf(t) ----- (1)

----- (2)

n m(n) = Kp e(n) + Ki e(i) t + Kd ----------------

t e(n) – e(n-1)

i=0

m(n)= m(n-1) + Kp [e(n)-e(n-1)] + Ki e(n) t + Kd [---------------- - ------------------- ] e(n) – e(n-1)

t t

e(n-1) – e(n-2)

- (3)

- (4)

Where -- e(t): Error signal; Kp: Proportional Gain; Ki: Integral Gain; Derivative Gain

Control Law Processor - PID Controller (Proportional-Integral-Derivative)

TM

External Use 25

• Any Control Algorithm being converted to digital world is the digital filter

• Digital Signal Controller is Specialized microprocessor whose architecture contains a core engine capable of competitively performing both microcontroller and digital signal processor functionalities

X(n)

X(n-1)

X(n-2)

X(n-3) X(n-4)

X(n-5)

X(n-6)

X(n-7)

r0

X(n)

X(n-1)

X(n-2)

X(n-3)

X(n-4)

X(n-5)

X(n-6)

X(n-7)

r0

X memory

C(0)

C(1)

C(2)

C(3)

C(4)

C(5)

C(6)

C(7)

X memory

r3

A/D Samples:

FIR equation: inXiCnYN

i

*1

0

Digital Control Algorithms Accessing Coefficients & Samples

TM

External Use 26

Freescale DSC Roadmap

Future

Available

Planned

Announced

Proposed

Perf

orm

ance

MC56F824x– 60MHz

48K Flash

Ultra-Hi Res PWM,

UHS ADC, XBar

MC56F824x/5x

56F847xx – 100MHz 32-bit Core

256K Flash

DMA, UHS ADC, Ultra-Hi Res

PWM, XBar, DAC, ACMP, CAN

MC56F84xxx

50MHz

64K Flash

Ultra-Hi Res PWM

UHS ADC, Xbar, DAC,

ACMP, CAN

MC56F82xxx

MC56F825x – 60MHz

64K Flash

Ultra-Hi Res PWM,

UHS ADC, XBar

56845xx – 80MHz 32-bit Core

256K Flash

DMA, UHS ADC, Ultra-Hi Res

PWM, XBar, DAC, ACMP, CAN

56F844xx – 60MHz 32-bit Core

64K Flash

DMA, UHS ADC, Hi Res PWM,

Xbae, ACMP, CAN

MC56F802x/3x

MC56F803x – 32MHz

Hi Res PWM, CAN, ADC,

DAC, ACMP

MC56F802x – 32MHz

Hi Res PWM, ADC, DAC,

ACMP MC56F801x

MC56F801x – 32MHz

Hi Res PWM, ADC

25MHz

Low power

Small Flash Blocks

UHS ADC, Hi Res PWM

MC56F80xxx

150MHz 32-bit Core

512K Flash

Dual Core (DSC+M4)

FPU

MC56F85xxx

New

MC56F800x

MC56F800x – 32MHz

Hi Res PWM, ADC, PGA,

ACMP

MC56F83xx

MC56F83xx – 60MHz

48 - 256K Flash

Large capacity

New

TM

External Use 27

New Freescale DSC Products

32pin 44 pin 48pin 64pin 80pin 100pin

Inte

gra

tion

60MHz - Motor Control

100MHz - Digital Power

50MHz Flash / 100MHz SRAM

50MHz

56F827x

48K Flash

56F827x

32K Flash

80MHz - Digital Power

80MHz – Dual Motor Control

56F827x

48K Flash

56F827x

32K Flash

56F827x

64K Flash

56F827x

48K Flash

56F827x

32K Flash

56F827x

64K Flash

56F827x

48K Flash

56F827x

32K Flash

56F827x

16K Flash 56F823x

16K Flash

56F827x

64K Flash

56F827x

64K Flash

QFN LQFP LQFP

LQFP LQFP

56F8455x

64K Flash

56F8454x

64K Flash

56F8455x

96K Flash

56F8454x

96K Flash

56F8467

128K Flash

56F8465

128K Flash

56F84587

256K Flash

56F84585

256K Flash

56F8444x

64K Flash

56F8444x

64K Flash

56F8446x

128K Flash

56F8445x

96K Flash 56F8445x

96K Flash

56F847x

128K Flash

56F847x

128K Flash

56F847x

256K Flash

56F847x

256K Flash

56F847x

128K Flash

56F847x

256K Flash

Microcontrollers Based on 32-bit Hawk 56800EX core in Freescale’s 90nm TFS

- Starting below $1.00

- Cost & Performance optimized for ….

-Advanced control loop algorithm development

-And critical high speed timing applications

- Including

-Advanced Motor Control (Sensorless VOC)

-Solar Inverters

-Server & Telecom Power Supplies

-UPS

-Power Adapters

-Board Level Power Supplies

-Low Cost Power Line Modem

-And much more………..

TM

External Use 28

56800EX Hawk V3

100MHz

Core

• 56800EX Hawk V3 @ 100MHz supporting fractional arithmetic with 4 ACC, a pipeline depth of 8 cycles, separate program and data memory maps, nested looping, and a superfast interrupt far outpacing any competitive core on the market.

System

• Intermodule Cross-Bar directly connecting any input and/or output with flexibility for additional logic functions (AND/OR/XOR/NOR)

• DMA controller for reduced core intervention when shifting data from peripherals

• Memory resource protection unit to ease safety certification

Timers

• eFlexPWM – Freescale’s most advance timer for Digtial Power Conversion with up to 8ch and 312pico-sec resolution, supported by 4 independent time bases, with half cycle reloads for increased flexibility and best in class performance

• NanoEdge placer to implement fractional delays

Analog

• 2x12-bit high-speed ADCs each with 330ns conversion rates

• 16 ch 16b SAR ADC that enables external sensors inputs and accurate system measurements

• 4 analog comparators with integrated 6-bit DACs that can enable emergency shutdown of the PWMs

• Integrated PGAs to increase the accuracy of ADC conversions on small voltages and currents

4 ch DMA

Memory

Resource

Protection

Program

Flash

up to 256KB

SRAM

up to 32KB

FlexMemory

32KB Flash

or 2KB

EEPROM

Phase Lock

Loop 8ch HS

12-bit ADC

w/PGA

Band-

Gap Ref

12bit

DAC

eFlexPWM

8ch

2x

I2C/SMBus

3xSPI

3xUARTs

System Memories

Clocks Analog Timers Communication

Interfaces

Freescale DSC

FlexCAN

4 x Analog CMP with 6bit

DAC

Inter-module

Cross Bar

NanoEdge

Placer

Program

Controller and

Hardware

Looping Unit

Data Arithmetic

Logic Unit

Enhanced On-

Chip Emulation

(EOnCE)

Address

Generation

Unit (AGU)

Bit

Manipulation

Unit

Core

Cyclic

Redundancy

Check

(CRC)

Quadrature

Decoder

Crystal OSC

8MHz OSC

32kHz OSC

16-bit Timer

8ch

16ch 16-bit SAR ADC

Others

• 5-volt tolerant I/O for cost-effective board design

• Freescale FlexMemory for simplified data storage

Packages

48LQFP, 64LQFP, 80LQFP, 100LQFP

8ch HS

12-bit ADC

w/PGA

2 x PITs

MC56F84xxx Key Features:

TM

External Use 29

56800EX Hawk V3

50/100MHz

MC56F827xx Key Features:

Core

• 56800EX Hawk V3 @ 50/100MHz supporting fractional arithmetic with 4 ACC, a pipeline depth of 8 cycles, separate program and data memory maps, nested looping, and a superfast interrupt far outpacing any competitive core on the market.

System

• Intermodule Cross-Bar directly connecting any input and/or output with flexibility for additional logic functions (AND/OR/XOR/NOR)

• DMA controller for reduced core intervention when shifting data from peripherals

• Memory resource protection unit to ease safety certification

Timers

• eFlexPWM – Freescale’s most advance timer for Digtial Power Conversion with up to 8ch and 312pico-sec resolution, supported by 4 independent time bases, with half cycle reloads for increased flexibility and best in class performance


Analog

• 2x12-bit high-speed ADCs each with 800ns conversion rates

• 4 analog comparators with integrated 6-bit DACs that can enable emergency shutdown of the PWMs

• Integrated PGAs to increase the accuracy of ADC conversions on small voltages and currents

Power Consumption:

• Less than 0.4mA/Mhz at full speed run

4 ch DMA

Memory

Resource

Protection

Program

Flash

up to 64KB

SRAM

up to 8KB

Phase Lock

Loop 8ch HS

12-bit ADC

w/PGA

Band-

Gap Ref

& Temp

Sensor

2x 12bit

DAC

eFlexPWM

8ch I2C/SMBus

2xSPI

2xUARTs

System Memories


Interfaces

Freescale DSC

msCAN


DAC

Inter-module

Cross Bar

NanoEdge

Placer

Program

Controller and

Hardware

Looping Unit

Data Arithmetic

Logic Unit

Enhanced On-

Chip Emulation

(EOnCE)

Address

Generation

Unit (AGU)

Bit

Manipulation

Unit

Core

Cyclic

Redundancy

Check

(CRC)

Crystal OSC

8MHz OSC

200kHz OSC

16-bit Timer

4ch

Others


Packages

32QFN (5x5), 32LQFP, 48LQFP, 64LQFP

8ch HS

12-bit ADC

w/PGA

2 x PITs

TM

External Use 30

56800EX Hawk V3

50MHz

MC56F823xx Key Features:

Core

• 56800EX Hawk V3 @ 50MHz supporting fractional

arithmetic with 4 ACC, a pipeline depth of 8 cycles,

separate program and data memory maps, nested

looping, and a superfast interrupt far outpacing any

competitive core on the market.

System

• Intermodule Cross-Bar directly connecting any input

and/or output with flexibility for additional logic functions

(AND/OR/XOR/NOR)

• DMA controller for reduced core intervention when

shifting data from peripherals

• Memory resource protection unit to ease safety

certification

Timers

• eFlexPWM – Freescale’s most advance timer for Digtial

Power Conversion with up to 8ch and 312pico-sec

resolution, supported by 4 independent time bases, with

half cycle reloads for increased flexibility and best in

class performance


Analog

• 2x12-bit high-speed ADCs each with 800ns conversion

rates

• 4 analog comparators with integrated 6-bit DACs that can

enable emergency shutdown of the PWMs

• Integrated PGAs to increase the accuracy of ADC

conversions on small voltages and currents

Power Consumption:

• Less than 0.5mA/Mhz at full speed run

4 ch DMA

Memory

Resource

Protection

Program

Flash

up to 32KB

SRAM

up to 4KB

Phase Lock

Loop 8ch HS

12-bit ADC

w/PGA

Band-

Gap Ref

& Temp

Sensor

2x 12bit

DAC

eFlexPWM

8ch I2C/SMBus

1xSPI

2xUARTs

System Memories


Interfaces

Freescale DSC


DAC

Inter-module

Cross Bar

NanoEdge

Placer

Program

Controller and

Hardware

Looping Unit

Data Arithmetic

Logic Unit

Enhanced On-

Chip Emulation

(EOnCE)

Address

Generation

Unit (AGU)

Bit

Manipulation

Unit

Core

Cyclic

Redundancy

Check

(CRC)

Crystal OSC

8MHz OSC

200kHz OSC

16-bit Timer

4ch

Others


Packages

32QFN (5x5), 32LQFP, 48LQFP

8ch HS

12-bit ADC

w/PGA

2 x PITs

TM

External Use 31

Kinetis V Series MCU Overview

TM

External Use 32

Kinetis V Series MCUs Motor & Power Control

• Full Kinetis MCU portfolio

compatibility targeting low cost, stand

-alone motor control, to high-

performance digital power conversion

• Optimized for processing efficiency

with performance ranging from 75 MHz

to beyond 240 MHz

• ARM architecture with best-in-class,

high speed capture and control

peripherals for motor control and

power management applications

• Enablement and tools built around

reducing customer development time

and cost, whilst increasing ease of use.

TM

External Use 33

Kinetis V Series

Device

Family

Core & Performance Positioning

KV1x M0+ @ 75MHz Low cost, entry level, 3 phase FOC BLDC solution,

KV2x M0+ @ 75MHz

56800EX @ 100MHz

Black box solution for Motor Control

KV3x M4 @ 100 &120MHz Mid Range solution building on Kinetis K family, Wide

memory range, Floating Point

KV4x M4 @ 150MHz High Performance, small memories, integrates DSC ADC &

PWM IP for best in class performance.

KV5x M4 @ 200MHz Large memory blocks, integrates DSC ADC & PWM IP for

best in class performance.

KV6x M4 @ 200MHz

M4 @ 100MHz

Dual core solution for multi-domain environment; M4

controlling Motor, M4 for communications, controlling house

keeping & safety tasks

KV7x M Series @ 240MHz Next generation ARM Cortex Solution. Limited internal

memory with excellent communications to external

memories.

DS

C A

DC

& P

WM

K

inetis A

DC

& P

WM

TM

External Use 34

Kinetis V Series MCUs: Scalable Solution

Core

150MHz

M4 w/ DSP & FPU

100MHz

120MHz & FPU

M4 w/DSP

75MHz M0+

Memory

256kB Flash

128 -512kB Flash

32kB Flash

Motor Control Timers

2 x 8Ch FlexTimer

2x 8ch FlexTimer

1x 6ch FlexTimer

Enhanced

Timers

12Ch eFlexPWM

w/Nano Edge

None

None

ADC

2x 240nS

2x< 1uS

2x <1uS

LQFP

PinOut

100 & 64

100, 64, 48 & 32

48 & 32

CMP

4x CMP with 6b DAC

2x CMP with 6b DAC

2x CMP with 6b DAC

DAC

1 x 12b DAC

1 x 12b DAC

1 x 12b DAC

MKV4x

150MHz

MKV3x

100/120MHz

Scalable IP according to application needs

Key IP for Control Applications

Increasing

performance and

integration

MKV1x

75MHz

TM

External Use 35

Kinetis V Series KV1x – Key Messages

Leadership Performance Enablement

From the market leader in motor control MCUs - A high performance, cost-optimized and best-in-class enabled 32-bit ARM

Cortex-M0+ MCU for low/mid range Brushless DC and PMSM Motor Control applications

• Reputation & heritage – >20 years of motor control processor development spanning multiple MCU & DSC architectures. Now includes next-generation 32-bit ARM Cortex MCUs

• Systems Expertise – Motor Control Centre of Excellence with >170 yrs of combined expertise in product development and OEM customer support. Extensive library of reference designs and software libraries covering all motor technologies

• Kinetis V Series – 6th Kinetis MCU family with KV1x as the entry point. Additional hardware & software compatible V Series families throughout 2014 with scalable performance, memory and feature integration

• Highest performance 75MHz clocked ARM Cortex M0+ MCU with hardware divide & square root blocks - combined 35% performance advantage vs. comparable ARM Cortex-M0 MCUs provides cost-reduction path for BLDC/PMSM designs.

• 2x 16-bit ADCs with 835nS conversion time – fast current and voltage phase measurement with reduced input jitter and improved control loop accuracy

• Flexible Motor Control Timers – fast, high accuracy PWM generation with integrated power factor correction or speed/position sensor measurement. 12-bit DAC & Analog Comparators reduce BOM cost and provide fast, accurate over-current/voltage protection with PWM safe state shutdown

• Freescale Tower MCU & Motor Driver modules, CodeWarrior IDE with Processor Expert and Cortex-M0+ math/motor control libraries. ARM ecosystem support

• FreeMASTER – free, run-time debugging and data visualization tool. Continual motor operation during debug. Free MCAT (Motor Control Application Tuner) plug-in simplifies the set-up and tuning of motor control algorithms

• Motor Control Toolbox – plug-in for MATLAB™/Simulink™ environments that generates initialization routines, device drivers, and includes a real-time scheduler for motor control algorithms

TM

External Use 36

Kinetis V Series KV1x MCU: Features and Benefits

Features Benefits

Cortex M0+ @75MHz Fastest Cortex M0+ in the market enables PMSM motor control with a

M0+ solution

Hardware Square Root & Divide Hardblock 26% performance improvement running math intensive applications

such as Sensorless FOC algorithms

Dual ADC Blocks @ 835nSec conversion time Capture current & voltage simultaneously for the most accurate result

4ch DMA Further improvements in performance realized through increased CPU

bandwidth-

6ch FlexTimer + 2x2ch FlexTimer Motor control PWM generation with integrated PFC, or integrated

speed sensor decoder (incremental decoder / hall sensor)

Integrated 6b DAC & CMP Reduce BOM costs with integrated components for over current over

voltage fault detection

Peripheral Interconnection ADC and CMP interconnected with PWM and PDB for real time

hardware control.

Light weight peripheral and memory configuration

Enough performance for the majority of Motor Control applications,

with the right amount of memory to fit complex motor control

algorithms

Dual Watchdog IEC60730 Compliant solution

TM

External Use 37

Key Peripherals For Digital Power

37

TM

External Use 38

Memory Capability

• Dual Harvard architecture permits as many as three simultaneous accesses to program and data memory

• Internal flash memory with security and protection to prevent unauthorized access

• Memory resource protection (MRP) unit to protect supervisor programs and resources from user programs

• Programming code can reside in flash memory during flash programming

• On-chip memory

− Up to 256 KB program/data flash memory

− Up to 32 KB dual port data/program RAM

− Up to 32 KB FlexNVM, which can be used as additional program or data flash memory

− Up to 2 KB FlexRAM, which can be configured as enhanced EEPROM (used in conjunction with FlexNVM) or used as additional RAM

Reserved

Reserved

RAM

Prog. Flash

EOnCE

Reserved

RAM

0x06BFFF

0x05FFFF

0x000000

0x1FFFFF

Program Data

Reserved

0x000000

0x003FFF

0x01DFFF

0x004000

0x060000

0x06C000

0x01E000

0x03FFFF

0x040000

0xFFFEFF

0xFFFF00

0xFFFFFF

0x01FFFF

0x020000

Reserved

Boot Flash

0x063FFF

0x064000

0x067FFF

0x068000

Reserved Data Flash 2

Peripherals

FlexRAM

Data Flash 1

0x007FFF

0x008000

0x00BFFF

0x00C000

0x00FFFF

0x010000

0x01FFFF

0x020000

TM

External Use 39

What FlexMemory is?

Main Program

Memory

FlexMemory

EEPROM:

• Eliminates external component

‒ Lower system cost

• No system resources required

‒ Easier implementation over

emulation

• High endurance

‒ Up to 10 million cycles

• High performance

‒ Fast write time = ~100 uSec

‒ Erase+write = 1.5mSec

User Configurable As…

EEPROM Data Flash

Additional Data Flash:

• Flexibility

‒ Space for future expansion needs

• Efficient

‒ Read-while-write with the main

program Flash

• High endurance data memory

Or Combination of Both

TM

External Use 40

Enhanced FlexPWM Module

• The eFlexPWM

architecture is

configurable, up to

4 sub-modules

(shown)

TM

External Use 41

eFlexPWM Sub-Module Detail

TM

External Use 42

Center-aligned PWM Example

VAL1 ($0100)

INIT ($FF00) VAL2

VAL3

($0000)

VAL4

VAL5

Ch0a

Ch0b

When the Init value is the signed negative of the Modulus value, the PWM module works in signed mode. Center-aligned operation is achieved when the turn-on and turn-off values are the same number, but just different signs.

TM

External Use 43

Edge-aligned PWM Example

VAL1 ($0100)

INIT ($FF00)

VAL2, VAL4 = $FF00

VAL5

($0000)

VAL3

All PWM-on values are set to the init value, and never changed again. Positive PWM-off values generate pulse widths above 50% duty cycle. Negative PWM-off values generate pulse widths below 50% duty cycle. This works well for bipolar waveform generation.

CH0b

CH0a

TM

External Use 44

Phase Shifted & double Switching PWMs

VAL1 ($0100)

INIT ($FF00) VAL2

VAL3

($0000)

VAL4

VAL5

PWMAx

PWMBx

In this example, both PWMs have the same duty-cycle. However, the edges are shifted relative to each other by simply biasing the compare values of one waveform relative to the other.

Alternatively, if the waveforms are generated by different sub-modules, the waveforms can be shifted by simply changing the Init value of one sub-module relative to the other.

PWMAx PWMBx

(DBLPWM)

TM

External Use 45

Dead Time Insertion

INDEP

PWMAx

PWMBx

DBLPWM DBLEN

0

1

0

0

0

0

1

1

1

1 IPOL

rising

edge

detect

falling

edge

detect

down

counter

down

counter

DTCNT0

DTCNT1

start

start

PWMAx

PWMBx

TM

External Use 46

Challenge of Controlling Resonate Converter

Original PWM New PWM

Modification to both PWM edges

PWM period requires small incremental adjustment

Initial PWM period

New PWM period

Challenge:

• Wide range of PWM switching frequency from 100KHz up to 1Mhz

• Need to make a change to the PWM period without changing the duty cycle for up to 4 channels of PWM within one period of the existing PWM

• PWM period change must be in a few nanosecond

Solution:

• High speed digital PWM plus Analog edge delay

• PWM duty cycles are calculated by high speed controller

• Special circuit is used to automatically increment the PWM period by repositioning edges

TM

External Use 47

Fractional

Delay A

Fractional

Delay B

INDEP

PWMAx

PWMBx

DBLPWM DBLEN

0

1

0

0

0

0

1

1

1

1 IPOL

rising

edge

detect

falling

edge

detect

down

counter

down

counter

DTCNT0

DTCNT1

start

start

eFlexPWM Detail Showing Inclusion of Fractional Delays

TM

External Use 48

Digital adder for frequency control

• Need to calculate the next edge position for rising and falling edges within very short period.

• Software not fast enough so need hardware adder

• Diagram shows 21 bit adder to control both edges automatically setting new comparator values after each edge has been triggered

16 bits

at IP Bus

timing

resolution

5 bits

MicroEdge

timing

resolution

16 bit + 5 bit

adder

Ideal timing

16 bits

at IP Bus

timing

resolution

5 bits

MicroEdge

timing

resolution

16 bits

at IP Bus

timing

resolution

5 bits

MicroEdge

timing

resolution

Actual timing Timer

5 bits from previous MEP calculation

PWM Period N-1

PWM

Period N

PWM

Period N

TM

External Use 49

ADC Channel Scan Modes

Once

− The ADC starts to sample just one time whether you use the START bit or by a sync pulse. This mode must be re-armed by writing to the ADCR1 register again if you want to go capture another scan

Triggered

− Sampling begins with every recognized START command or sync pulse

Loop

− The ADC continuously take samples as long as power is on and the STOP bit has not been set

Sequential Mode

− Sequential will sample SampleN one after another. Channel ANAx are sampled by ADCA and Channel ANBx are sampled by ADCB

Parallel Mode

− Simultaneous: Parallel can sample SampleN from Group1 and SampleN from Group 2 at the same time.

− Independent:: ADCA and ADCB can operate independently. At end of scan of each ADC, they generate separate interrupt request.

SYNCx

Voltage

Reference

Circuit

Controller

VREFHI

VREFLO

Scaling and Cyclic

Converter A 12 Sample/

Hold

ANA0

MUX

ANA1 ANA2 ANA3 ANB0 ANB1 ANB2 ANB3

Sequential

Mode Result Reg 0

Result Reg 1

Result Reg 2

Result Reg 3

Result Reg 5

Result Reg 7

Result Reg 6

Result Reg 4 Scaling and Cyclic

Converter B 12

Voltage

Reference

Circuit

Controller SYNCA

VRETH VREFP VREFM

ID VREFN

VREFLO

Scaling and Cyclic

Converter A0

Scaling and Cyclic

Converter A1 12

12 Sample/

Hold

ANA0

MUX

ANA1 ANA2 ANA3 ANA4 ANA5 ANA6 ANA7

Simultaneous

Mode Result Reg 0

Result Reg 1

Result Reg 2

Result Reg 3

Result Reg 5

Result Reg 7

Result Reg 6

Result Reg 4

TM

External Use 50

• Fast ADC input clock

• Integrated PGA with gain 1x, 2x, 4x

• Support multi-trigger operation

A/D Converter

>

<

HIGH

LIMIT

LOW

LIMIT

Zero Crossing Logic

ADC

OFFSET

ADC

RESULT

IRQ

Lo

gic

IRQ

RE

SU

LT

MU

X

12Bit

ADC MU

X V+

V-

Vrefl

AN0

AN1

ANx

Channel Select

Single Ended or Differential

Below

Above

PGA

Gain Setting

X1, x2, x4

…

16x

8x

8x

8x

TM

External Use 51

ADC Sampling helps to filtering the measured current - antialiasing.

Noise free ADC sampling when the power switch is not acting

ADC sample is taken at middle of PWM pulse which is equal to average Current

But second phase samples are difficult to be located in middle of PWM Pulse

PWM Period

PWM 0

PWM 1

Inductor Current I1

Sampled and Average Currents

calc.

Calculation

ADC trigger Signal

Inductor Current I2

end of scan interrupt end of scan interrupt

T1

Temp

Voltage

A/D Converters - PWM Synchronization Benefits

TM

External Use 52

A/D Converters -Example Irregular Triggers

Trigger 0 (T0) starts 1st conversion which ADC takes two conversions then wait next trigger

Trigger 1 (T1) starts 2nd conversion which ADC takes one conversion then wait next trigger

Trigger 2 (T2) starts 3rd conversion which ADC takes three conversions then generates INT

PWM 0

PWM 1

Inductor Current I1

calc.

Calculation

ADC trigger Signal

Inductor Current I2

end of scan interrupt end of scan interrupt

Temp

Voltage

T0 T1 T2 T0 T1 T2

TM

External Use 53

ADC trigger

Programmable

Delay Module

Channel List ( Select ) Registers

…

ADC

Conversion

Result

ADC

Analog

Input

PWM

Trigger Selector Timers

Comparators

…

ADC

Multiplexer Select

Control Module

Transistor

Power Stage

Energy

Source

Motor or

other Loads

ADC Start Signal T0, T1, T2, …

ADC Irregular Triggers

Sample (0) Result

Sample (1) Result

Sample (2) Result

Sample (n) Result

IN0

IN2

INn

IN3 Sample n … Sample 1 Sample 0

Sample DISn … Sample DIS1 Sample DIS0

Sample Disable Register

ADC Scan Controller

Sample SCn Sample SC1 Sample SC0

ADC Scan Control register

Sample Result

Register Address

ADC Module …

TM

External Use 54

Equivalent Circuit for A/D Loading

125 Ohm

ESD Resistor

channel mux

equiv resistance

100 Ohms

(VREFHx - VREFLx) / 2

C1

S/H

S1

1 2 3

ADC Input

1. Parasitic capacitance due to package, pin-to-pin and pin-to-package

base coupling; 1.8pF

2. Parasitic capacitance due to the chip bond pad, ESD protection devices

and signal routing; 2.04pF

3. 8 pF noise damping capacitor

4. C1 = 1.4 pF

5. S1 and S2 switch phases are non-overlapping and operate at the ADC

clock frequency

S1

S2 S2

C1 : Singled Ended Mode

2 X C1 : Differential Mode

S1

S1

C1

C1 : Singled Ended Mode

2 X C1 : Differential Mode

S1

S2

6. Equivalent input impedance, when the input is selected = ohmohmRateClockADC

12510012104.1)(

1

TM

External Use 55

ADC Current Injection Circuit

Pad

With

ESD

VSSA

VDDA

MUX

ADC

To Other Mux

VSSA

100pF -100nF

Less Than 3mA

TM

External Use 56

R2

110K

12

R3110K

12

R424.9K

12

R52.2K

12

R6

100ohm ~ 1K

1 2

R1110K

12

C1

0.1uF ~ 0.47uF

12

1nF ~ 10nF

C2

12

+- 430V

DC_Bus

TO ADC input

Close to ADC pin as possible

DC -Bus Voltage Sensing Circuit

TM

External Use 57

Design Considerations for ADC

• Assure clean power supply and reference source to improve ADC

conversion precision

• Use software calibration routine for ADC to improve ADC

conversion precision

• Simultaneous sampling mode increases sample rate of ADC and

keeps conversion synchronization for two different analog signals

• High input impedance to remove follower requirement

• Build-in clamp circuit to protect ADC from damaging by over-

voltage

• Build-in PGA to improve dynamic precision of ADC conversion

TM

External Use 58

When time-division sampling is required?

Application Case for ADC

Scan control mode helps reduce software overhead.

TM

External Use 59

Digital to Analog Converters

12-bit Resolution

Up to Two independent voltage mode DACs

2us settling time settling time when output swing from rail to rail at 3K /400pf load

Output glitch filter to eliminate switching glitches

Two output update modes

− Asynchronous – Update On-demand

− Synchronous – Update based on PIT or Timer Overflow, or PWM synch signal

Automatic waveform generation generates square, triangle and sawtooth waveforms with programmable period, update rate, and range

Software controlled power down mode

12bit

12bit

12bit

Data Register

DAC Buf

Automatic

Waveform

Generation

STEP

MAXVAL

MINVAL

12bit

12bit Data Bus

Sync-In

Vdd Auto Mode

selection

To Internal module

TM

External Use 60

Quad Timer – All DSCs

• Unique architecture with - 2x Inputs (Primary + Secondary) and 1x Output

• Powerful MUX - Primary Input, Secondary Input and Output can be connected to external pins

• Individual channel capability - Input capture trigger, Output compare, Clock source, Prescaler

• Counters are pre-loadable, Count once or repeatedly

• Master Operation - any channel can be a master that broadcasts its compare signal to the other channels. Such way they can be configured to reinitialize their counters and/or force their OFLAG output signals to predetermined values.

• Compare - The TMRCMP1/2 registers provide the compare values (up/down) for the counter. If a match occurs, the OFLAG signal can be set, cleared, or toggled (polarity is selectable). If enabled, an interrupt is generated, and the new compare value is loaded into TMRCMP1 or 2 registers from TMRCMPLD1 and 2 (as enabled).

• Capture register stores a copy of the counter’s value when an input edge (positive, negative, or both) is detected. Once a capture event occurs, no further updating of the Capture register will occur until the Input Edge Flag is cleared.

PRESCALER

MUX

CONTROL

COUNTER

TMRLOAD TMRHOLD CAPTURE TMRCMP1 TMRCMP2

CMPLD1 CMPLD2

COMPARATO

R

COMPARATO

R

MUX OFLAG

OUTPUT

INPUTS

OTHER INPUTS

STATUS &

CONTROL

DATA BUS

QTimer Channel PRESCALER

MUX

CONTROL

COUNTER


CMPLD1 CMPLD2

COMPARATO

R

COMPARATO

R

MUX OFLAG

OUTPUT

INPUTS

OTHER INPUTS

STATUS &

CONTROL

DATA BUS

QTimer Channel PRESCALER

MUX

CONTROL

COUNTER


CMPLD1 CMPLD2

COMPARATO

R

COMPARATO

R

MUX OFLAG

OUTPUT

INPUTS

OTHER INPUTS

STATUS &

CONTROL

DATA BUS

QTimer Channel

Primary Input

Secondary Input

PRESCALER

MUX

CONTROL

COUNTER


CMPLD1 CMPLD2

COMPARATOR COMPARATOR

MUX OFLAG

OUTPUT

INPUTS

OTHER INPUTS

STATUS &

CONTROL

DATA BUS

Quad-Timer Channel

Output

4x

TM

External Use 61

Quad Timer Operating Modes

0

Primary

Count

Primary

Count 1 2 3 4 5 6

Primary

Count 1 2 3 4 5 6 7 8 9 10 11

Primary

Count 1 2 3

Secondary

Primary

Count

Secondary

1 2 1 2 1 0

Prim

ary

Se

co

nd

ary Ou

tpu

t Prim

ary

Se

co

nd

ary Ou

tpu

t Prim

ary

Se

co

nd

ary Ou

tpu

t Prim

ary

Se

co

nd

ary Ou

tpu

t

Timer0 Timer1 Timer2 Timer3

Stop Mode - Counter is inert. No counting will occur

Count Mode – Counts rising or falling edges

(generating periodic interrupts, timing purposes)

Edge Count Mode – Counts rising and falling edges

(counting of simple encoder wheel)

Gated Count Mode - Counts primary input if secondary

input is high (signal width measurement)

Signed Count Mode – Counts primary input up or down based on polarity

of secondary input

Cascaded Count Mode - Input is connected to the output of

another (Great for large counts up to 264)

TM

External Use 62


Triggered Count Mode – Start/Stop count of Primary input on rising edge of Secondary input.

One-Shot Mode - Provides timing delays

(ADC acquisition of new samples until a specified period of time has passed since the PWM sync signal occurred)

Primary

Secondary

Count

Timer_Out

0 1 2 3 4 5 6

Timer starts

count

Timer stops

count

Timer starts

count

Primary

Secondary

Count

Timer_Out

0 1 2 3 4 0 1 2

LOAD = 0, CMP1 = 4Timer_Out Assertion Count = CMP1 + 1

Timer starts

count

TM

External Use 63


Fixed Period

Adjustable

Duty Cycle

Adjustable Period

Adjustable

Duty Cycle

Fixed Frequency PWM - Fixed frequency, variable duty cycle

(driving PWM amplifiers)

Variable Frequency PWM - Variable frequency and duty cycle (driving

PWM amplifiers)

Pulse Output Mode - Supports stepper motor systems

and provides change of signal frequency and number of pulses

Primary

Count 0 1 2 3 4 0

Output

Count Mode Timer is Off Timer is in Count Mode

Timer

Stopped due

to Compare

(COMP1 = 4)

Quadrature Count Mode

• Counter will decode the primary and secondary external

inputs as quadrature encoded signals

• Compare interrupts will signal commutation

TM

External Use 64

Crossbar Detail

XBAR_OUT3 XBAR_OUT4 XBAR_OUT5

XBAR_OUT9

XBAR_IN9

XBAR_OUT2 XBAR_OUT1 XBAR_OUT0

XBAR_IN4 XBAR_IN3 XBAR_IN2

XBAR_IN5 XBAR_IN6 XBAR_IN7

Window

/Sample CMPA

COUT

FAULT0 FAULT1

FAULT2 FAULT3

EXT_CLK

EXT_FORCE

EXTA

EXT_SYNC

OUT_TRIG0

OUT_TRIG1

EXTA

EXT_SYNC

OUT_TRIG0

OUT_TRIG1

EXTA

EXT_SYNC

OUT_TRIG0

OUT_TRIG1

EXTA

EXT_SYNC

OUT_TRIG0

OUT_TRIG1

Submodule

3

XBAR_OUT6

XBAR_OUT7

XBAR_OUT8

ADCA TRIGGER ADCA

SYNC_IN DAC

ADCB TRIGGER ADCB

Submodule 2

Submodule

1

Submodule

0

OR

OR

OR

OR

TB0 OUT

IN 1 0

XBAR_IN12

XBAR_OUT26

XBAR_IN10 Window

/Sample CMPB

COUT

XBAR_OUT10

XBAR_IN11 Window

/Sample CMPC

COUT

XBAR_OUT11

TB1 OUT

IN 1 0

XBAR_IN13

XBAR_OUT27

TB2 OUT

IN 1 0

XBAR_IN14

XBAR_OUT28

TB3 OUT

IN 1 0

XBAR_IN15

XBAR_OUT29

XBAR_OUT23

XBAR_OUT24 XBAR_OUT25

XBAR_OUT22 XBAR_OUT21

XBAR_OUT20

XBAR_OUT19

XBAR_IN0 VSS

VDD XBAR_IN1

XBAR_OUT15

XBAR_IN20

XBAR_IN21

XBAR_OUT18

XBAR_OUT14

XBAR_IN18

XBAR_OUT17

XBAR_OUT13

XBAR_IN17

XBAR_OUT16

XBAR_OUT12

XBAR_IN16

XBAR_IN19

Enhanced

Flex

PWM Module

Crossbar

Switch

GP

IO

MU

X

GP

IO M

UX

+

+

+

-

-

-

ANA0-7

ANB0-7

DAC0

TM

External Use 65

Inter-Module CrossBar Module Capability

Reprogrammable interconnection among control peripherals to improve system flexibility and simplify system design.

AND-OR-INV Logic

eFlexPWM

HS-CMP

Timer

Q_Decoder

I/O

PDB

Crossbar B

AND-OR-INV Logic

AND-OR-INT Logic

AND-OR-INV Logic

16

4

8

4

10

4

n

n

n

n

n

n

n

n

n

n

n

INT

DAM Req

Crossbar A

TM

External Use 66

AND-OR-INVERT Module

AND-OR-INT Output =

(0,A,~A,1) & (0,B,~B,1) & (0,C,~C,1) & (0,D,~D,1) // product term 0

| (0,A,~A,1) & (0,B,~B,1) & (0,C,~C,1) & (0,D,~D,1) // product term 1



•AOI Input Mux Configuration Register

•Boolean Function Evaluation Configuration Register

TM

External Use 67

And-OR-Invert Schematic

TM

External Use 68

Configuration Examples for the Boolean Function

Evaluation

• AND-OR-INT Output = • (PT0_AC[0] & A | PT0_AC[1] & ~A) & (PT0_BC[0] & B | PTO_BC[1] & ~B) • & (PT0_CC[0] & C | PTO_CC[1] & ~C)& (PT0_DC[0] & D | PTO_DC[1] & ~D) // product term 0

• | (PT1_AC[0] & A | PT1_AC[1] & ~A) & (PT1_BC[0] & B | PT1_BC[1] & ~B)

• & (PT1_CC[0] & C | PT1_CC[1] & ~C)& (PT1_DC[0] & D | PT1_DC[1] & ~D) // product term 1





Event Output Expression PT0 PT1 PT2 PT3

A & B A & B 0 0 0

A & B & C A & B & C 0 0 0

(A & B & C) + D A & B & C D 0 0

A + B + C + D A B C D

(A & ~B) + (~A & B) A & ~B ~A & B 0 0

TM

External Use 69

Peripherals to Trigger DMA Transfer

DMA

Triggers

(initiate DMA transfers)

Source Destination

eFlexPWM

Timers

A/D

SCI

I2C

SPI

Crossbar

Data transfers

Periphera

ls

TM

External Use 70

Inter-Module CrossBar to Trigger DMA Transfer

DMA

Triggers

(initiate DMA transfers)

Source Destination

eFlexPWM

COMPARATOR

PWM

Timer

I/O

RTC

PDB

transfers

Crossbar

Interrupt Request

TM

External Use 71

LLC Resonant Converter with Sync Rectifier

ADC

Voltage

Regulator

- +

Cr Lr

Lm

T1

T2

C1

C2

1

5

T3

T4

T

1 5

4 8

PWMA_0A/0B CMPA/B

Fault

MC56F84xxx

XBar

PWM frequency

TM

External Use 72

Peak Current Controlled Phase-Shift Full-Bridge

Slope

compensation

CMP DAC

Digital

PWM

Module

Voltage

Regulator

Inductor Current

Feedback

Voltage Feedback

-

+

Peak Current

Mode Control

MC56F82xx/84xxx

Sync PSFB

Fault

Phase shift

Compensation

TM

External Use 73

Executive Summary

Introduction

• Digital Power Control is the replacement of analog components to digital components within power control systems. Analog systems have many disadvantages that can be overcome by replacing with digital components and digital components can also bring many other advantages, such as greater control within the system and the ability to reduce reliability fluctuations.

Trends / Drivers

• Improve system flexibility–change quickly to meet market needs

• Improve systems efficiency–reduce system heat output

• Improve control–more accuracy, due to tighter system controls

• Reduce manufacturing costs–single design for product family, lower component count

• Reducing systems size, smaller chassis, smaller power supply needed

Technology

• High-resolution PWM, high speed analog-to-digital converter, digital signal process core, programmable gain amplifiers (PGA), on-chip comparators

• Enablement :

− Soft Switching technique

− Multiple-Phase interleaving Power Factor Correction

− Adaptive close loop control

TM

External Use 74

Resonant Converters

Introduction

TM

External Use 75

Switch Mode Power Supply Introduction

• We can distinguish SMPS according many parameters:

− Type of source

Voltage Source Converters, Current source Converters

− Type of conversion

DC/DC, AC/DC, AC/AC or DC/AC

− Ratio VOUT/VIN

Step Up, Step Down or Both

− Galvanic Isolation

Isolated/non-isolated

− Type of operation

Pulse with modulated, Frequency Controlled (Resonant)

TM

External Use 76

Switch Mode Power Supply Introduction

• We can distinguish SMPS according many parameters:

− Type of source

Voltage Source Converters, Current source Converters

− Type of conversion

DC/DC, AC/DC, AC/AC or DC/AC

− Ratio VOUT/VIN

Step Up, Step Down or Both

− Galvanic Isolation

Isolated/non-isolated

− Type of operation

Pulse with modulated, Frequency Controlled (Resonant)

TM

External Use 77

+ Simple design

– Higher switching looses

– Lower switching

frequencies – bulky

components

=> Resonant converters

• The semiconductor switches generate square wave voltage output

using PWM modulation - Vg

• The Vg is rectified by output rectifier and filtered by a low pass filter

• The Vo corresponds to actual duty cycle

PWM Operated Switch Mode Power Supply

TM

External Use 78

Resonant Converter Introduction

• The resonant converter employs resonant circuit between

semiconductor switches and rectifier

• The resonant circuit consist of at least one capacitor and inductor

TM

External Use 79

Resonant Converters

• There are many variants, how to implement resonant circuit

(two and three components)

• This presentation focuses on widely used combinations:

− Series resonant converter

− Parallel resonant converter

− LLC Resonant converter

All possibilities for two components resonant circuit

TM

External Use 80


LCfr

2

1

• The resonant tank impedance is frequency dependent

• Series LC (RLC) circuit features at resonant frequency fr

− The resonant tank has minimal impedance

− There is zero voltage drop on resonant tank (ideally)

− The voltage on resonant circuit components can be higher

then the input voltage

TM

External Use 81


• Zero Voltage Switching (ZVS) of MOSFET transistor

− The MOSFET transistor is switch on at zero drain-source voltage

− There are no turn on losses

TM

External Use 82


• Series Resonant Converter

− The resonant tank is connected in series with the load RL

TM

External Use 83



− The resonant tank is connected in series with the load RL

− The resonant tank creates voltage divider together with the load

TM

External Use 84



− The resonant tank creates voltage divider together with the load

− The resonant tank impedance is frequency dependent

GO VGainV

TM

External Use 85


• Series Resonant Converter (SRC) - Summary

− The SRC can run at ZVS over the resonant frequency

− At light loads it is difficult to control output voltage

− High conduction losses at high input voltage and light loads

TM

External Use 86


• Parallel Resonant Converter

− The load RL is connected in parallel to resonant circuit

TM

External Use 87


• Parallel Resonant Converter

GO VGainV

TM

External Use 88


• Parallel Resonant Converter (PRC) - Summary

− The PRC can also run at ZVS over the resonant frequency

− The PRC can work at no load condition

− High conduction losses at high input voltage and light loads

TM

External Use 89


• LLC resonant Converter

− Additional inductance is employed in resonant circuit

− The load RL is connected in parallel to this inductance

TM

External Use 90


• LLC resonant Converter

− When transformer used in LLC converter, the magnetizing inductance

and leakage inductance can be used in resonant circuit instead of

external separate inductances

− This is one of the advantages of LLC resonant converter

TM

External Use 91


• LLC Resonant Converter

− There are two resonant frequencies: first one for Lr and Cr

and second one for (Lr + Lm) and Cr

fr1

fr2

GO VGainV

TM

External Use 92


• LLC Resonant Converter – Operation at no Load

TM

External Use 93


• LLC Resonant Converter – Operation at Resonance

TM

External Use 94


• LLC Resonant Converter – Operation below Resonance

TM

External Use 95


• LLC Resonant Converter – Operation above Resonance

TM

External Use 96


• LLC Resonant Converter - Summary

− The LLC resonant converter can run at ZVS in whole range of the

operating frequency (above even below resonant frequency)

− The LLC resonant converter can work at no load condition. The turn of

current can be controlled by Lm inductor

− The LLC resonant converter works at resonant frequency at nominal

input voltage

− The LLC resonant converter can operate over wide range of operating

input voltage

TM

External Use 97


• Resonant Converter Comparison

SRC PRC LLC

ZVS Operation Above fr only Above fr only Yes

Operation without

load No

Yes, but high

losses Yes

Operation at fr No (Close to fr) No (Close to fr) Yes

Operation at wide

input voltage range No, High losses No, high losses Yes

TM

External Use 98


• Operation at wide input range

− There is a requirement, that power supply must delivery output power

during one whole period, if there is mains line drop out

TM

External Use 99


• Operation at wide input range – PWM modulated Converters

− The PWM modulated converters are not able to increase gain by

changing duty cycle. Therefore the VBUS – Vmin has to small (20-30V).

− The whole energy has to by stored in DC bus capacitor

− Example of DC bus capacitor calculation

Pout = 500W

VBUS = 400V

Vmin =370V

fmin = 45Hz

FVVf

PC

BUS

962)(

2

minmin

TM

External Use 100


• Operation at wide input range – Resonant Converters

− Some resonant converters can increase gain over 1 by changing switching frequency. Therefore the VBUS – Vmin can be much higher than for PWM modulated coverters.

− Example of DC bus capacitor calculation Pout = 500W VBUS = 400V Vmin =200V fmin = 45Hz

− The DC Bus capacitor can be significantly smaller 185 F versus 962 F!!!

FVVf

PC

BUS

185)(

2

minmin

TM

External Use 101

Application Example:

Digital Control of LLC

Resonant Converter

TM

External Use 102

Digital Control of LLC Resonant Converter

• General requirements

− Powerful Core

The control loop is calculated every 5-20 s (motor control application

50 – 200 s)

− Very fast A/D Converter (better than 1s conversion, capable of parallel

conversion)

− PWM module capable of high resolution frequency and duty cycle

generatin

The resolution should be comparable to resolution of ADC measurement

It means more than 10 bits for frequencies 100 – 400 kHz

− Search in Freescale portfolio leads to DSC 56F824x/5x

These devices meet the best the requirements mentioned above

TM

External Use 103

LLC Resonant Converter – Freescale Solution Overview

• Used SMPS Topology

− Primary Side: Two Phase Interleaved PFC (Average Current Control)

− Secondary Side: Half Bridge LLC Resonant Converter with Synchronous

Rectification for 12V output

− Additional Synchronous Buck Converter for 5V output

• Fully Digital Control by Two DSCs:

− Primary Side: MC56F8013

− Secondary Side: MC56F8257

TM

External Use 104

Freescale LLC Resonant Converter - Detail Parameters

• Input voltage − 85-265Vac @ 45-65Hz

• Output voltage − 12V/41 Amps (max.)

− 5V/25 Amps (max.)

• Output Power − 500W shared by both voltage outputs. The power limit can be set individually by

SW for each voltage output.

• Communication − PM Bus communication (HW ready)

− CAN Communication (HW ready)

− Communication with PC using USB

• Full Fault Protection − Over-voltage, Over-current, over-temperature on both primary and secondary

side. Active controlled cooling

TM

External Use 105

Freescale LLC Resonant Converter - Block Diagram

105

Auxiliary

Power Supply

AC/DC DC/DC 85-265V

45-65Hz

DC-Bus

400V

2xPWM 3xADC

MC56F8013

HV daughter card

MC56F82xx

HV daughter card

SCI SCI1

I2C PM – Bus

Isolation barrier

2xPWM Isolation

2xADC

3,3V

12V 12V

12V

Isolation

DC-Bus

SCI2 Host PC SCI/USB

DC/DC 5V

2xPWM

2xPWM

3,3V

2xADC

CAN – Bus CAN

TM

External Use 106

Freescale LLC Resonant Converter - Primary Side

• PFC Topology − Two Phase Interleaved Boost Converter

• PFC Control Algorithm − Fully Digital Average Current Control by DSC MC56F8013

• Measured Quantities − Input Rectified Voltage

− Input Current

− DC Bus Voltage

− Heatsing Temperature

• Generated signals − 2x PWM signals for MOSFETs transistor (100kHz)

− 1x PWM signal for cooling fan

− 1x GPIO input relay control

• Fault Protection − HW over-current protection

− SW over-voltage/under-voltage protection

− SW over-temperature protection

TM

External Use 107

C810nf

relay2

C91UF

C1310nf

R111.0K

C710nf

L4

2x300uH / 15A

41

2 3

C1210nf

R7100K

R6100K

R9100K

L5

2x300uH / 15A

41

2 3

+3.3VA_prim

C101UF

Q3BSS138

1

23

C111UF

450V ~ 3,3V

R142.21K

relay1

450V ~ 3,3V

D2

KBU8M

+1

-4

ALT12

ALT23

GNDA GNDA

relay1

Q1FCP22N60N

1

32

Q2FCP22N60N

1

32

relay3

L3

390uH

1 2

GND

L6

390uH

1 2

R3

30

relay2

D1

MUR860

3 1

D3

MUR860

3 1

+12V_prim

D4

MUR860

3 1

TP13Ipfc+

relay3

R19

220

R4

30

R20

1.6K

TP15Ipfc

R17

220 C1947PF

R16

7.5K

R15

50M

TP14Ipfc-

GND

R18

1.6K

DCB_PosL

N

GND

Vin

PF C_Gat e_1

PF C_Gat e_2

Vdcb

PF C_Source_1

PF C_Source_2

Ipfc

+

Ipfc

-

Ipfc+

Ipfc-

Imax = 8A

3.3V @ + Imax

C170.1UF

D5

MBR0520LT 1G

R5100K

C180.1UF

PE

D6

MBR0520LT 1G

+C1656uF

D8

MBR0520LT 1G

D7

MBR0520LT 1G

D9

MBR0520LT 1G

PE

R132.21K

C15

680pF

GND

PE

R8100K

U2

276XAXH-12D

4

3

2

5

1

DCB_Pos

R12100K

+

-

U3B

MC33502DG

5

67

Relay

8 kondu na dc bus 18x31,5mm 56uF/450V

+3.3VA_prim

C141UF

Ipfc_out

R10

1.0K

U1S10K250E2

12

PE

Freescale LLC Resonant Converter - PFC Schematic

TM

External Use 108

Freescale LLC Resonant Converter -

PFC SW Implementation

• Inner current loop

− PI Controller running every 10 s

• Outer voltage Loop

− PI Controller with running every 500 s

− Optionally output power feedforward (sent from secondary side)

• Other Control Tasks

− Cooling fan control based on heatsing temperature

− Input relay control

− Communication with secondary controller

TM

External Use 109

Freescale LLC Resonant Converter - Secondary Side

• Main Converter Topology (12V Output) − Half Bridge LLC Resonant Converter with synchronous rectification

• Secondary Converter Topology (5V Output) − Synchronous Buck Converter

• Control Algorithm − Fully Digital Voltage Mode Control by DSC MC56F8257 for both converters

• Measured Quantities − 2x Output Voltage

− 2x Output Current

− Secondary Side PCB Temperature

• Generated Signals − 2x PWM signals for half bridge MOSFET transistors (50% duty cycle, 100kHz – 400kHz)

− 2x PWM signals for synchronous rectification MOSFET transistors (50% duty cycle, 100kHz – 400kHz)

− 2x PWM signals for secondary buck MOSFET transistors (500 kHz)

• Fault Protection − 2x HW over-current protection

− 2x SW over-voltage protection

− Over-temperature protection

TM

External Use 110


LLC Converter Schematic

Q6FDMS8460

14

32

5

GND_EART H

GND_EART H_SEC

C360.1UF

C370.1UF

Q10FDMS8460

14

32

5

SR GT2a

Q8FDMS8460

14

32

5

R36

ULR2-R001FT 2

2x 13nF/630V

SR GT2b

C32

680pF

2.2nF Y2

Q5

FDMS8460

14

32

5

PHB GT1

Is1-

PHB GT2

GND

PHB S1

PHB S2CAP_BANK-

C3310UF

C3410UF

C3510UF

C3810UF

C3910UF

C4010UF

D15

MUR460

21

D16

MUR460

21

2x 2.2nF Y2

GND

DCB_pos

CAP_BANK+

SR GT1a

Q7

FCP22N60N

1

32

Q9

FCP22N60N

1

32

T1

90780-087

7

5432

1 1413

1112

10

89

6Is1+

+

C54

1000UF

C4922UF

C4822UF

C4722UF +

C53

1000UF

C4622UF +

C52

1000UF

C4522UF +

C51

1000UF

C4422UF

C4322UF

C4222UF

C4122UF

+12V

GND_SEC

+12V

CAP_BANK-

CAP_BANK+

4x 470uF/16V10x 22uF/25V

R37680.0

R3812.0K

R393.3K

3.3V @ Vout1=16V

Vout1Vout1

C5022UF

L81UH

1 2 3

TM

External Use 111

L91UH

1 2 3

C7022UF

C7122UF

Is2-

[ULR2-R002]

C7222UF

Is2+

C6522UF

C6622UF

C6722UF

Q11

FDMS7670

14

32

5

R56180

R575.1K

R584.7K

3.3V @ Vout2=7V

+

C681000UF

Buck GT2

Buck GT1

+12V

+5V

Vout2

GND_SEC

+5V

D29

MBRA340T 3G

21

+

C731000UF

+

C741000UF

Q12

FDMS7670AS

14

32

5 D30

MBR0520LT 1G

2x 1500uF/6.3V1500uF/16V

D31

MBR0520LT 1G

GNDA_SEC

+3.3VA_sec

R55

ULR2-R001FT 2

TP37Is2+

TP38Is2-

Buck Source

C6922UF


Buck Converter Schematic

C760.22UF

R60

22

R63

22

TP41Buck Gat e 2

TP40Buck GT1

TP43Buck GT2

R6222K

TP42Buck Gat e 1

R6122K

Buck Gat e 1

Buck Gat e 2

GND_SECGND_SEC GND_SEC

Buck GT2

Buck GT1

MAX15019A

U11

MAX15019AASA+

VD

D1

IN_L6

BS

T2

DH3

HS4

IN_H5

GN

D7

DL8

EP

9

+12V_sec

D32

MBR0520LT 1G

D33

MBR0520LT 1G

Buck Source

GNDA_SEC

R595.1K

Is2+ Is2-

U10

MAX4173

RS+8

RS-6

OUT4

GN

D3

VCC1

NC12

NC25

NC37C75

0.1UF

TP39Is2

3.3V @ 33A

Is2

+3.3VA_sec

TM

External Use 112


Secondary Side SW Implementation

• LLC Resonant Converter

− PI Controller running every 10 ms

• Buck Converter

− PID Controller running every 10 ms

• Other task Control

− Communication with host PC

− Communication with primary controller

− Communication via PM Bus (Optional)

− Communication via CAN (Optional)

TM

External Use 113

Freescale LLC Resonant Converter - Aux. SMPS

• Auxiliary power supply to

power all circuits on both

primary and secondary side

• Topology: Flyback Converter

• Independent control by

dedicated IC (TNY275)

• Output voltage: 12V/3.3V

• Output power: 8W

TM

External Use 114

sec

R7

0

primL2

BL01RN1A1D2B

12

C30.1UF

R3

0 OHM

R6

0 OHM

C510UF

C40.1UF

C80.1UF

T1

CPH-EFD20-1S-10PD-Z

1

2

3

4

5 67

9

10

8

R8

0 OHM

D5

BZ X84C6V8LT 1G13

2

C70.1UF

R4

0 OHM

D4

1N4007

21

U2

SF H6156-2

1

23

4

R2100 OHM

+ C1100UF

C210UF

L1 BL01RN1A1D2B

1 2

D3

1N4007

21

R1100 OHM

R5

100 OHM

U1

TNY275PN

BP/M2EN/UV1

D4

S15

S26 S3

7

S48

D6

BZ X84C6V8LT 1G

13

2

D1

1N4007

2 1

D2

P6KE150A

21 +

C6 100UF

GND

DCB_pos

+15V_prim

GND_SEC

+15V_sec

+3.3V_prim

+3.3V_sec

GND_SECGND

GND

+3.3V_sec

+3.3V_prim

GND_SEC

TP6xx

TP4

xx

TP1DCB_pos

TP8GND

TP9GND

TP2+15V_sec

TP3

+15V_prim

TP5xx

TP7

xx


Aux. SMPS Schematic

R9

0 OHM

C13 0.1UFC110.1UF

C1247UF

12

C10

100UF

U3

MC33269D_3.3

NC15

GND/ADJ1

VIN4 VOUT1

2

NC28

VOUT23

VOUT36

VOUT47

D7

1N4007

2 1

TP11+3.3V_prim

C9100UF

TP10+6V_prim

+3.3V_prim

GND GND GNDGNDGNDGND

prim+3.3V_prim

R10

0 OHM

TP14+6V_sec

C17 0.1UF

D8

1N4007

2 1

C15

100UF

U4

MC33269D_3.3

NC15

GND/ADJ1

VIN4 VOUT1

2

NC28

VOUT23

VOUT36

VOUT47

C1647UF

12C18

0.1UFC14

100UF

TP15+3.3V_sec

GND_SECGND_SEC

+3.3V_sec

GND_SEC GND_SECGND_SECGND_SEC

sec+3.3V_sec

TM

External Use 115

Freescale LLC Resonant Converter – Picture Gallery

TM

External Use 116

Freescale LLC Resonant Converter – Picture Gallery

TM

© 2014 Freescale Semiconductor, Inc. | External Use

www.Freescale.com

http://www.freescale.com/

https://twitter.com/Freescale

https://twitter.com/Freescale

https://www.facebook.com/freescale

https://www.facebook.com/freescale

Date post:	06-Jun-2018
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