Power Electronic Transformer based
Three-Phase PWM AC Drives
A DISSERTATION
SUBMITTED TO THE FACULTY OF THE GRADUATE SCHOOL
OF THE UNIVERSITY OF MINNESOTA
BY
Kaushik Basu
IN PARTIAL FULFILLMENT OF THE REQUIREMENTS
FOR THE DEGREE OF
Doctor of Philosophy
Professor Ned Mohan
December, 2012
c© Kaushik Basu 2012
ALL RIGHTS RESERVED
Acknowledgements
I want to express my profound gratitude to Professor Mohan for being my advi-
sor. I really appreciate his encouragement and relentless support particularly in
difficult times. He always listened to my ideas and discussions with him led to key
insights. His commitment to teaching is an inspiration to any one like me who
aspires to be a teacher. Above all, he made me feel a friend, which I appreciate
from the bottom of my heart.
I express my heartfelt thanks to Professor Robbins for giving me an opportu-
nity to teach courses and being supportive at all times. I consider myself fortunate
to work with Professor Wollenburg during faculty workshops. I am grateful to
Professor Anderson for interesting discussions in mathematics.
I appreciate the financial support provided by Office of Naval research. I thank
Mr Dan Dobrick for the support extended in procuring components.
I would specially like to thank Mohapatra for introducing to the idea of power
electronic transformers. I am grateful to Dr Chris Henze and professor D.T.
Shahani for their time and helpful discussions during the hardware implementation
of this project.
I thank Hari, Apurva, Shanker, Rohit, Viswesh, Ruben and Ashish for their
i
help and support at various stages of my project.
I thank all my friends Arushi, Apurva, Eric, Gysler, Rashmi, Nathan, Ruben,
David, John, Ranjan, Saurav, Kartik, Srikant, Hari, Shanker, Rohit, Viswesh,
Ashish for creating a charming atmosphere in the lab.
ii
Dedication
To my parents who valued education above all.
iii
Abstract
A Transformer is used to provide galvanic isolation and to connect systems at
different voltage levels. It is one of the largest and most expensive component in
most of the high voltage and high power systems. Its size is inversely proportional
to the operating frequency. The central idea behind a power electronic transformer
(PET) also known as solid state transformer is to reduce the size of the transformer
by increasing the frequency. Power electronic converters are used to change the
frequency of operation. Steady reduction in the cost of the semiconductor switches
and the advent of advanced magnetic materials with very low loss density and high
saturation flux density implies economic viability and feasibility of a design with
high power density. Application of PET is in generation of power from renewable
energy sources, especially wind and solar. Other important application include
grid tied inverters, UPS e.t.c.
In this thesis non-resonant, single stage, bi-directional PET is considered. The
main objective of this converter is to generate adjustable speed and magnitude
pulse width modulated (PWM) ac waveforms from an ac or dc grid with a high
frequency ac link. The windings of a high frequency transformer contains leakage
inductance. Any switching transition of the power electronic converter connecting
the inductive load and the transformer requires commutation of leakage energy.
Commutation by passive means results in power loss, decrease in the frequency of
operation, distortion in the output voltage waveform, reduction in reliability and
power density.
iv
In this work a source based partially loss-less commutation of leakage energy
has been proposed. This technique also results in partial soft-switching. A series
of converters with novel PWM strategies have been proposed to minimize the
frequency of leakage inductance commutation. These PETs achieve most of the
important features of modern PWM ac drives including 1) Input power factor
correction, 2) Common-mode voltage suppression at the load end, 3) High quality
output voltage waveform (comparable to conventional space vector PWM modu-
lated two level inverter) and 4) Minimization of output voltage loss, common-mode
voltage switching and distortion of the load current waveform due to leakage in-
ductance commutation. All of the proposed topologies along with the proposed
control schemes have been analyzed and simulated in MATLAB\Simulink. A
hardware prototype has been fabricated and tested. The simulation and experi-
mental results verify the operation and advantages of the proposed topologies and
their control.
v
Contents
Acknowledgements i
Dedication iii
Abstract iv
List of Tables ix
List of Figures x
1 Introduction 1
1.1 Power electronic transformers . . . . . . . . . . . . . . . . . . . . 1
1.2 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.3 Current state of the art . . . . . . . . . . . . . . . . . . . . . . . . 6
1.3.1 dc/ac PETs . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.3.2 ac/ac PETs . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.4 The problem of leakage inductance commutation . . . . . . . . . . 9
1.4.1 Proposed solution and outline of the thesis . . . . . . . . . 13
2 Modulation 15
vi
2.1 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.2 Modulation for ac/ac topology . . . . . . . . . . . . . . . . . . . . 17
2.3 Modulation for dc/ac topology . . . . . . . . . . . . . . . . . . . . 22
3 Commutation 28
3.1 The Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4 Results 38
4.1 Experimental set up . . . . . . . . . . . . . . . . . . . . . . . . . 39
4.1.1 Power and Driver circuits . . . . . . . . . . . . . . . . . . 39
4.1.2 Control platform and Measurement card . . . . . . . . . . 41
4.1.3 High frequency transformers . . . . . . . . . . . . . . . . . 42
4.1.4 Input filter and protection circuits . . . . . . . . . . . . . . 43
4.1.5 Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . 44
4.1.6 motor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4.2 Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
4.2.1 Results for the dc/ac topology . . . . . . . . . . . . . . . . 57
5 Conclusion 64
References 67
Appendix A. PETS without common-mode voltage elimination 72
A.1 Analysis and Simulation . . . . . . . . . . . . . . . . . . . . . . . 73
A.1.1 Modulation for the dc/ac topology . . . . . . . . . . . . . 73
A.1.2 Modulation of the ac/ac converter . . . . . . . . . . . . . . 77
A.1.3 Commutation for the dc/ac topology . . . . . . . . . . . . 80
vii
A.1.4 Simulation results of dc/ac topology . . . . . . . . . . . . 87
A.1.5 Simulation results ac/ac topology . . . . . . . . . . . . . . 88
A.2 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Appendix B. Inter-winding Capacitance 94
Appendix C. A PET based on indirect modulation 97
C.1 Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
C.1.1 PWM Strategy for the Front End Converter . . . . . . . . 98
C.1.2 Isolation and Rectification . . . . . . . . . . . . . . . . . . 103
C.1.3 PWM strategy for the output inverter . . . . . . . . . . . 104
C.1.4 Simulation results . . . . . . . . . . . . . . . . . . . . . . . 107
viii
List of Tables
2.1 Switching States . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.1 Output as a function of state . . . . . . . . . . . . . . . . . . . . 32
3.2 Output as a function of state for four-step commutation . . . . . 34
4.1 Measured transformer parameters . . . . . . . . . . . . . . . . . . 43
4.2 Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
A.1 iout > 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
A.2 iout < 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
A.3 Parameters for dc/ac topology . . . . . . . . . . . . . . . . . . . . 88
A.4 Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
B.1 Measured transformer parameters . . . . . . . . . . . . . . . . . . 95
C.1 Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
ix
List of Figures
1.1 Power electronic transformers . . . . . . . . . . . . . . . . . . . . 3
1.2 Wind power application . . . . . . . . . . . . . . . . . . . . . . . 4
1.3 dc/ac single phase inverter with high frequency ac link . . . . . . 6
1.4 dc/ac three phase inverter with high frequency ac link . . . . . . . 7
1.5 PET in its simplest form . . . . . . . . . . . . . . . . . . . . . . . 9
1.6 Leakage Commutation . . . . . . . . . . . . . . . . . . . . . . . . 11
2.1 Control signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.2 Circuit diagram of ac/ac topology . . . . . . . . . . . . . . . . . . 17
2.3 Modulation with anti clockwise vectors . . . . . . . . . . . . . . . 18
2.4 Modulation with clockwise vectors . . . . . . . . . . . . . . . . . . 21
2.5 Circuit diagram of the dc/ac topology . . . . . . . . . . . . . . . . 24
2.6 Available voltage space vectors with zero common-mode voltage . 26
3.1 Finite state machine for leakage inductance commutation . . . . . 30
3.2 Circuit configurations at the various stages of commutation . . . . 31
3.3 Finite state machine for four-step commutation . . . . . . . . . . 33
3.4 Circuit configurations at the various stages of four-step commutation 36
4.1 Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
x
4.2 Simulation Result ac/ac: output waveforms . . . . . . . . . . . . 49
4.3 Experimental Result ac/ac: output waveforms . . . . . . . . . . . 49
4.4 Simulation Result ac/ac: common-mode voltage . . . . . . . . . . 50
4.5 Experimental Result ac/ac: common-mode voltage . . . . . . . . 50
4.6 Simulation Result ac/ac: input waveforms . . . . . . . . . . . . . 51
4.7 Experimental Result ac/ac: input waveforms . . . . . . . . . . . . 51
4.8 Simulation Result ac/ac: flux-balance . . . . . . . . . . . . . . . . 52
4.9 Experimental Result ac/ac: flux-balance . . . . . . . . . . . . . . 52
4.10 Simulation Result ac/ac: Leakage Commutation . . . . . . . . . . 53
4.11 Experimental Result ac/ac: Leakage Commutation . . . . . . . . 53
4.12 Simulation Result ac/ac: Leakage Commutation (Zoomed) . . . . 54
4.13 Experimental Result ac/ac: Leakage Commutation (Zoomed) . . . 54
4.14 Experimental Result ac/ac: Motor currents . . . . . . . . . . . . . 55
4.15 State of the art topology . . . . . . . . . . . . . . . . . . . . . . . 55
4.16 Experimental Result ac/ac: Comparison line voltage . . . . . . . 56
4.17 Experimental Result ac/ac: Comparison common-mode voltage . 56
4.18 State of the art topology . . . . . . . . . . . . . . . . . . . . . . . 57
4.19 Simulation Result dc/ac: output waveforms . . . . . . . . . . . . 58
4.20 Experimental Result dc/ac: output waveforms . . . . . . . . . . . 58
4.21 Simulation Result dc/ac: common-mode voltage . . . . . . . . . . 59
4.22 Experimental Result dc/ac: common-mode voltage . . . . . . . . 59
4.23 Simulation Result dc/ac: flux-balance . . . . . . . . . . . . . . . . 60
4.24 Experimental Result dc/ac: flux-balance . . . . . . . . . . . . . . 60
4.25 Simulation Result dc/ac: Leakage Commutation . . . . . . . . . . 61
xi
4.26 Experimental Result dc/ac: Leakage Commutation . . . . . . . . 61
4.27 Simulation Result dc/ac: Leakage Commutation (Zoomed) . . . . 62
4.28 Experimental Result dc/ac: Leakage Commutation (Zoomed) . . . 62
4.29 Experimental Result dc/ac: Motor currents . . . . . . . . . . . . 63
4.30 Experimental Result dc/ac: comparison line voltages . . . . . . . 63
4.31 Experimental Result dc/ac: Comparison common-mode voltage . 63
A.1 Circuit diagram of the dc/ac topology . . . . . . . . . . . . . . . . 73
A.2 Control signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
A.3 Circuit configuration a) positive b) negative states of power transfer 75
A.4 Front end inverter PWM generation . . . . . . . . . . . . . . . . . 76
A.5 Circuit diagram of the ac/ac topology . . . . . . . . . . . . . . . . 78
A.6 Front end converter PWM generation . . . . . . . . . . . . . . . . 80
A.7 Circuit configuration at four stages of commutation . . . . . . . . 83
A.8 The equivalent circuit during commutation . . . . . . . . . . . . . 84
A.9 Simulation result dc/ac: output waveforms . . . . . . . . . . . . . 89
A.10 Simulation results: Commutation process (dc/ac) . . . . . . . . . 91
A.11 Simulation results: Magnetizing current (dc/ac) . . . . . . . . . . 91
A.12 Simulation result ac/ac: output waveforms . . . . . . . . . . . . . 92
A.13 Simulation results: Input voltage and current(filtered) (ac/ac) . . 92
A.14 Simulation results: Commutation process (ac/ac) . . . . . . . . . 93
A.15 Simulation results: Magnetizing current (ac/ac) . . . . . . . . . . 93
B.1 inter-winding capacitance . . . . . . . . . . . . . . . . . . . . . . 96
B.2 Different winding structures . . . . . . . . . . . . . . . . . . . . . 96
C.1 Circuit diagram of the high frequency AC link . . . . . . . . . . . 98
xii
C.2 Front end converter PWM generation . . . . . . . . . . . . . . . . 99
C.3 Equivalent circuit of the transformer secondary . . . . . . . . . . 105
C.4 Voltage vectors produced by a three level inverter . . . . . . . . . 106
C.5 Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
C.6 Variable slope carrier and primary voltage over a subcycle . . . . 107
C.7 Simulation result: output load current . . . . . . . . . . . . . . . 109
C.8 Simulation result: common-mode voltage . . . . . . . . . . . . . . 109
C.9 Simulation result: positive dc link voltage . . . . . . . . . . . . . 109
C.10 Simulation result: input line current . . . . . . . . . . . . . . . . . 110
xiii
Chapter 1
Introduction
In this chapter the idea of power electronic transformer is introduced along with
the statement of the problem of this thesis. A number of applications of the
type of power electronic transformer discussed in this work are presented. Then
a brief review of the current state of the art is given. It has been identified that
the high frequency transformer present in these topologies has leakage inductance
and commutation of leakage energy by passive methods (snubber circuits) leads
to several disadvantages. In this thesis a number of new topologies and control
strategies have been proposed to overcome these problems. The last section of
this chapter provides an outline of this thesis.
1.1 Power electronic transformers
Transformers are used in power systems and power electronic systems to provide
galvanic isolation and to connect systems at different voltage levels. For example in
power systems a power transformer is used to connect a generator at a relatively
1
2
low voltage to a high voltage transmission line. The voltage applied across a
transformer is purely ac. The size of the transformer (one of the measure of the
size is the product of its window and cross sectional or iron area) is inversely
proportional to the frequency of the applied ac voltage waveform. The central
idea of power electronic transformers/ solid state transformers is to reduce the
size by increasing the frequency of operation. Power electronic converters are
used to change in the frequency of operation.
Power electronics used in such converters comprises of semiconductor switches
and adds to the system cost. Steady reduction in the cost of the semiconductor
switches and their availability at higher power level implies economic viability and
feasibility of power electronic transformers. The additional cost of the semicon-
ductors can be compensated by the reduction in the material (iron and copper)
cost of the transformers. The availability of superior magnetic materials like
FINEMET with low loss density and high saturation flux density implies feasi-
bility of the design of high power and high frequency transformers. Even with
very high power density due to relatively low power loss, these high frequency
transformers may have enough effective area to extract the heat. As we will see
in the application section that the transformer is one of the largest and one of
the most expensive equipment of the many power conversion systems. So use of
power electronic transformers may have a far reaching impact on the cost and the
power density of such systems.
Power electronic transformers considered in this thesis are of the form as shown
in Fig 1.1. On one side there is a dc or three phase balanced ac voltage source and
on the other side there is a three phase balanced load. In most of the applications
3
PETAc or dc voltage
source
Three phase balanced
load
Figure 1.1: Power electronic transformers
this load is an electrical machine. In this context the power electronic transformer
(PET) can be considered as a drive system with a high frequency ac link. At the
load end adjustable frequency and magnitude pulse width modulated or PWM ac
voltage is generated. In this thesis we are considering power electronic transform-
ers to be single stage with bi-directional power flow capability. This implies PET
consists of a set of semiconductor switches with a high frequency transformer.
Multi stage power conversion systems uses passive elements leading to decreased
power density, low reliability and increased power loss. Bi-directional power flow
is essential in most of the PET applications. The main objective of this thesis is
to find PETs with the following features of a modern PWM ac drives.
• High Power density.
• Flexible voltage transfer ratio.
• Galvanic isolation.
• Bi-directional Power flow.
• Single stage power conversion (no unreliable electrolytic dc capacitance).
4
• Common-mode voltage suppression, [1] [2].
• Input Power factor correction.
• High quality output voltage synthesis.
1.2 Applications
One of the most important applications of PET is in harvesting of energy from
renewable energy sources. Here a particular application is presented in details.
This application is related to the generation of electric power from wind. In the
vertical wind mills as shown in Fig 1.2, the induction generator is located in a
nacelle at the top of a tower of height 80 to 100 meters.
Figure 1.2: Wind power application
5
In most of the 1 MWwind mills the induction generator operates at a voltage of
690 volts. The power flows from the top of the tower at a very high current (of the
order of 1.5 K A) to the bottom where the required power converters are located
to convert the variable frequency ac to a 60 Hz ac and connect to the collection
grid of the wind farm at a voltage level of 34.5 KV through a heavy line frequency
power transformer. This transformer weighs a few tons. The power flowing from
the top to the bottom of the tower at high current encounters considerable amount
of ohmic loss. The heavy long copper cables also adds to the cost. One solution to
avoid this loss is to put the power transformer and the power electronic converters
at the top in the nacelle. Actually some vertical wind mills has this arrangement
too. But incorporating the very heavy power transformer in the nacelle implies
expensive construction and maintenance.
This power transformer can be replaced by PET which is much lighter and the
entire arrangement can be put into the nacelle at a much lower cost.
ac/ac PETS can find applications in grid connected inverters and also in the
generation of electric power from waves. The dc/ac PETS can be used in solar
inverters that needs very high levels to voltage boost and also isolation in order to
prevent the flow of ground leakage currents. dc/ac PETs can also find applications
in standby power supplies like UPS inverters, [3][4]..
6
1.3 Current state of the art
1.3.1 dc/ac PETs
A conventional dc/ac PET involves a three stage power conversion (dc-high fre-
quency ac-dc-adjustable ac) and requires an electrolytic capacitor that reduces
the reliability of the system. A more direct power conversion is possible. Such
systems can generally be classified as resonant and non-resonant type. Resonant
type of converters contain reactive elements and output voltage depends on load-
ing [5][6]. Non-resonant type of topologies use the more conventional PWM type
of control of adjustable speed ac drives, maintain a constant frequency of the ac
link and practically do not need any reactive element.
D
A
O
L
C
HF-TR
AVdc
0
H-bridge
H-bridge
Figure 1.3: dc/ac single phase inverter with high frequency ac link
Fig 1.3 shows the schematic of the single phase dc/ac inverter with high fre-
quency link [7][8]. It is known that when the output current and voltage are in
the same quadrant, this converter can be operated like a phase shifted full bridge
converter in order to get soft switching in most of the switches [9].
The known topology for three phase dc/ac inverter with high frequency ac
7
link is first proposed in [8], Fig 1.4. Here the input H-bridge chops the dc to a
high frequency square wave ac and the output cyclo-converter converts the high
frequency ac to a variable magnitude and frequency PWM voltage waveform. In
[10], it has been identified that as the three phase load is of inductive nature, every
time the output cyclo-converter changes its switching state the energy stored in
the leakage inductances of the transformer needs to be commutated. A source-
based commutation of the leakage energy is proposed in [10]. In [5] an auxiliary
circuit and control method has been suggested in order to get soft switching. In [4]
a carrier based PWM technique has been suggested for the output cyclo-converter.
Vdc
0H-bridge
HF-TR
3 phase-bridge
LOAD
Figure 1.4: dc/ac three phase inverter with high frequency ac link
Transition of each switching state of the output cyclo-converter requires com-
mutation of leakage energy and that results in loss in output voltage [5], distortion
in the output current and common-mode voltage switching. Also the commuta-
tion process requires a sequence of complicated switching at variable instants of
time. If the output cyclo-converter is operated with conventional space vector
PWM (CSVPWM), the output cyclo-converter changes its state six times in a
subcycle over which the average output voltage vector is synthesized.
8
1.3.2 ac/ac PETs
Conversion of single phase ac to constant frequency adjustable magnitude ac with
a high frequency transformer is described in [11] and [12]. In [13], a switching
strategy based on phase modulated converter is proposed in order to get soft
switching when the output voltage and current are in the same quadrant. Single
and three phase ac/ac converters with power electronic transformer based on
flyback or push-pull topologies with multiple power conversion stages and reactive
elements are proposed in [14],[15] and [16].
This thesis focuses on topologies that provide single stage power conversion
with bi-directional power flow capability without using any storage elements. In
a conventional multi-power stage approach, a rectifier-inverter system has an iso-
lated dc-dc converter in the dc link. This topology has a bulky and unreliable
electrolytic capacitor. Matrix converters are well known as a total silicon solution
for direct ac/ac power conversion. In literature [17, 18, 19, 20], there exist two dif-
ferent matrix converter-based approaches for three-phase ac/ac power conversion
with a high frequency ac-link.
The first approach is based on indirect modulation of the matrix converter.
The virtual dc-link is chopped to a high frequency ac and fed to the transformer by
the input converter [17],[18]. The load side converter converts the high frequency
ac to adjustable speed and magnitude three-phase ac. In the second approach,
first the input three-phase ac is chopped at a high frequency and fed to a bank
of three transformers. This can be achieved either by a full-bridge [19] or by a
push-pull [20] [21] type of configuration. In the secondary side, a matrix converter
is employed to generate output voltage from the high frequency three-phase ac.
9
1.4 The problem of leakage inductance commu-
tation
The high frequency transformer windings used in PET has leakage inductances.
Some of the switching of the power electronic converters in PET requires com-
mutation of the leakage energy leading to power loss and distortion of the output
voltage waveform [22][23]. In order to understand the problem of the leakage
inductance commutation and its adverse effects here a single stage PET in its
simplest form is considered, Fig 1.6. The input is a dc voltage source and the
inductive load can be modeled as a dc current source.
+
−
+
−
Vp
Llkgp Llkgs
High Frequency
Transformer
V
ic
Vc
I
Figure 1.5: PET in its simplest form
Note that when the primary or the source side converter switches the leak-
age inductances comes in series with the inductive load and no commutation is
10
necessary. On the other hand any switching of the secondary or the load side
converter requires change in the current flowing through the leakage inductances.
The current through an inductance can not be changed instantaneously and a
voltage needs to be applied across the inductance to bring such a change. All of
the PET topologies discussed in the previous section uses a passive clamp or a
snubber circuit to do the leakage inductance commutation. Leakage inductance
commutation with a passive clamp circuit has the following disadvantages.
• Lossy Solution: The entire leakage energy is lost during commutation.
• Each time the clamp circuit acts it applies the clamp voltage across the load.
leading to distortion of the output voltage and reduction in the quality of
the output waveform.
• Common-mode voltage switching.
• Increase in the voltage rating of the semiconductor switches. The clamp
voltage needs to be maintained at a higher voltage Vc > V , otherwise the
clamp will be active during normal operation. When the clamp is active
the turned OFF switches in the secondary converter has to block the clamp
voltage.
• The capacitor used in the clamp circuit needs to be maintained at a system
level voltage. Introduction of an electrolytic dc capacitor defeats the purpose
of using a single stage PET.
• The leakage inductance commutation requires finite amount of time, de-
pending on the amount of the current to be commutated, magnitude of the
11
leakage inductance and the clamp voltage. This implies reduction of the
frequency of operation leading to lower power density. This in a way defeats
the very purpose of using a PET at a relatively high frequency of operation.
In order to appreciate the magnitude of the problem a simple calculation is
being done. Consider a switching transition in which the load current reverses its
direction in the secondary winding. At this stage the initial current in the leakage
inductance (consider both the primary and secondary leakage inductances are
lumped together) was I and the final current must become −I. This activates the
clamp circuit. Let Vs be the secondary voltage applied at this instant of time, also
let’s assume that the primary converter is not switching at this instant of time.
Let’s also assume the turns ratio to be unity.
++
+
ic
Vc
I
L
Vs Vc
i
Figure 1.6: Leakage Commutation
Applying KVL in the secondary winding we get 1.1, solving this with initial
12
condition i(0) = I we obtain 1.2. The total time for commutation is tcom =2LI
Vc − Vs
.
In the worst case Vs = V , so in order to do commutation Vc > V , and to finish
commutation in a reasonable amount of time, without any loss of generality we
may assume Vc = 2V . So this implies the ratings of the output side converter
needs to be increased twice in order to hold the clamp circuit voltage during com-
mutation. During this time the clamp current is equal to I + i. So the amount of
energy lost in the clamp capacitor due to this transition is given in 1.3.
Ldi
dt= Vs − Vc (1.1)
i(t) = −Vc − Vs
Lt+ I (1.2)
Ec = Vc
∫ tcom
0
(i+ I)dt = 4LI2 (1.3)
Let the frequency over which the flux is balanced be f , assuming square wave
operation the peak of the magnetizing current Im is given in 1.4, where Lm is the
magnetizing inductance. Let’s assume that the number of leakage commutation
per cycle of the flux balance be n. This implies the power loss due to leakage
commutation Pl = nf4LI2. Let σ1 =Im
Iand σ2 =
L
Lm
. Using these relations
we can finally write the power loss due to the leakage inductance in terms of the
system power P = V I, 1.5.
Im =V
4Lmf(1.4)
13
Pl = n
(
σ2
σ1
)
P (1.5)
Now for the normal operation of the converter σ1 must be small (usually 1%).
From the line frequency power transformer design σ2 is also small (usually 0.01%).
The minimum value of n is 2. This implies that the loss due to leakage inductance
commutation may be significant (1 to 10 %). It is difficult to design winding
arrangements with high voltage ratings without giving rise to considerable amount
of leakage inductance. So leakage inductance commutation with passive clamp
circuits may not be a suitable solution.
1.4.1 Proposed solution and outline of the thesis
In this thesis a source based commutation strategy is proposed. Leakage energy
commutation refers to the change in the leakage inductance current when the
secondary side converter is switched. The current across an inductor is changed
by applying suitable voltage across it. In source based commutation the input
voltage source is used by properly controlling different switches. This takes care
of the power loss part of the leakage inductance commutation.
As mentioned earlier each commutation leads to distortion of the output volt-
age, common-mode voltage switching and reduction in the frequency of operation.
Complete removal of the commutation is impossible as it implies removal of the
secondary converter. In all of the previously proposed topologies, modulation or
the generation of adjustable frequency and magnitude PWM ac voltage was partly
or entirely done by switching the secondary side converter, [23]. In this thesis a
set of PET topologies are proposed where modulation is done in the primary side
14
and the secondary converter has minimal number of switching (twice over each
flux balance cycle of the transformer).
A total number of four topologies are proposed in this thesis, two for ac/ac
and the other two for dc/ac PET, [24] [25] [26] [27]. In one set of such ,PETs
leakage inductance commutation is simpler and requires less number of switching.
This set of topologies along with proposed PWM control yields all of the desirable
properties of the modern ac drive. These topologies given in Fig 2.2 and Fig 2.5,
are the focus of this thesis. The other set is discussed in the Appendix.
Chapter 2 presents a detailed discussion of the PWM techniques for the gen-
eration of the desired high quality output voltages. Source based loss- less leakage
inductance commutation is presented in Chapter 3. Chapter 4 provides various
different simulation and experimental results confirming the analytical predictions
and advantages of the proposed method.
Chapter 2
Modulation
The control of these converters is divided into two parts: Modulation and com-
mutation. Modulation refers to power transfer or generation of the pulse width
modulated or PWM adjustable magnitude and frequency voltage waveforms at
the load end. This chapters presents details of the modulation used to gener-
ate high quality output voltage along with common-mode voltage suppression for
both dc/ac and ac/ac topologies 1 .
2.1 Control
As mentioned before control of these converters is divided into two parts: mod-
ulation or the power transfer and commutation. The various control signals are
given in Fig 2.1. Modulation of this topology has two stages and controlled by the
signal S. In the first half of modulation when the signal S goes high the power
is transferred through the upper half of the secondary windings of the three high
1 parts of this chapter is taken from [27], [25].
15
16
frequency transformers. During the next half when signal S goes low, power is
transferred through the lower half of the secondary windings. Commutation hap-
pens when power flow changes from one stage to the consecutive one. During
commutation signals com high.
During each stages of modulation the required (adjustable frequency and mag-
nitude) three phase output voltages are synthesized on an average at the load ter-
minals by the input or the primary side converters. These is done over each period
of the carrier signal (with period Ts). During the but yes modulation the leakage
inductance of the transformers appears in series with the load, so the switching of
the input converters during this stage requires no commutation. The transformer
flux is balanced over one complete cycle of the signal s. Due to this in this thesis
the S signal is often referred as the flux balance signal.
Carrier
0 TS 2TS 3TS 4TS
dir
com
S
Figure 2.1: Control signals
17
2.2 Modulation for ac/ac topology
The modulation of the ac/ac topology as shown in Fig 2.2 is done using rotating
vectors. Use of these vectors leads to zero common-mode voltage at the load end.
There are two types of rotating vectors are available for modulation. When in Fig
2.1, dir signal is high counter clock wise vectors are used and clock wise vectors are
used otherwise. Here modulation due to counter clock wise vectors is presented
in details.
SaA1
A1
L1
N1
A2
B1
B2
C1
C2ScC2
HFT
ia
Ni
a
b
c
3ph-Source
Q2L2
Q1
R1
N2
N2
R2
r
Q4
Q3
L3
Y1
Ns
Y2
B1
b
B2
y
SaA1...cC2
No
3ph-Load
ir
Figure 2.2: Circuit diagram of ac/ac topology
18
The input voltages and the average output line to neutral voltages gener-
ated at the load end are given in (2.1) and (2.2) respectively. (2.3) defines the
instantaneous output voltage vector. The reference average output voltage vec-
tor is given in (2.4). Using transformer relationship (2.5) and definitions (2.6),
(2.8), (2.9) it is possible to get (2.10). When S is high VS1= Vo. This implies
Vo = N2
N1(VA1B1C1
−VA2B2C2).
V3
bca(A2B2C2)
w3V2
cab(A1B1C1)
u2
V4
Iabc
abcθ u1
(A1B1C1)
Vrefα
V1w2
cab(A2B2C2)
w1abc(A2B2C2)
u3
bca(A1B1C1)
V5
V6
Figure 2.3: Modulation with anti clockwise vectors
In Fig 2.3 VA1B1C1= u1 = 3
2Vie
jωit when switches SaA1 , SbB1 and ScC1 are
ON. When switches SbA2 , ScB2 and SaC2 are ON, −VA2B2C2= w3 = 3
2Vie
(jωit+π3).
These results can be obtained by using (2.1), (2.8) and (2.9). Combination of u1,2,3
with w1,2,3 produces six active voltage vectors V1,2..,6 (Fig 2.3) which are available
for modulation in this state (S = 1). Here, modulation is similar to that of a two
level voltage source inverter. For example, if at a particular instant of time Vref is
19
located in a sector formed by vectors V1 andV2, Vref is synthesized on an average
using these two vectors, (2.11), (2.12), (2.13). Where d1 is the fraction of time for
which V1 is applied, m is equal to(
N1
N2
)
Vo√3Vi
and α = ωot+φ−(ωit− π6). The zero
vector is obtained by the simultaneous use of u1 and w1. A mid point clamped
carrier is used and the sequence in which the vectors are applied is 0120-0210. It
is possible to show that application of these vectors results in zero common-mode
voltage (Vcm = 13(VrNo
+ VyNo+ VbNo
)).
vaNi= Vi cosωit
vbNi= Vi cos
(
ωit−2π
3
)
vcNi= Vi cos
(
ωit+2π
3
)
(2.1)
vrNo= Vo cos (ωot+ φ)
vyNo= Vo cos
(
ωot−2π
3+ φ
)
vbNo= Vo cos
(
ωot+2π
3+ φ
)
(2.2)
Vo = vrNo+ vyNo
ej2π3 + vbNo
e−j 2π3 (2.3)
Vref = vrNo+ vyNo
ej2π3 + vbNo
e−j 2π3
=3
2Voe
(jωot+φ) (2.4)
20
vR1Ns=
N2
N1(vA1Ni
− vA2Ni)
vY1Ns=
N2
N1(vB1Ni
− vB2Ni)
vB1Ns=
N2
N1(vC1Ni
− vC2Ni) (2.5)
VS1= vR1Ns
+ vY1Nsej
2π3 + vB1Ns
e−j 2π3 (2.6)
VS0= vR2Ns
+ vY2Nsej
2π3 + vB2Ns
e−j 2π3 (2.7)
VA1B1C1= vA1Ni
+ vB1Niej
2π3 + vC1Ni
e−j 2π3 (2.8)
VA2B2C2= vA2Ni
+ vB2Niej
2π3 + vC2Ni
e−j 2π3 (2.9)
VS1=
N2
N1
(VA1B1C1−VA2B2C2
) (2.10)
Vref =N2
N1(V1d1 +V2d2) (2.11)
mej(ωot+φ−[ωit−π6 ]) = d1 + d2e
j π3 (2.12)
d1 = msin
(
π3− α
)
sin π3
d2 = msinα
sin π3
(2.13)
21
Assuming the load power factor angle to be θ, the output load currents are
given in (2.14). When vector V1 is applied ia =N2
N1(ir − iy), as a is connected to
A1 and B2. Similarly during the application of V2, ia =N2
N1(ir − ib). The average
input currents during this state are given in (2.15). Using definition (2.16), the
average input current vector during this state is given by (2.17).
acb
bac cba
V3
V2
Vref
α acb−θ
Iabc
V1bac
V4
V6
V5 cba
(A1B1C1) (A2B2C2)
(A2B2C2)
(A1B1C1)(A2B2C2)
(A1B1C1)
Figure 2.4: Modulation with clockwise vectors
In the following cycle, when S is low, power is transferred through the lower
half of the secondary windings and VS0= Vo = −N2
N1(VA1B1C1
−VA2B2C2).
Vectors V1,2..,6 are used to generate −Vref . This results in flux balance. In this
state, the average input current vector is given (2.18). The average Iabc over one
complete cycle of S is 32Iomejωit i.e. in phase with the input voltage vector. This
results in input power factor correction. Clock wise vectors (Fig 2.4) are used
22
when dir signal goes low.
ir = Io cos (ωot + φ+ θ)
iy = Io cos
(
ωot−2π
3+ φ+ θ
)
ib = Io cos
(
ωot+2π
3+ φ+ θ
)
(2.14)
ia =N2
N1[(ir − iy) d1 + (ir − ib) d2]
ib =N2
N1[(iy − ib) d1 + (iy − ir) d2]
ic =N2
N1[(ib − ir) d1 + (ib − iy) d2] (2.15)
Iabc = ia + ibej 2π
3 + ice−j 2π
3 (2.16)
Iabc =3
2Iome(jωit+θ) (2.17)
Iabc =3
2Iome(jωit−θ) (2.18)
2.3 Modulation for dc/ac topology
This section presents the details of the modulation for the dc/ac topology, Fig
2.5. Similar to the ac case (2.19) defines the voltage space vector for the voltages
induced in the upper half of the secondary windings. These voltages are measured
23
with respect to the star point N formed by the mid points of the secondary
windings. Similarly (2.20) provides the definition of the voltage space vectors
formed by the voltages induced in the lower half of the secondary winding. In
(2.21) Vp refers to the voltage space vector formed by the primary side voltages
of the three high frequency transformers. N1 is the number of turns of the primary
winding of each of the transformers. N2 is the number of turns of each half of the
secondary windings. During modulation or power transfer stage we can neglect
the voltage drop in the leakage impedances of the transformer. This implies (2.22)
holds. Using (2.19), (2.20), (2.21) and (2.22) it is possible to obtain (2.23).
VS1= va1N + vb1Ne
j 2π3 + vc1Ne
−j 2π3 (2.19)
VS0= va2N + vb2Ne
j 2π3 + vc2Ne
−j 2π3 (2.20)
Vp = vA1A2 + vB1B2ej 2π
3 + vC1C2e−j 2π
3 (2.21)
va1N = −va2N =
(
N2
N1
)
vA1A2
vb1N = −vb2N =
(
N2
N1
)
vB1B2
vc1N = −vc2N =
(
N2
N1
)
vC1C2 (2.22)
VS1= −VS0
=
(
N2
N1
)
Vp (2.23)
24
+-
SA1
A1
SA2 LA
N1SA3
SA4
A2
B1
B2
C1
C2SC4
HFT
La1
Q2
Q1
a1
N2
N2
a2
ia
a
Q4
Q3
La2
bN
b2
3ph-Load
c1
SA1...C4
c2
c
nVdc
dc-source
b1
Figure 2.5: Circuit diagram of the dc/ac topology
In the first half of the modulation only the upper half of the secondary windings
conduct. For example during this stage in Fig 2.5 in phase a the switches Q1 and
Q2 are ON and Q3 and Q4 are OFF. So when S goes high as the load is considered
to be balanced and neutral point n is floating, Vo is equal to
(
N2
N1
)
Vp. Note that
in each phase the primary winding of the transformer is connected to the dc-bus
with a H-bridge. For example in phase a this bridge consists of four two quadrant
switches SA1 to SA4. In each leg the switches are controlled in a complementary
25
fashion in order to avoid short circuit of the input voltage source and interruption
of the output inductive load current. For example at any instant of time either
of the switches SA1 or SA2 is ON but they are never turned on simultaneously.
Considering this switching strategy each H bridge has four switching states. Two
of them are active. During these states the possible applied primary voltages (vp)
are +Vdc or −Vdc. Rest of the two are zero states i.e. the primary winding is short
circuited. These states are given in Table 2.1. In this analysis the positive active
state of a bridge is denoted by +, negative state is by - and zero state is by 0. As
each bridge has three different states all the three bridges can apply 27 possible
voltage combinations to the three phase load. Out of these possibilities here only
six active states are considered that leads to zero common-mode voltage at the
load terminals. For example when a phase bridge applies a positive voltage, b
phase bridge applies a negative voltage and c phase bridge applies zero voltage
the sum of the three voltages is zero. In this discussion this particular switching
state is referred as (+ − 0). This six active states produces six active voltage
vectors at the primary terminals. This vectors, scaled with
(
N2
N1
)
, is given in Fig
2.6. The state (+− 0) generates voltage vector V1. As in this state VA1A2 = Vdc,
VB1B2 = −Vdc and VC1C2 = 0, by (2.21) Vp = Vdc
√3e−j π
6 and V1 = Vp
(
N2
N1
)
.
Similarly it is possible to obtain other five active voltage vectors, Fig (2.6).
Table 2.1: Switching States
State 0 + − 0
S1 ON ON OFF OFF
S3 ON OFF ON OFF
vp 0 Vdc −Vdc 0
26
(0 +−)V3
V2
(+0−)
(000)
V4
−Vref
(−+ 0)
Vrefα
V5
(−0+)
V6
(0−+)
V1
(+ − 0)
Figure 2.6: Available voltage space vectors with zero common-mode voltage
In the first half of the power transfer the output reference voltage vector,
Vref , is synthesized by using these six active voltage vectors and the zero vectors.
This situation is similar to a two level voltage source inverter. The 6 active space
vectors divide the complex plane into six symmetrical sectors. The output voltage
vector is generated by using the two active vectors that form the sector in which
the output reference voltage is located at that particular instant of time. For
example in Fig 2.6, the reference voltage vector is synthesized on an average using
vectors V1 and V2, (2.24). The duty ratios (d1 and d2) or the fraction of time for
which these active vectors need to be applied are given in (2.25). Here m is the
modulation index and is equal toVref
Vdc
(
N2
N1
) .
During the second half of the modulation power is transferred through the
lower half of the secondary windings. During this state Vo is equal to the negative
27
of
(
N2
N1
)
Vp. So in this stage the negative of the output reference voltage vector
is generated using six available active voltage space vectors, Fig 2.6. As the three
high frequency transformers are identical the magnetizing inductances forms a
balanced three phase load at the primary side. Over one full cycle of modulation
the net average voltage vector applied to the magnetizing inductances is zero.
This results in flux balance in the cores of the three high frequency transformers.
Vref = d1V1 + d2V2 (2.24)
d1 = m sin(π
3− α
)
d2 = m sinα (2.25)
Chapter 3
Commutation
In this chapter source based commutation of leakage energy is presented in details.
The procedure for leakage inductance commutation is same for both ac/ac and
dc/ac topologies as far as the control of the secondary side converter is concerned.
The control of the primary converter is much simpler for the dc/ac topology and
can be easily extended from ac/ac case. This is the reason why in this chapter
commutation is presented exclusively for the ac/ac topology 1 .
3.1 The Procedure
At each transition of the flux balance signal S, The power flow exchanges between
the two halves of the secondary winding. Leakage inductance commutation in this
context refers to reversal of the primary leakage inductance current and exchange
of the load current between the leakage inductances of the two halves of the
secondary winding.
1 parts of this chapter is taken from [25].
28
29
Commutation is done on a per-phase basis by applying an appropriate voltage
at the transformer primary by switching the input converter and controlling the
individual igbts Q1,2,3,4, Fig 2.2.
The entire commutation process can be described by a finite state machine
(FSM). The output load currents and the the input voltages are at line frequency
ac, usually in the order of tens of Hertzs. The commutation time period is much
smaller than that of the input voltage and output current waveforms. So it is
possible to model these current and voltage waveforms as dc sources during com-
mutation.
As commutation is done on a per-phase basis, its same for all of the three
output phases. Here the commutation process is described for one such generic
output phases. Depending on the direction of load current during commutation
period and the nature of the transition of the S signal, four different cases are
possible. The commutation process with all of these four possibilities are summa-
rized in the FSM given in Fig 3.1. Inputs of this finite state machine are sign or
the direction of the load current, SGNi, and the flux balance signal S. SGNi is a
binary signal with one being positive (io > 0) and zero refers to negative current
(io < 0). The outputs of this FSM are the control signals for the four switches
Q1,2,3,4 and two other binary signals, com and Scom, respectively. An active com
indicates that the system is in the commutation stage. Scom is high when the
required primary voltage to be applied for commutation is positive. Table 3.1
gives the output signals as a function of the current state and the input signal S.
Here, the case when load current is positive and S is making a transition from
high to low is described in detail. At the initial stage of this transition S signal
30
B
C
D
E
G
F
H
A
tcom
S == 1
S == 1S == 1
S == 1
S == 1
S == 0
S == 0
S == 0
S == 0
S == 0
tp, S == 1
tsw, S == 1
tp, S == 0
tsw ,S == 0
tp, S == 0
tsw ,S == 1
tp, S == 1
tsw ,S == 0
io > 0,S == 0
S == 0
S == 0
io < 0, S == 1
io > 0,
S == 0io < 0,
S == 1
S == 1
tcom
S == 1
Figure 3.1: Finite state machine for leakage inductance commutation
was high and the converter was in modulation stage and the power was flowing
through the top half of the secondary winding, Q1 and Q2 was ON. The current
state was A. According to modulation the voltage applied by the input converter
to the primary winding was zero. We may assume at this state both ends of the
primary winding was connected to the input a phase. This stage is shown in Fig
3.2.a. Once the S makes a transition high to low as the load current is positive in
this case (SGNi=1) FSM moves to the next state B. In this state the switch that
is not conducting i.e. Q2 is switched OFF. In order to change the currents in the
leakage inductances a negative voltage is required to be applied. It takes a finite
31
amount of time for the input converter to apply the required voltage and we need
to wait in the state B for tp amount of time.
a
b
c
a
b
c
Ni
(a)
NsNo
Ni
a
b
c
a
b
c
Q1 D2No
(b)
Ni
a
b
c
a
b
c
No
Q4
(c)
Q2L2 D1
Q1i2 D2
D3 Q4
Q3 D4L3
i1
L1
L2 D1 Q2
L3 Q3 D4
D3 Q4
L1
i1
i2
+
-
e2
+Ns
i3e3
+
e1
--
Q2D1L2
Q1
D3
D4Q3L3
i3
Ns
i1
L1 D2 io
io
io
Figure 3.2: Circuit configurations at the various stages of commutation
To design the time period tp it is important to understand the switching mech-
anism of the input converter. Each leg of the input converter contains three four-
quadrant switches. Each of these bi-directional switches are implemented with
32
Table 3.1: Output as a function of state
STATE Q1 Q2 Q3 Q4 com Scom
A 1 1 0 0 0 X
B 1 0 0 0 1 S
C 1 0 1 0 1 S
D 0 0 1 0 1 S
E 0 0 1 1 0 X
F 0 0 0 1 1 S
G 0 1 0 1 1 S
H 0 1 0 0 1 S
two igbts (with anti-parallel diodes) connected in common-emitter configuration.
The switching in one leg is done using four-step commutation. This commutation
is necessary in order to avoid short circuit of input voltage sources and to ensure
a continuous path for the inductive output leg current. Switching of each of these
pair of igbts in one four-quadrant switch is controlled by a FSM as shown in Fig
3.3. The definition of outputs as a function of the inputs and the current state is
given in Table 3.2. Let Q1x and Q2x are the two igbts forming the bi-directional
switch connected to input phase x. Where x can be any of the input phases a, b
or c. The FSM of the four-step commutation has two binary inputs. Sx is the
corresponding switching signal and SGNiP is the sign of the leg current ip. The
outputs are the switching signals for the individual igbts Q1x and Q2x. The de-
tails of the four-step process and an estimation of tp is presented considering one
typical example case.
Let’s assume that during leakage inductance commutation vba is the maximum
33
A
B
C
D E 2tsw2tsw
tsw
Sx == 1
Sx == 1
Sx == 0
ip < 0
Sx == 0
Sx == 1
ip > 0
Sx == 0
Sx == 1
ip < 0, Sx == 0 ip > 0, Sx == 0
Figure 3.3: Finite state machine for four-step commutation
negative line to line voltage. Now when the Leakage commutation FSM is in
current state B, the voltage applied to the primary winding must be vba. So in
Fig 3.2 the top leg of the input converter must switch from a phase to the b phase.
This implies Sa goes from high to low and Sb does the opposite. Note that at
this instant of time the top leg current is positive (SGNiP=1). So the four-step
FSM of phase a moves from state A to B and that of b phase moves C to E. This
implies Q2a (the non conducting igbt) is switched OFF and both Q1b and Q2b
continues to be OFF. FSM of phase b waits in this state for tsw period of time,
Fig 3.4.a. This time period is designed to avoid short circuit. tsw must be more
than the absolute difference between the OFF and ON time of the igbts. After
the wait is over phase b FSM moves from state E to B by turning ON Q1b. The
34
FSM of phase a waits in the state B for 2tsw time. When FSM of phase b enters
state B both Q1a and Q1b are ON, Fig 3.4.b. Transfer of the current from phase
a to phase b depends on the sign of the voltage vab. If vab is negative the diode
D2b gets forward biased and the current transfers from phase a to b and the pole
voltage changes. But in the present case vab is positive and natural commutation
does not happen. At the end of this period the FSM for phase a moves from state
B to C by switching OFF Q1a. At this point current will transfer from phase a
to b and the igbt Q1b starts conducting. FSM of the phase b waits in state B for
another tsw amount of time before moving on to the next state A by switching ON
Q2b. This implies the total time to make this transition (change over of primary
voltage from vaa to vba) may take from 2tsw to a maximum of 3tsw.
Table 3.2: Output as a function of state for four-step commutation
STATE Q1x Q2x
A 1 1
B 1 0
C 0 0
D 0 1
E 0 0
The leakage commutation FSM after waiting tp amount of time, moves from
the current state B to the next state C by turning on the igbt Q3. As the currents
in the leakage inductances L1,2,3 can not change instantaneously, application of
negative primary voltage and zero current turn ON of switch Q3 forward biases
diode D4. This is the starting point of the actual commutation process, Fig 3.2.b.
In this analysis magnetizing currents are neglected. Diodes are considered to
35
be ideal. According to transformer relationships (3.1) and (3.2) are valid. By
KCL at the point where output load is connected we get (3.3). (3.4) and (3.5)
are obtained by applying KVL to the primary and secondary windings. Solution
of these equations leads to (3.6). This gives the rate of change of the leakage
inductance current i3. The commutation time is maximum when the output load
current is at its peak (Iopk) and the available maximum line to line voltage is at
its minimum (Vi
√3 cos π
6). The time period for which the FSM waits in the state
C is tcom, (3.7). When i3 reaches io, i2 and i1 becomes zero and −io respectively
and the commutation process comes to a natural end. After waiting for tcom
period of time in the state C it moves to the next state D by turning OFF Q1
with zero current. After waiting in this state for tsw time the FSM moves to the
state E by turning ON Q4 in zero current (ZCS). Fig. (3.2.c) shows the circuit
configuration just after the commutation process is over. Note that all of the igbts
in the secondary side converter are soft-switched.
e1
N1=
e2
N2=
e3
N2(3.1)
i1N1 − i2N2 + i3N3 = 0 (3.2)
io = i2 + i3 (3.3)
vab = L1d
dti1 + e1 (3.4)
e2 + e3 = L2d
dti2 − L3
d
dti3 (3.5)
36
(a)
(b)
(c)
D1a D2a
ipQ1a Q2a
va
vb
D1b D2b
Q2bQ1b
D1a D2a
ipQ1a Q2a
D2b
Q2b
D1a D2a
ip
va
vb
va
D1b
Q1b
vb
Q1a Q2a
D2bD1b
Q2bQ1b
Figure 3.4: Circuit configurations at the various stages of four-step commutation
d
dti3 = −
vab
(
N2
N1
)
(
L2+L3
2
)
+ 2L1
(
N2
N1
)2 (3.6)
tcom =
[
(
L2+L3
2
)
+ 2L1
(
N2
N1
)2
Vi
√3 cos π
6
(
N2
N1
)
]
Iopk (3.7)
37
Note in order to switch the input converter we need to know SGNiP. It is
possible to derive SGNiP from SGNi and the flux balance signal S, 3.8. But this
is not valid during commutation (or at the beginning of it). S must replaced in
(3.8) by a delayed version of S. The amount of delay must be between tp and
tp + tcom.
SGNiP = S • SGNi + S • SGNi (3.8)
Chapter 4
Results
In this chapter simulation and experimental results are presented. The entire
topology (both dc/ac and ac/ac) along with the proposed control is simulated
in MATLAB\Simulink. Even though both the simulation and experiments are
conducted with same set of parameters, the simulation differs from the actual
experimental set up in the following assumptions.
• For the input or primary side converters switches are assumed to be ideal.
• In the secondary side converter switches are implemented with common-
emitter connection of ideal igbts with anti parallel diodes.
• The switching of the primary converter is controlled with ideal pulses (No
intelligent commutation).
The first section describes the experimental set up and various design aspects in
relevant details. In the later section simulation results are presented along with
their experimental counterpart for a direct comparison.
38
39
4.1 Experimental set up
4.1.1 Power and Driver circuits
48 PWMCPMC3 i, 3 v
P1
P2
P3
S1
S2
S3
4 PWM
12 PWM
vi
CF ilt
LF ilt
RLoad
LLoad
Figure 4.1: Schematic
As the dc/ac topology is simpler in comparison with the ac/ac, and the for-
mer can be seen as a subset of the later, in this section details of ac/ac PET is
presented.The primary side converter can be thought of as a combination of three
40
3-phase to single phase matrix converters, Fig 4.1.
Each of these converters are implemented as a single unit, P1,P2 and P3. Each
of the legs of this unit consists of three four quadrant switches, realized by back
to back common-emitter connection of two igbts with anti parallel diodes. An
integrated power module (IPM) from Microsemi, APTGT75TDU120PG is used
to implement each leg. In the output side converter for a particular output phase
requires two bi-directional switches S1,S2 and S3. Each of these switches are
implemented with an IPM from Microsemi designated as APTGT75DU120TG.
The reverse blocking voltage rating of the input converter igbts must be more
than the peak of the input line to line voltages (40√6= 100 V). Assuming one is
to one turns ratio of the transformer windings, the voltage rating of the secondary
side converters is twice that of the input converter. The actual rating in the
presence of passive clamp circuits is double of these ratings. In the present case
this leads to a maximum rating of 400 V for the secondary side switches. The
actual data sheet rating is 1200 V. The data sheet current rating 75 A is much
higher than the actual rms currents in the experimental set up. Igbt driver 2SD
106AI from CONCEPT is used to drive each of these two igbts independently in
one bi-directional switch. Each of these igbt drivers accept digital/PWM signals
at 0-15 V level and generates an isolated bipolar ± 15 V gating pulses at a drive
power of 1 W. The average power required to drive each of this igbts can be
approximated by (4.1), where f = 5kHz is the sampling frequency, n = 2 is
the number of switching per sampling cycle, VG = 15V and Cies is the input
capacitance of the igbt (5340 pF from data-sheet), with this data PD turns out to
be only 250mW. In the driver card PCB the analog and the digital grounds are
41
kept separate. A dc supply of 15 V is provided to the driver to switch the igbts.
The delay introduced by the driver is observed to be approximately 400 ns.
PD = 2nfCiesV2G (4.1)
The gate resistance RG has an impact on the switching times of the igbts. In
this project the gate resistance is chosen to be equal to 18 Ω to provide a turn ON
time of 1200 ns and turn OFF time of 1750 ns (this includes the delay introduced
by the drivers). So the difference between ON and OFF time (550 ns) leads to
a design of tsw (the delay time in various stages of the four-step commutation of
the input converter) to be equal to 600 ns.
4.1.2 Control platform and Measurement card
The PWM signals are generated using a control platform based on a FPGA from
Xilinx, XC3S500E. All of the codes have been written using Verilog to configure
and control the FPGA. The three output load currents and the input voltages (as
these quantities are balanced, i.e. sum of them is zero at any instant of time only
two of them is required to be measured) are sensed using a measurement card.
The measurement card contains Hall effect voltage (LV25-P) and current sensors
(LA55-P) followed by Sallen Key filters with band width of 250 KHz. Actually
a low band width sensor is sufficient as the sensed signals are at a low frequency
(ten to hundreds of Hz). Also note that for the output currents only direction is
required for the leakage inductance commutation. The ADC (AD7366) used in
the control platform accepts signals in ± 10 V range and generates output as a
signed 12 bit number. The resolution used is 1 V == 8 and 1 A == 68. In order
42
to avoid zitter in the sensing of the output current direction a hysteresis loop with
a band of ± 0.25 A is digitally implemented in the Verilog code.
4.1.3 High frequency transformers
This circuit consists of three three-winding high frequency transformers. The
turns ratio is chosen to be unity. The design of these transformers are done using
area product method. The flux swing in each cycle of the S signal is not constant.
The maximum flux swing occurs when corresponding average output voltage is
peaking. The average volt-seconds applied to the transformer primary in one half
of the S signal is VoTs. This leads to the first design equation (4.2), where Ac is
the core area, Bpk is the peak flux density and N is the number of turns. The rms
current through each of the secondary windings isIorms√
2where that of the primary
current is Iorms. The effective window area is given by (4.3), where AwKw is the
effective window area and J is the current density.
Ac =Vo
2NfsBpk
(4.2)
AwKw =N
JIorms
(1 +√2) (4.3)
In this experimental set up the transformer is over designed. A FINEMET
C core (F1AH0803, F3CC series) from Hitachi is used. These cores have high
saturation flux density of 1.235 T and very low loss density of 300 kW per cubic
meter at 100 kHz and 0.2T. The number of turns used is 115. The windings are
made of copper coils of 16 AWG. The tri-filar winding structure is used in order
to get minimum leakage inductance. The various parameters of this transformer
43
are measured using LCR meter, Network analyzer (NA) and open and short cir-
cuit test (SC/OC) using a programmable AC source at 1 kHz. Results of these
measurements are given in the following table. These results are for one of the
three transformers. The leakage parameters are almost the same but there is a
large variation in the magnetizing inductance (55mH and 23mH) due to difference
in the air gap adjustment.
Table 4.1: Measured transformer parameters
Parameter LCR NA SC/OC
Lm 180mH 180mH 54mH
Llkg 5µH 10µH 32µH
Rlkg 0.5 Ω 0.55 Ω 0.69 Ω
Due to tri-filar winding arrangement these transformers have relatively low
leakage inductance but higher value of inter-winding capacitance. The series con-
nection of the two secondary winding leads to higher value of capacitance. See
Appendix, for a discussion related to the impact of different winding structures
on leakage inductance and inter-winding capacitance.
4.1.4 Input filter and protection circuits
The design of the input L-C filter is rather involved and requires an estimation
of the input current ripple which is a function of the modulation index and the
output power factor. The details of design is beyond the scope of this thesis.
One of the main objective of this project is to remove clamp or snubber circuits.
In the experimental set up passive clamp circuits are used for protection, Fig
44
4.1. The circuits remains in-active during the normal operation. It is possible
to implement intelligent protection circuits that obviates any use of unreliable
passive components like an electrolytic dc capacitor.
4.1.5 Parameters
The peak of the balanced input line to neutral voltage is set at 40√2 V (Vin) at
a frequency of 60 Hz (fi). The modulation index, m is set to 0.8. The output
voltage generated at the load end is at a frequency fo of 42 Hz. The sampling
frequency fs over which on an average the output voltage is generated is set at 5
kHz. Frequency of the S signal is 2.5 kHz. Table 4.2, provides different parameters
related to the output R-L load and input L-C filter.
Table 4.2: Parameters
Lload 30mH
Rload 16.6Ω
CF ilt 80µF
LF ilt 0.5mH
RF ilt 12Ω
In the finite state machine related to the four step commutation of the input
converter tsw is set at 600 ns. From the observed switching times (in sub section
on Power and drive circuits) it is possible to set different parameters in the FSM
controlling the leakage inductance commutation. The waiting period for the pri-
mary to switch is set at tp = 2µs. Similarly td is set to 1.5µs. In order to design
the commutation time tcom we need to do the following computation. The peak of
the fundamental component of the output voltage Vo can be computed from the
45
modulation index and Vin, 4.4. Using 4.5 it is possible to compute peak of the
output load current Io. In this particular design all of the three windings can be
assumed to be identical. An inductance of 5µH is connected in series with each
of the windings. With this addition, the effective leakage inductance Llkg of each
of the windings can estimated to equal to 10 µH. From 3.7, it is possible to get
an estimate of maximum commutation time, 4.6. tcom is set to be equal to 4 µs.
Vo =3
2Vinm = 68V (4.4)
Io =Vo
√
R2load + (2πfoLload)2
= 3.7A (4.5)
Tcom =3LlkgIo
1.5Vin
= 1.3µs (4.6)
4.1.6 motor
A four (p = 4) pole induction machine is run by this converter at ratedV
f= 3
(ratio of the peak of the line to neutral voltage to the frequency). The input
voltage applied to the converter was 20√2 V,Vin at 60 Hz. The modulation
index is set to 0.8 in order to generate peak of the fundamental component of
the output voltage Vo to be equal to 33 V. In order to apply the ratedV
f, the
output frequency fo is set at 11 Hz. The no load magnetizing current of the motor
is 2 A (peak). The induction machine was loaded with a permanent magnet dc
generator feeding a resistive load of R = 10Ω. The induced emf, e, of the generator
is given by e = Kω, where K = 1 and ω is the rotor speed in mechanical radians
per second. If we neglect slip we get ω = (2πfo)2
p. This implies induced emf is
46
approximately 34.5 V. Assuming both the dc generator and induction machine to
be loss-less and neglecting slip and stator leakage drop, the reflected component
of the rotor current can be assumed to be along the input voltage and given by
4.7. Here it is assumed that the turns ratio of the rotor to the stator winding
is unity. Combining this with the magnetizing current we get an estimate of the
output load current of the converter to be equal to 3.12 A at a frequency of 11
Hz. The measured line currents closely matches the predicted value.
I ′ =e2
1.5RVo
(4.7)
4.2 Results
Fig 4.2 and Fig 4.3 shows three output line currents along with the output line to
neutral voltage of one phase. The R-L load acts as a low pass filter and eliminates
the response due to switching frequency components. The simulated output cur-
rent waveforms have approximately a peak of 3.7 A as predicted analytically. The
experimental waveforms has a lower peak of 3.2 A. This can be attributed to the
voltage drop across the semiconductor switches. The three output line to neutral
voltages are plotted in Fig 4.4 and Fig 4.5. Common-mode voltage is obtained by
directly summing these waveforms. The common-mode voltage switches only once
in one sampling cycle (fs = 5kHz). The next result as shown in Fig 4.6 and Fig
4.7 shows input line to neutral voltage of one phase along with the corresponding
filtered input line current. This result clearly indicates input power factor correc-
tion. The input voltage to the transformer along with the magnetizing current
over one cycle of the flux balance signal S is given in Fig 4.8 and Fig 4.9. The
47
magnetizing current is obtained by summing the three winding currents (note in
the transformer all of the three windings have same number of turns). As the
magnetizing current is very small (in mili amps) its was difficult to measure it
experimentally. Although the experimental result clearly indicates flux balance.
The next set of results corresponds to leakage inductance commutation, 4.10,
Fig 4.11 and 4.12, Fig 4.13. The two secondary and primary winding currents are
plotted with the primary voltage. The secondary current waveforms are comple-
mentary to each other and composed of 50% duty cycle modulated output load
current. The primary current is the 50% duty cycle modulated chopped version
of the load current. The zoomed version of these waveforms clearly shows the ap-
plication of suitable voltage by the input converter and linear change in winding
currents at the end of each sampling cycle due to commutation. The measured
slope of the inductor currents during commutation matches with its analytical es-
timation. In experimental results at the end of leakage inductance commutation
the currents show a small overshoot. This is due to the reverse recovery of the
anti parallel diode that is turning OFF in the secondary side converter.
Fig 4.14 shows the line currents when an induction motor is driven with Vf
control along with input line to neutral voltage. The frequency and magnitude of
the measured output line currents matches with the analytical estimation of the
last section.
This topology is compared with a topology based on indirect modulation of
matrix converter, Fig 4.15. The transformer has a turns ratio of 1:2. The input
voltage and the modulation index is set in order to get the same amount of output
voltage. The transformer leakage inductances are adjusted by adding external
48
inductance to have comparable effective leakage inductance. A clamp circuit is
used for leakage inductance commutation and the output converter is operated
with dead time of 2 µS. The modulation strategy used is also indicated in the
same figure.
Fig 4.16 shows two line to neutral voltages (the second plot corresponds to the
proposed ac/dc PET) over one cycle of the S signal (the first plot). It clearly shows
8/10 glitches in the line to neutral voltage of the indirect topology in comparison
with 2 glitches in case of the proposed one. Similar observation can be made for
the common-mode voltage switching from Fig 4.31. The common-mode voltage
in this case is measured with respect to the mid point of the secondary winding.
49
0.0244 0.0369 0.0494−8
−4
0
4
8
ir
(A)
0.0244 0.0369 0.0494−8
−4
0
4
8
iy
(A)
0.0244 0.0369 0.0494−8
−4
0
4
8
ib
(A)
0.0244 0.0369 0.0494−200
−100
0
100
200
time (s)
vrN
o(V
)
Figure 4.2: Simulation Result: Three Output line currents and line to neutralvoltage of one phase
Figure 4.3: Experimental Result: Three output line currents (2A/div) and line toneutral voltage of one phase (50V/div)
50
0.0164 0.0165 0.0166−400
−200
0
200
400
vA
(V)
0.0164 0.0165 0.0166−400
−200
0
200
400
vB
(V)
0.0164 0.0165 0.0166−400
−200
0
200
400
vC
(V)
0.0164 0.0165 0.0166−400
−200
0
200
400
time (s)
vco
m(V
)
Figure 4.4: Simulation Result: Three output line voltages and common-modevoltage
Figure 4.5: Experimental Result: Three output line voltages (100V/div) andscaled (3 times) common-mode voltage (150V/div)
51
0.0388 0.0638 0.0888−80
−40
0
40
80
va
Ni(V
)an
dia(A
)
time (s)
Figure 4.6: Simulation Result: Input line to neutral voltage and filtered inputcurrent
Figure 4.7: Experimental Result: Input line to neutral voltage (20V/div) andfiltered input current (20A/div)
52
0.0233 0.0236 0.0239
−200
0
200
vp
(V)
0.0233 0.0236 0.0239
−0.05
0
0.05
time (s)
im
(A)
Figure 4.8: Simulation Result: Primary voltage and magnetizing current
Figure 4.9: Experimental Result: Primary voltage (100V/div) and magnetizingcurrent (0.5A/div)
53
0.0208 0.0255 0.0303−8
−4
0
4
8
i3
(A)
0.0208 0.0255 0.0303−8
−4
0
4
8
i2
(A)
0.0208 0.0255 0.0303−8
−4
0
4
8
i1
(A)
0.0208 0.0255 0.0303−400
−200
0
200
400
time (s)
vp
(V)
0.0246 0.0256 0.0266−2
0
3
6
i3
(A)
0.0246 0.0256 0.0266−2
0
3
6
i2
(A)
0.0246 0.0256 0.0266−6
−3
0
3
6
i1
(A)
0.0246 0.0256 0.0266−200
−100
0
100
200
time (s)
vp
(V)
Figure 4.10: Simulation Result: Two secondary winding current, primary currentand primary voltage
Figure 4.11: Experimental Result: Two secondary winding current, primary cur-rent (2A/div) and primary voltage (100V/div)
54
0.0254 0.0256 0.0259−2
0
3
6
i3
(A)
0.0254 0.0256 0.0259−2
0
3
6
i2
(A)
0.0254 0.0256 0.0259−6
−3
0
3
6
i1
(A)
0.0254 0.0256 0.0259−400
−200
0
200
400
time (s)
vp
(V)
0.0256 0.0256 0.0256−2
0
3
6
i3
(A)
0.0256 0.0256 0.0256−2
0
3
6
i2
(A)
0.0256 0.0256 0.0256−6
−3
0
3
6
i1
(A)
0.0256 0.0256 0.0256−200
−100
0
100
200
time (s)
vp
(V)
Figure 4.12: Simulation Result: Two secondary winding current, primary currentand primary voltage
Figure 4.13: Experimental Result: Two secondary winding current, primary cur-rent (2A/div) and primary voltage (100V/div)
55
Figure 4.14: Experimental Result: output line currents (5A/div) and input lineto neutral voltage (10V/div)
PS
I1 I2
V0 V2 V0V2 V1
Figure 4.15: State of the art topology
56
Figure 4.16: Experimental Result: a) S signal b) line to neutral voltage for pro-posed topology (50V/div) c) same for the state of the art topology (50V/div)
Figure 4.17: Experimental Result: a) S signal and scaled (3times) common-modevoltage (150V/div)
57
4.2.1 Results for the dc/ac topology
Simulation and experimental results corresponding to the dc/ac topology is pre-
sented in this sub-section. The input dc bus voltage is set at 90V. The modulation
index is set (0.8) such that the peak of the output voltage is 72 V at a frequency
of 60 Hz. All other parameters are identical to the ac/ac set up. The same induc-
tion motor is run but the output frequency is set at 40 Hz maintaining the same
Vf= 3. The resistive load of the dc generator is set at 20 Ω. The state of the art
topology with which results are compared is given in Fig 4.18.
SP
Figure 4.18: State of the art topology
58
0.0142 0.025 0.0358−8
−4
0
4
8
ia
(A)
0.0142 0.025 0.0358−8
−4
0
4
8
ib
(A)
0.0142 0.025 0.0358−8
−4
0
4
8
ic
(A)
0.0142 0.025 0.0358−200
−100
0
100
200
time (s)
va
n(V
)
Figure 4.19: Simulation Result: Three Output line currents and line to neutralvoltage of one phase
Figure 4.20: Experimental Result: Three output line currents (2A/div) and lineto neutral voltage of one phase (50V/div)
59
3.65 3.8 3.95
x 10−3
−200
−100
0
100
200
va
(V)
3.65 3.8 3.95
x 10−3
−200
−100
0
100
200
vb
(V)
3.65 3.8 3.95
x 10−3
−200
−100
0
100
200
vc
(V)
3.65 3.8 3.95
x 10−3
−200
−100
0
100
200
time (s)
vco
m(V
)
Figure 4.21: Simulation Result: Three output line voltages and common-modevoltage
Figure 4.22: Experimental Result: Three output line voltages (50V/div) andscaled (3 times) common-mode voltage (100V/div)
60
6.4 6.8 7.2
x 10−3
−100
0
100
vp
(V)
6.4 6.8 7.2
x 10−3
−0.05
0
0.05
time (s)
im
(A)
Figure 4.23: Simulation Result: Primary voltage and magnetizing current
Figure 4.24: Experimental Result: Primary voltage (50V/div) and magnetizingcurrent (1A/div)
61
0.0128 0.0175 0.0222−8
−4
0
4
8
i1
(A)
0.0128 0.0175 0.0222−8
−4
0
4
8
i2
(A)
0.0128 0.0175 0.0222−8
−4
0
4
8
i3
(A)
0.0128 0.0175 0.0222−200
−100
0
100
200
time (s)
vp
(V)
0.0177 0.0182 0.0187
−3
0
3
i1
(A)
0.0177 0.0182 0.0187
−7
−2
3
i2
(A)
0.0177 0.0182 0.0187
−7
−2
3i3
(A)
0.0177 0.0182 0.0187−200
−100
0
100
200
time (s)
vp
(V)
Figure 4.25: Simulation Result: Two secondary winding current, primary currentand primary voltage
Figure 4.26: Experimental Result: Two secondary winding current, primary cur-rent (2A/div) and primary voltage (50V/div)
62
0.0179 0.0181 0.0183
−3
0
3
i1
(A)
0.0179 0.0181 0.0183
−7
−2
3
i2
(A)
0.0179 0.0181 0.0183
−7
−2
3
i3
(A)
0.0179 0.0181 0.0183−200
−100
0
100
200
time (s)
vp
(V)
0.018 0.0181 0.0182
−3
0
3
i1
(A)
0.018 0.0181 0.0182
−7
−2
3
i2
(A)
0.018 0.0181 0.0182
−7
−2
3
i3
(A)
0.018 0.0181 0.0182
−100
0
100
time (s)
vp
(V)
Figure 4.27: Simulation Result: Two secondary winding current, primary currentand primary voltage
Figure 4.28: Experimental Result: Two secondary winding current, primary cur-rent (2A/div) and primary voltage (50V/div)
63
Figure 4.29: Experimental Result: output line currents (5A/div) and input lineto neutral voltage (100V/div)
Figure 4.30: Experimental Result: a) S signal b) line to neutral voltage for pro-posed topology (50V/div) c) same for the state of the art topology (50V/div)
Figure 4.31: Experimental Result: a) S signal and scaled (3times) common-modevoltage (200V/div)
Chapter 5
Conclusion
Power electronic transformers, considered in this thesis are single stage with bi-
directional power flow capability. The main objective of these converters is to
generate high quality adjustable frequency and magnitude ac form a ac or a dc
grid.
Due to the presence of leakage inductances it is necessary to commute the
leakage energy when the secondary/load side converter is switched. To avoid
commutation using a passive clamp/snubber circuit, in this thesis a source based
commutation technique has been proposed. This results in the conservation of
leakage energy and reduction in the auxiliary circuits leading to higher efficiency,
reliability and power density. The commutation process results in soft switching
of the output side converters but requires multiple hard switching of the primary
side converter. So this process will be meaningful when the leakage energy lost
per commutation is more than the total switching loss incurred in the process.
Even with source based commutation we can not avoid distortion in the out-
put voltage waveform. In fact during commutation when the currents in different
64
65
windings are changing the applied output voltage is zero. If the commutation is
done when modulation was actually applying a zero vector, no effect of commuta-
tion will be seen by the output load. But for this we need to withdraw the applied
voltage by the primary converter exactly at the end of each commutation. The ex-
act commutation time is variable, as it depends on the amount of the load current
and the applied voltage, so to withdraw the applied voltage we need to monitor
the current corresponding to the secondary winding that is switching off. Also
it takes finite amount of time to change the switching state in the primary side
converter, switching with four step commutation. So withdrawal of the applied
voltage exactly at the end of commutation is difficult to implement.
Also commutation takes finite amount of time, and this time is taken from
the modulation period. The total commutation time over one sampling cycle (the
period over which the output voltage is generated on an average) must be a small
fraction of sampling time in order to get good quality output voltage. So more
commutation time implies reduction in the sampling frequency.
In this context, this thesis has presented a series of power electronic transform-
ers that minimizes the frequency of leakage inductance commutation, only once
in one sampling cycle. This is achieved by shifting modulation to the primary
side converter. The topologies presented in this work also leads to common-mode
voltage suppression. Common-mode voltage is switched only once in one sampling
cycle.
In summary following advantages of the proposed topologies have been con-
firmed through the presented simulation and experimental results:
1. Common-mode voltage suppression.
66
2. Minimum number of switching transitions between the load and the trans-
former secondary windings. This implies lower distortion and loss in the
output voltage.
3. Loss less commutation of the leakage energy.
4. Zero current switching (ZCS) in all secondary side switches.
5. Input power factor correction.
6. High quality output voltage synthesis comparable to conventional space vec-
tor modulation.
These topologies with the proposed control provides a promising and com-
prehensive solution for direct ac/ac or dc/ac three phase motor drive application
with high frequency ac link. However, since the modulation for output voltage
generation is done in the input side, the circuit has more number of switches in
the input side (usually high voltage) which may be not be desirable.
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Appendix A
PETS without common-mode
voltage elimination
In this appendix two PET topologies one for dc/ac and the other for ac/ac con-
version is presented. This topologies and the proposed control results in loss-less
commutation of leakage energy along with reduced switching of the secondary
side converter. The modulation is done by the primary side converter (a two level
inverter for the dc/ac case and a matrix converter for the other topology). The
commutation employs a bi- directional switch at the primary side. The secondary
side converter along with the primary side switch, that is used only during com-
mutation are both soft switched. Here modulation and simulation results for both
of this converters are presented. As the commutation is essentially same for both
of the converters the commutation only for the dc/ac topology is presented 1 .
1 parts of this chapter is taken from [24], [26].
72
73
S1
S2
S3
S4
S5
S6
O
Q
S1,2,3,4,5,6
3 phase load
Q4
Q3
Q1
Q2Lp
A
B
C
c
b
a
−0.5Vdc
0.5Vdc
iA
n
n′ n′′
Ls1
Ls2
Figure A.1: Circuit diagram of the dc/ac topology
A.1 Analysis and Simulation
A.1.1 Modulation for the dc/ac topology
The basic operation of this converter as shown in Fig A.1 is divided into two parts:
power transfer and commutation. Fig A.2 shows the different control signals that
govern these two modes over one cycle of operation. The signal PT refers to power
transfer mode. The complement of PT is CT and it refers to commutation.
The following analysis refers to the output converter for phase-A. Over one
74
cycle, the signal BASIC has two states: positive and negative. These states are
denoted by P and N in Fig A.2. During the positive state, switches Q1 and Q2
are ON and power is transferred through the upper half of the secondary winding.
During the negative state, switches Q3 and Q4 are ON and power is transferred
through the lower half of the secondary winding. The star point of the primary
windings (n) and the mid-point (O) of the input dc bus is connected with a four
quadrant switch Q, (Fig A.1). During the power transfer mode the switch Q is
turned OFF in order to prevent the flow of common-mode current.
P N
0 TS 2TS
PT
CT
BASIC
Carrier
NP1
NP2
PN1
PN2
Figure A.2: Control signals
In this topology, the output three-phase load appears to be in parallel with
the star-connected magnetizing inductances seen from the primary side as shown
in Fig A.3. During the positive half of the power transfer interval, the required
output voltage vector is generated on an average by switching the input inverter.
75
During the other half, negative of the required output voltage vector is generated
by the input inverter. The output cyclo-converter inverts this voltage vector and
applies the correct voltage vector to the load. The net average voltage vector
applied to the magnetizing inductances is zero. So the required flux balance in
the transformer is achieved over one cycle of operation for the power transfer
mode.
b
c
A
BC
Lm
a
b
c
A
BC
Lm
a(a)
(b)
Lm
Lm
Lm
Lm
Figure A.3: Circuit configuration a) positive b) negative states of power transfer
The PWM signals for the input inverter during power transfer mode are gen-
erated using the triangle comparison method. This is the carrier based method
of generation of conventional space vector PWM (CSVPWM). The duty ratios of
the switches S1, S3 and S5 are given by (A.1). The duty ratios given by (A.1)
are derived using (A.2), (A.3) and (A.4). These duty ratio signals are compared
with a triangular carrier in order to generate PWM signals for the input inverter
during the power transfer mode (Fig A.4). The switches in each leg of the inverter
are switched in a complementary fashion.
The input dc bus voltage is Vdc. Np and Ns respectively denote the number of
76
1
TS0
0
S1
S3
S5
d5
d3
d1
Figure A.4: Front end inverter PWM generation
turns in the primary and each half of the secondary windings of the transformer.
In (A.2) m denotes modulation index and it is defined such that the peak of
the generated average line to neutral voltage at the output is mVdc
(
Ns
Np
)
. The
maximum value of m is1√3. The frequency of the synthesized output voltage
waveform is ω.
d1(t) = m(t) cosωt+ dcm(t)
d3(t) = m(t) cos
(
ωt− 2π
3
)
+ dcm(t)
d5(t) = m(t) cos
(
ωt+2π
3
)
+ dcm(t) (A.1)
m(t) =
+m first half of power transfer
−m next half of power transfer(A.2)
dcm(t) =1
2+
x(t)
2(A.3)
77
x(t) = mid
[
m(t) cosωt,
m(t) cos
(
ωt− 2π
3
)
,
m(t) cos
(
ωt+2π
3
)]
(A.4)
A.1.2 Modulation of the ac/ac converter
The input converter of Fig A.5 is modulated with a carrier-based PWM technique.
The input three-phase balanced ac voltage source is given by (A.5). The duty ratio
of the switch Sar is denoted by dar. As the input is connected to a voltage source,
no two switches in any leg of the input converter can be ON at the same time.
As the output load is inductive in nature, one switch in each leg of the input
converter needs to be ON at all times. These requirements result in (A.6) and
(A.7). The duty ratios of the nine switches of the input converter are given by
(A.9), (A.9), and (A.10),. Details of the offset duty ratios are given by (A.11),
(A.12), (A.13).
va(t) = Vi cosωit
vb(t) = Vi cos
(
ωit−2π
3
)
vc(t) = Vi cos
(
ωit +2π
3
)
(A.5)
dar + dbr + dcr = 1
78
Q4
Q3
Q1
Q2
High FrequencyTransformer
Q
L1
L21
L22
iR
r
y
b
R
Y
B
3 phase load
n
N
n1
n2
Say
Sar
Scb
va
vb
vc
Figure A.5: Circuit diagram of the ac/ac topology
day + dby + dcy = 1
dab + dbb + dcb = 1 (A.6)
0 ≤ dar, dbr, dcr ≤ 1
0 ≤ day, dby, dcy ≤ 1
0 ≤ dab, dbb, dcb ≤ 1 (A.7)
79
dar(t) = k(t) cosωot cosωit +Da +∆a (A.8)
dbr(t) = k(t) cosωot cos
(
ωit−2π
3
)
+Db +∆b
dcr(t) = k(t) cosωot cos
(
ωit+2π
3
)
+Dc +∆c
day(t) = k(t) cos
(
ωot−2π
3
)
cosωit+Da +∆a
dby(t) = k(t) cos
(
ωot−2π
3
)
cos
(
ωit−2π
3
)
+Db +∆b
dcy(t) = k(t) cos
(
ωot−2π
3
)
cos
(
ωit+2π
3
)
+Dc +∆c (A.9)
dab(t) = k(t) cos
(
ωot +2π
3
)
cosωit +Da +∆a
dbb(t) = k(t) cos
(
ωot +2π
3
)
cos
(
ωit−2π
3
)
+Db +∆b
dcb(t) = k(t) cos
(
ωot +2π
3
)
cos
(
ωit+2π
3
)
+Dc +∆c (A.10)
Da(t) = 0.5| cosωit|
Db(t) = 0.5
∣
∣
∣
∣
cos
(
ωit−2π
3
)∣
∣
∣
∣
Dc(t) = 0.5
∣
∣
∣
∣
cos
(
ωit+2π
3
)∣
∣
∣
∣
(A.11)
80
∆a,b,c =1− (Da +Db +Dc)
3(A.12)
k(t) =
+k first half of modulation
−k next half of modulation(A.13)
The modulation index is k. The maximum value of modulation index is 0.5.
The peak of the line to neutral of the output voltage waveform is kVin where Vin
is the peak of the input voltage waveform. The angular frequency of the output
voltage waveform is ωo. This modulation leads to input power factor correction.
The duty ratio signals are compared with a triangular carrier waveform to generate
the gating signals for the switches in the input converter (Fig A.6).
TS0
Sar
Sbr
Scr
dar + dbr
dar
0
1
Figure A.6: Front end converter PWM generation
A.1.3 Commutation for the dc/ac topology
During commutation, the current in the primary winding changes direction. Also,
in the secondary windings, the current transfers from one half to the other half.
The process of commutation occurs whenever the power transfer mode changes
81
from one state to the other (positive-to-negative or negative-to-positive). The
transformer windings have leakage inductances which are shown in Fig A.1. Lp is
the leakage inductance of the primary winding. Ls1 and Ls2 are the leakage induc-
tances present in the upper and lower half of the secondary winding respectively.
Table A.1: iout > 0
SIG Q1 Q2 Q3 Q4 S1 Q D1 D2 D3 D4
P 1 1 0 0 X 0 0 1 0 0
PN1a 1 0 0 0 0 1 0 1 0 0
PN1b 1 0 1 0 0 1 0 1 0 1
PN2 0 0 1 1 1 1 0 0 0 1
N 0 0 1 1 X 0 0 0 0 1
NP1a 0 0 1 0 1 1 0 0 0 1
NP1b 1 0 1 0 1 1 0 1 0 1
NP2 1 1 0 0 0 1 0 1 0 0
In order to change the current through these leakage inductances, appropriate
voltages need to be applied. In this topology, these voltages are applied by the
input converter. Since the input converter uses the input dc voltage, there is no
energy loss associated with the commutation process. Depending on the direction
of the output current and type of the change in the power transfer mode (positive-
to-negative or otherwise), the commutation process can be classified into four
different cases.
Here, details of one of the four cases of commutation in one phase (phase-A)
are presented. The commutation mechanism is same for all the three phases. In
the case described here,
82
Table A.2: iout < 0
SIG Q1 Q2 Q3 Q4 S1 Q D1 D2 D3 D4
P 1 1 0 0 X 0 1 0 0 0
PN1a 0 1 0 0 1 1 1 0 0 0
PN1b 0 1 0 1 1 1 1 0 1 0
PN2 0 0 1 1 0 1 0 0 1 0
N 0 0 1 1 X 0 0 0 1 0
NP1a 0 0 0 1 0 1 0 0 1 0
NP1b 0 1 0 1 0 1 1 0 1 0
NP2 1 1 0 0 1 1 1 0 0 0
1. the power transfer mode is changing from negative to positive
2. the load current is negative (iA < 0)
Tables A.1 and A.2 describe the details of the commutation process for all four
cases. Fig A.7 shows the circuit configurations during the commutation process.
Since the commutation period is much smaller with respect to the time period of
the output load current, the load can be modeled as a dc current source during
the commutation process.
Fig A.7(a) shows the power transfer through the lower half of the secondary
winding, switch Q4 and diode D3 are conducting. Note that the switch Q is
open during the power transfer mode. The commutation is done on a phase-by-
phase basis. A proper voltage needs to be applied to the primary of each phase,
independent of the other phases. This is the reason why the switch Q is turned
ON during commutation. Commutation starts when PT goes low and CT goes
high. NP1 is high during the first part of the commutation process and NP2 is
83
Q4
Q2
n′
S1
S2
Lp
Q
Oa iA
A
Q1
+0.5Vdc
−0.5Vdc
Q4
Q3
Q2
n′
S2
Lp
Q
Oa iA
A
Q1
+0.5Vdc
−0.5Vdc
Q4
Q3
Q2
n′
S1
S2
Lp
Q
Oa iA
A
Q1
+0.5Vdc
−0.5Vdc
Q3
D1
D2
D3
D4
n′′
n
D1
D2
D3
D4
Q4
Q3
Q2
n′
S2
Lp
Q
Oa iA
A
Q1
+0.5Vdc
−0.5Vdc
D4
D1
D2
D3
n
n
n
n′′
n′′n′′
D1
D2
D3
D4
S1
S1
Ls1
Ls2
Ls1
Ls2Ls2
Ls1
Ls1
Ls2
(a) State:N
(d) State: P
(b) State:NP1
(c) State:NP2
Figure A.7: Circuit configuration at four stages of commutation
high during the second stage (Fig A.2). The first stage of NP1 is referred as NP1a
in the Tables I and II. In this stage switch Q3 is turned OFF and Q is turned ON.
In this commutation, a negative voltage needs to be applied to the transformer
primary since iA < 0. So the switch S2 is turned ON. During the second stage
of NP1 (referred to as NP1b), switch Q2 is turned ON. This forward biases the
diode D1 and current is1 starts building in the upper half of the primary winding
(Fig A.7(b)). The equivalent circuit of this stage is given by the Fig A.8. Io is
the value of iA during this time.
In order to find the time required to finish the commutation process, the circuit
in Fig A.8 needs to be analyzed. In this analysis, the magnetizing component of
the transformer current is neglected. This assumption and Ampere’s law results
in (A.14). Faraday’s law implies (A.15). Application of KCL at the load terminal
84
Lp
−0.5Vdc
NsNp
Ns
Io
ip
+
-
+ +
+
- -
-
es
es
ep
Ls1
is1
is2
Ls2
Figure A.8: The equivalent circuit during commutation
gives (A.16). Applying KVL to the primary and secondary winding gives (A.17)
and (A.18) respectively. The solution of these equations leads to (A.19). So
the maximum time required to finish the commutation process (tcom) is given by
(A.20) where iomax is the peak of the sinusoidal output current. Setting tcom as
the commutation time will ensure sufficient time for commutation at all other load
conditions.
When current is1 reaches the load current iA, is2 becomes zero. Because of the
diode D3 the current is2 can not become negative and the commutation process
ends automatically. The duration for the pulse NP1 must be slightly more than
tcom. The turn-ON transition of Q and Q2 happens with zero current switching
(ZCS).
is1Ns + ipNp − is2Ns = 0 (A.14)
ep
Np
=es
Ns
(A.15)
Io = is1 + is2 (A.16)
85
0.5Vdc + ep + Lp
d
dtip = 0 (A.17)
2es + Ls1
d
dtis1 − Ls2
d
dtis2 = 0 (A.18)
d
dtis1 =
0.5Vdc
(
Ns
Np
)
(
Ls1+Ls2
2
)
+ 2Lp
(
Ns
Np
)2 (A.19)
tcom =
[
(
Ls1+Ls2
2
)
+ 2Lp
(
Ns
Np
)2
0.5Vdc
(
Ns
Np
)
]
iomax (A.20)
In the beginning of next stage (Fig A.7(c)), when NP2 goes high, switch Q4
is turned off with ZCS. In order to maintain the true bi-directional nature of
the converter, switch Q1 is turned ON (to allow for possible change in current
direction in the upcoming power transfer mode). The switch S1 is turned ON
in order to apply a positive voltage to the transformer primary. The duration of
NP1 and NP2 are same. The Q switch current becomes zero at the end of NP2.
Q is turned off at this instant with zero current (ZCS). The commutation process
is now over and the converter goes into the positive state of the power transfer
mode (Fig A.7(d)).
When CT is high, the switch Q is ON. The current through the switch Q has
two components. One of them is the sum of the reflected currents flowing through
the secondary. As the load is balanced this current is non zero only during the
commutation stage. The other component is the sum of the magnetizing currents
of all three phases. At the beginning of the commutation stage when CT goes high
86
this current is also zero. The net change in the sum of the magnetizing currents
during the commutation stage, when CT is high, is zero.
To show this let us consider a special case when load currents iA and iB are
negative and iC is positive and power transfer is changing from positive to negative
half. As the load neutral point is not connected, (A.21) holds. This particular
case implies (A.22). During the first half of the commutation when NP1 is high,
voltages applied at the primary of A and B phases are 0.5Vdc. −0.5Vdc is applied
to C phase. tA, tB and tC are the times for actual commutation. Due to (A.20),
tA is proportional to the magnitude of the instantaneous current in phase A i.e.
|iA|. tc is the duration of pulses NP1 and NP2 and is chosen such that it is more
than maximum possible commutation time (tcom).
iA + iB + iC = 0 (A.21)
|iC | = |iA|+ |iB| (A.22)
tC = tA + tB (A.23)
eA = 0.5Vdc − Lp
d
dtip (A.24)
eA =
[
1− 2(
Ls1+Ls2
2
)(
Np
Ns
)2
+ 2Lp
]
0.5Vdc (A.25)
eA = eB = −eC (A.26)
87
∆imA =tAeA
Lm
+(tc − tA)Vdc
2Lm
− tcVdc
2Lm
=tA
Lm
(eA − 0.5Vdc) (A.27)
eA is the voltage that appears across the magnetizing inductance of the trans-
former in phase A. Due to KVL, eA is given by (A.24). In this particular case this
implies (A.25). Similarly it is possible to show that (A.26) holds. The change in
the magnetizing current in phase A during this time, is given by (A.27). Lm is
the magnetizing inductance. Similar expressions can be obtained for ∆imB and
∆imC . By (A.23) and (A.26) the net change in the sum of these three magnetizing
currents during the time for which NP1 and NP2 are high is zero (A.28). The
switch Q is turned OFF with zero current.
∆imA +∆imA +∆imA = 0 (A.28)
A.1.4 Simulation results of dc/ac topology
The circuit in Fig A.1 is simulated in MATLAB/Simulink. The input dc bus
voltage, Vdc, is set to 500 V. The output is connected to a balanced three-phase
RL load. The load is star-connected. The parameters of the circuit are given in
Table A.3. The modulation index m is set at 0.25. The frequency (fs = 1Ts) at
which the output voltage is synthesized on an average is 5 kHz. The effective
frequency at which the transformer flux is balanced is 2.5 kHz. The commutation
time tcom is calculated as 16.6 µs according to (A.20). The frequency of the output
voltage is set to 45 Hz.
88
Table A.3: Parameters for dc/ac topology
Lload 10mH
Rload 2.5Ω
Lp 50µH
Rp 0.2Ω
Ls1, Ls2 25µH
Lm 15mH
Fig A.9 shows the output load current and the current through the upper half of
the winding in phase-A. It is clear from this figure that each half of the secondary
winding conducts only for 50% of time. Fig A.10 describes the commutation
process. The signal ON is the combination of signals NP1 and NP2. Similarly,
OFF is the combination of PN1 and PN2. The current through the inductor
Ls1 changes linearly during the commutation according to the slope predicted by
(A.19). Fig A.10 also shows the current through the switch Q and the sum of the
magnetizing currents. The net change in the sum of the magnetizing currents,
im,sum, during ON and OFF is zero as predicted. The current through the switch
Q is also zero at the beginning and at the end of the commutation. Thus, the
simulation results confirm the soft switching (ZCS) of all of the four-quadrant
switches. Fig A.11 shows the magnetizing current for one of the transformers.
This figure verifies the flux balance in the transformer core and its high frequency
operation.
A.1.5 Simulation results ac/ac topology
The circuit in Fig A.5 is simulated in MATLAB/Simulink. Vin is set to 500 V. The
output is connected to a balanced three phase RL load. The load is star connected.
Different parameters of this circuit are given in Table A.4. The modulation index k
is set to 0.25. The frequency (fs =1Ts) at which the output voltage is generated is
89
Table A.4: Parameters
Lload 10mH
Rload 2.5Ω
L1 15µH
R1 0.2Ω
L21, L22 15µH
Lm 15mH
5 kHz. Transformer flux is balanced at 2.5 kHz. The commutation time according
to (16) is 6.2 µs. The frequency of the output voltage is 60 Hz.
0.405 0.41 0.415 0.42−500
0
500
vo
A(V
)
0.405 0.41 0.415 0.42−30
−20
−10
0
10
20
30
iA
(A)
0.405 0.41 0.415 0.42−30
−20
−10
0
10
20
30
time (s)
ilk
g(A
)
Figure A.9: Simulation results: Output voltage, output current, and currentthrough upper half of secondary winding (dc/ac)
Fig A.12(b) shows the output load current in phase-R. The peak of this current
is slightly less compared to its analytically predicted value. This is due to voltage
loss during commutation. Fig A.12(c) gives the current through the upper half of
the winding in phase-R. It is clear from this figure that each half of the secondary
90
winding conducts only for 50% of time. Fig A.14 describes the circuit operation
during commutation. The current through the inductor L11 changes linearly dur-
ing the commutation. Fig A.14(d) shows the current through the switch Q. As the
output load is balanced and the net change in the sum of the all three magnetizing
currents (Fig A.14(e)) is zero during commutation, the current through switch Q
is also zero at the beginning and at the end of the commutation process. These
waveforms confirm the soft switching (ZCS) of all of the bi-directional switches.
Fig A.13 presents filtered input line current waveform with corresponding line to
neutral voltage. This confirms input power factor correction. Fig A.15 shows the
magnetizing current in one of the phases.
A.2 Conclusion
The following benefits of the proposed topologies have been verified through the
presented simulation results:
1. Minimum number of switching transitions between the load and the trans-
former secondary windings. This implies lower distortion and lower loss in
the output voltage.
2. Loss-less commutation of the leakage energy and Zero current switching in
all secondary side switches
3. Input power factor correction
One major disadvantage of this topology is complicated commutation process in
order to maintain flux balance through additional switching. Also common-mode
voltage elimination is not possible.
91
0.4234 0.4235 0.4236−20
−10
0
10
ilk
g(A
)
0.4234 0.4235 0.4236
0
1O
N
0.4234 0.4235 0.4236
0
1
OFF
0.4234 0.4235 0.4236
−20
0
20
iQ
(A)
0.4234 0.4235 0.4236
0
1
BA
SIC
0.4234 0.4235 0.4236−0.4
−0.2
0
0.2
0.4
time (s)
im
,su
m(A
)
Figure A.10: Simulation results: Commutation process (dc/ac)
0.345 0.35 0.355 0.36 0.365−1.5
−1
−0.5
0
0.5
1
1.5
time (s)
im
(A)
Figure A.11: Simulation results: Magnetizing current (dc/ac)
92
0.302 0.304 0.306 0.308 0.31 0.312 0.314 0.316 0.318
−500
0
500
VR
N(V
)
0.302 0.304 0.306 0.308 0.31 0.312 0.314 0.316 0.318−50
0
50
iR
(A)
0.302 0.304 0.306 0.308 0.31 0.312 0.314 0.316 0.318−50
0
50
time (s)
ilk
g(A
)
Figure A.12: Simulation result: a) output voltage b) output current c) currentthrough the upper half of secondary winding (ac/ac)
0.318 0.32 0.322 0.324 0.326 0.328 0.33 0.332−50
0
50
time (s)
va(1
0V)
and
ia(A
)
Figure A.13: Simulation results: Input voltage and current(filtered) (ac/ac)
93
0.3064 0.3064 0.3065 0.3065 0.3066 0.3066−20
0
20
40
iQ
(A)
0.3064 0.3064 0.3065 0.3065 0.3066 0.3066
0
1
CT
0.3064 0.3064 0.3065 0.3065 0.3066 0.3066
0
20
40
ilk
g(A
)
0.3064 0.3064 0.3065 0.3065 0.3066 0.3066−0.4
−0.2
0
0.2
0.4
time (s)
im
,su
m(A
)0.3064 0.3064 0.3065 0.3065 0.3066 0.3066
0
1
BA
SIC
Figure A.14: Simulation results: Commutation process (ac/ac)
0.25 0.252 0.254 0.256 0.258 0.26 0.262 0.264 0.266−2
−1.5
−1
−0.5
0
0.5
1
1.5
2
time (s)
im
(A)
Figure A.15: Simulation results: Magnetizing current (ac/ac)
Appendix B
Inter-winding Capacitance
As it is mentioned in Chapter 4 that the high-frequency three winding transformer
used in this work has a tri-filar winding arrangement in order to minimize the leak-
age inductance. It is observed that the measured leakage inductance is relatively
low and in the order of 10 µH. But this winding structure leads to increasing
amount of inter-winding capacitance. During the power flow or modulation mode
it is observed that the load voltage has a significant amount of second order os-
cillation. This oscillation increases with the addition of external inductance in
series with each of the windings. Both from the network analyzer and by the
direct measurement of the oscillating waveforms in the scope it is found that an
equivalent capacitor appears across the load and is in the range of 5 to 10 nF.
Surprisingly it is found, while performing measurements with net work analyzer
that this equivalent capacitance is negligible when both the secondary windings
are not connected in series. The following analysis provides an explanation of this
observation.
In Fig B.1.a C12 represents the inter-winding capacitance between the winding
94
95
set 1 and 2. From this figure it is evident that C12 and C31 are in series. When
the two secondary windings 2 and 3 are connected as shown in Fig. B.1.b, C23
comes in parallel with the series combination of the other two capacitances. The
effective capacitance seen from the primary winding 1 that appears across the
load is given by (B.1). When the secondary windings are not connected no effect
inter-winding capacitance is observed.
Ceffective = C31||C12 + C23 (B.1)
Three other winding structures have been implemented as shown in Fig B.2.
Observed parameters are presented in Table B.1. Note the dramatic increase of the
leakage inductance (L) as the coupling between the windings reduces. The inter-
winding capacitance (C is the effective capacitance, Ceffective) reduces as expected
but the range of variation is less in comparison with the leakage inductance.
Table B.1: Measured transformer parameters
Parameter L C
Tri-filar 10 µH 10 nF
Ta 40 µH 4 nF
Tb 1.8 mH 1.8 nF
Tc 2.1 mH 1 nF
96
3
3’
3’
3
1
1’
2
2’
C12
C23C31 C31
C12
C23
1
1’
2
2’
(a) (b)
Figure B.1: inter-winding capacitance
1 21 2 31’2’3’ 1’2’ 3’3
3’3
2 2’
11’
Ta Tb
Tc
Figure B.2: Different winding structures
Appendix C
A PET based on indirect
modulation
In this appendix a novel topology based on the indirect modulation of matrix
converter is presented. The main objective of this topology along with the pro-
posed control is to eliminate the common-mode voltage present at the load end.
The input side converter is a three phase to single phase direct link matrix con-
verter switched with a simple triangle comparison based novel PWM strategy and
provides input power factor correction. This converter operates with the same
principle as that of the front end converter based on the indirect modulation. The
center tapped secondary of the transformer along with a single phase rectifier pro-
vides the required voltage levels for a three level inverter which is operated as a two
level inverter in order to eliminate common-mode voltages at its output. Due to
the presence of leakage inductance each state transition the secondary converters
lead to common-mode voltage switching. The analysis of the proposed converter
97
98
and with the control is presented in details followed by simulation results con-
firming various advantages. This topology is not pursued any further due to the
switching of the common-mode voltage due to leakage inductance commutation 1
.
C.1 Analysis
C.1.1 PWM Strategy for the Front End Converter
N
2
N
2
N
A
B
S1
S3 S4
Three Level Inverter
R
B
Front end Conv
S2
Y
Rectifier −0.5Vdc
+0.5Vdc
Vb
Vc
o
Va
n
3 phase load
Figure C.1: Circuit diagram of the high frequency AC link
The front end converter, figure (C.1) first converts the three phase input AC
voltage wave form at the line frequency of 60 Hz to dc by creating a virtual
dc link. This is called the rectification stage. In the next stage it converts the
virtual dc to a high frequency AC. This is the inverter stage. The input to the
transformer is constant frequency AC at 2.5 kHz. So a three phase low frequency
AC is converted into a high frequency single phase AC waveform. This converter
1 parts of this chapter is taken from [18].
99
is basically a direct link matrix converter with a conventional rectification stage
followed by a single phase inverter instead of a three phase one. The line currents
are also shaped to be in phase with the input voltage wave form. So this converter
provides the input power factor correction.
The PWM signals for the front end converter are generated using a simple
triangle comparison method. As the input three phases are connected to voltage
sources they can not be shorted at any instant of time. Due to the inductive nature
of load the output phases can not be opened. Let SaA be the switching state of
the switch between the input a phase and output A phase and daA be its duty
ratio. SaA is 0 when it is off and 1 when it is on. The above mentioned conditions
translate into the fact that SaA, SbA and ScA can not be simultaneously 1 (any
two of them or all of them). Also they can not be 0 all at a time. Fig C.2 shows
how the reference voltage signals are compared with a triangular carrier signal in
order to meet the above mentioned requirements. The signal SbA is obtained by
XOR ing the signals obtained by comparing the triangular carrier with daA and
(daA + dbA).
1
SbA
SaA
ScA
daA + dbA
daA
TS0
0
Figure C.2: Front end converter PWM generation
100
The above requirements also implies equation (C.1). Another restriction on
duty ratios is given by equation (C.2).
daA + dbA + dcA = 1
daB + dbB + dcB = 1 (C.1)
Let us assume that input is a three phase balanced sinusoidal voltage source
with peak magnitude Vi and angular frequency ωi, equation (C.3).
0 ≤ daA, dbA, dcA ≤ 1
0 ≤ daB, dbB, dcB ≤ 1 (C.2)
va(t) = Vi cosωit
vb(t) = Vi cos
(
ωit−2π
3
)
vc(t) = Vi cos
(
ωit +2π
3
)
(C.3)
The virtual dc link voltage at the output phase A, vA(t) is synthesized on an
average over a subcycle period Ts from va(t), vb(t) and vc(t). The average voltage
in the two output phases can be obtained from the equation (C.4).
vA(t) = daAva + dbAvb + dcAvc
vB(t) = daBva + dbBvb + dcBvc (C.4)
101
The choice of daA as KA(t) cosωit and phase shifted versions of the same
for dbA and dcA will generate an average voltage of 32KA(t)Vi in phase A over a
subcycle, equation (C.4). In order to satisfy equation (C.2) it is required to add
a common-mode component in each of these duty ratios. Da(t) = 0.5| cosωi(t)| is
added in daA and daB. Similarly phase shifted versions of Da(t) is added to the
corresponding duty ratios of phase b and c, equation (C.5). The common-mode
voltage generated due to this gets cancelled in the line to line voltage of VAB,
which is the input to the primary of the high frequency transformer. In order
to maintain equation (C.1), it is required to inject another set of common- mode
duty ratios ∆a, ∆b and ∆c corresponding to the phases a, b and c, equation (C.6).
After the inversion, the high frequency AC applied to the transformer primary
has three distinct levels over a subcycle.This results in a variable dc bus for the
output side three level inverter. A variable slope carrier is used to average out
this effect. This particular choice of common-mode duty ratios is made in order
to generate such a carrier for the output converter.
Da(t) = 0.5| cosωit|
Db(t) = 0.5
∣
∣
∣
∣
cos
(
ωit−2π
3
)∣
∣
∣
∣
Dc(t) = 0.5
∣
∣
∣
∣
cos
(
ωit+2π
3
)∣
∣
∣
∣
(C.5)
∆a(t) =1− (Da +Db +Dc)
2
∆b(t) = 0
∆c(t) =1− (Da +Db +Dc)
2(C.6)
102
Finally with all of these considerations, the duty ratios of all of the six switches
in the front end converter are given by equations (C.7) and (C.8). This choice of
duty ratios leads to an average line to line voltage, vAB, over a subcycle as given
by the equation (C.9).
daA(t) = KA(t) cosωit+Da +∆a
dbA(t) = KA(t) cos
(
ωit−2π
3
)
+Db +∆b
dcA(t) = KA(t) cos
(
ωit+2π
3
)
+Dc +∆c (C.7)
daB(t) = KB(t) cosωit +Da +∆a
dbB(t) = KB(t) cos
(
ωit−2π
3
)
+Db +∆b
dcB(t) = KB(t) cos
(
ωit+2π
3
)
+Dc +∆c (C.8)
vAB(t) =3
2Vi [KA(t)−KB(t)] (C.9)
In order to achieve the inverter operation, KA(t) is always chosen to be equal
to the negative of KB(t) equation (C.10) and KA(t) is given by the equation
(C.11). Ki is called the modulation index of the input converter and it is set to
its maximum value equal to 0.5. This implies that the average line to line input
voltage to the transformer primary is a square wave with amplitude 3KiVi.
KA(t) = −KB(t) (C.10)
103
KA(t) =
+Ki for (n− 1)Ts ≤ t < nTs
−Ki for nTs ≤ t < (n+ 1)Ts
(C.11)
This pulse width modulation strategy also ensures that the input line currents
are in phase with the input voltage waveforms. Assuming a continuous power
flow the average current in the transformer primary is also a square wave with
an amplitude I1. The average input line current in phase a is given in equation
(C.12) and it is in phase with the input voltage va. All the six switches of the
front end three phase to single phase matrix converter needs to be four quadrant.
ia = (SaA − SaB)iAB
= 2KiI1 cosωit (C.12)
C.1.2 Isolation and Rectification
Transformer changes the voltage level of the high frequency input voltage wave-
form and provides the required isolation. The midpoint of the secondary winding
is taken as the secondary ground. Other two ends of the secondary winding are
connected to a single phase rectifier. A three level voltage source inverter is used
to synthesize the three phase sinusoidal output voltage at a desired frequency and
amplitude. The midpoint of the secondary winding and the two outputs of the
rectifier provide the three voltage levels for the output inverter. The rectifier is
synchronized with the input converter. Switches S1 and S4 are closed during the
subcycle interval when KA(t) is Ki and in the next interval S3 and S4 is switched
on, Fig C.1.
104
In this prototype the turns ratio of the transformer is assumed to be one. An
approximate equivalent circuit of one of the halves of the secondary winding is
shown in Fig C.3. Let r1 be the resistance and l1 be the leakage inductance of
the primary winding. Similarly r2 and l2 represent the same quantities for one
half of the secondary winding. The equivalent leakage impedance turns out to be
re =r12+r2 and le =
l12+l2. In this analysis the effect of magnetizing inductance is
neglected and the currents in the two halves of the secondary winding is assumed
to be equal and opposite from the symmetry arguments. Assuming the rectifier
and the output three level inverter to be ideal and the three phase load to be
inductive in nature the load in this equivalent circuit appears to be a pulsating
current source. Due to the presence of leakage inductance it is not possible to
connect the secondary directly to the switching load and a voltage port is to be
created. That is why a capacitor is placed at the output of the secondary winding.
Presence of considerable amount of leakage inductance causes the output to be
oscillatory and poorly damped and that in turn leads to a reduction in switching
frequency. To provide considerable damping a resistance is put in parallel to the
capacitor. This leads to a constant power loss. An active loss less solution to this
problem needs to be worked out. Also in the design of the transformer it is very
important to keep the leakage inductance to be at its minimum otherwise it will
lead to the reduction in switching frequency and increase in the transformer size.
C.1.3 PWM strategy for the output inverter
A three level inverter produces 27 vectors as shown in the Fig C.4. Each of
these vectors are denoted by a switching state. For example when voltage vector
105
VsecR IC
rele
Figure C.3: Equivalent circuit of the transformer secondary
V1 is applied the switching state is (+0−). The output R phase is connected
to the positive dc bus +0.5Vdc, Y phase is shorted to the ground and B phase is
connected to −0.5Vdc, Fig C.1. Out of these only six active vectors are used. These
vectors are denoted by V1 to V6. The sum of the pole voltages are instantaneously
zero when these vectors are employed. This leads to a complete elimination of
common-mode voltages from the output load terminals. The inverter is operated
as a two level inverter with all of these six vectors . Only one zero vector is
used that is when all the phases are connected to the ground as it ensures zero
common-mode voltage. The average dc bus voltage Vdc available is 3KiVi. Use of
above mentioned vectors leads to an effective dc bus of√32Vdc. So this results in
an under utilization of the dc bus. The modulation index Ko of the three level
inverter is defined as the ratio of the magnitude of the synthesized output voltage
vector to that of the available dc bus. The maximum limit of Ko is√32. So the
peak value of the output phase voltage is given by the equation (C.13).
Vo =√3KiKoVi (C.13)
As mentioned earlier the modulation index of the front end converter is set
to its maximum value of 0.5. This leads to a three level voltage wave form in
a subcycle, in the transformer primary as shown in Fig C.6. One of the level is
106
(+ + −)
(+0−)
(+ − 0)(0 − 0)
(+ − +)
(−0+)
(+ + 0)
V5
(0 + 0)(−0−)
(0 + +)
(0 + −)
(0 − +)(− − +)
V6
(− + 0)
V4
(− + −)
V3
V2
V1
(0 − −)(+ + +)
(− − −)(0 0 0) (+ 0 0 )
(+0 +)
( 0 0 −)
( 0 0 +)
(− 0 0 )
(− − 0)
(+ − −)(− + +)
Figure C.4: Voltage vectors produced by a three level inverter
zero. Even though the average voltage remains 3KiVi, the dc bus voltage for the
output three level inverter is pulsating in nature. This will lead to a distortion in
the fundamental component of the output voltage. In order to solve this problem
a variable slope carrier is used to generate the duty ratios for the output inverter
as indicated in the Fig C.6. This carrier is generated with the help of two control
signals as shown in Fig C.5 and given by the equation (C.14). These two signals
when multiplied with the subcycle time period Ts give the time periods of the two
different voltage levels present in the dc bus voltage waveform. The variable slope
carrier ensures an average effective dc bus voltage of 3KiVi.
u1(t) = minDa, Db, Dc
u2(t) = maxDa, Db, Dc − u1(t) (C.14)
107
0 0.004 0.008 0.012 0.016 0.02−1
−0.5
0
0.5
1
sinωit
u2(t)
u1(t)
time(s)
Figure C.5: Control Signals
VAB
Carrier
0
1
u2TSu1TS u1TS
TS
u2TS
Figure C.6: Variable slope carrier and primary voltage over a subcycle
C.1.4 Simulation results
The proposed topology has been simulated in SABER. The PWM signals are gen-
erated in MATLAB SIMULINK and fed into the SABER model through COSIM.
The input is a three phase balanced AC voltage with peak magnitude, Vi, of 120
volts at frequency of 60 Hz. The output is connected to a three phase balanced R-
L load. The transformer parameters are given in the Table ??. Rc and Lm are the
core loss resistance and the magnetizing inductance as seen from the transformer
primary. The frequency of the AC voltage applied to the transformer is chosen to
108
Table C.1: Parameters
Lload 3.3mH
Rload 1.66Ω
l1 10µH
r1 10mΩ
l2 5µH
r2 5mΩ
Lm 1mH
Rc 100Ω
be 2.5 kHz. As mentioned earlier Ki is set to 0.5 and the modulation index of the
output inverter Ko is chosen to be 0.8. Output voltage is generated at a frequency
of 60 Hz. According to the equation (C.13) the peak of the output voltage is 83.14
volts resulting in a line current of 40 A peak. The Fig C.7 shows the simulated
output current waveform with a peak slightly less than its analytically predicted
value. This is due to the voltage drop in transformer windings. As the load is
balanced and its neutral point is isolated. the voltage Vno gives the common-mode
voltage present in the pole voltages of the three level inverter. Fig C.8 gives the
simulated Vno voltage waveform. Fig C.9 presents the the simulated positive dc
bus voltage at the input to the output inverter. Because of the presence of leakage
impedance there are spikes in the dc link voltage wave form. This also shows up
in the common-mode voltage waveform. The simulated input current waveform
(filtered) is shown in Fig C.10 along with the input voltage. It clearly indicates
the input power factor correction.
109
−40.0
−20.0
0.0
20.0
40.0
0.0 8.0m 16.0m 24.0m 32.0m
Load
Current(A
)
time (s)
Figure C.7: Simulation result: output load current
Com
mon M
ode
Volt
age
(V)
−100.0
−50.0
0.0
50.0
100.0
time (s)24.7m 24.75m 24.8m 24.85m 24.9m
Figure C.8: Simulation result: common-mode voltage
−400.0
−200.0
0.0
200.0
400.0
600.0
18.0m 18.4m 18.8m 19.2m 19.6m 20.0m
DC
BusVoltage(V
)
time (s)
Figure C.9: Simulation result: positive dc link voltage
110
0.0 10.0m 20.0m 30.0m
−200.0
−100.0
0.0
100.0
200.0
time (s)
InputVoltage(V
)
Input Voltage (V)
Input Current (A)
InputCurrent(A
)
Figure C.10: Simulation result: input line current
