Power Network Distribution
Chung-Kuan Cheng
CSE Dept.
University of California, San Diego
Page 2
Research Projects
SPICE_Diego
– Whole chip simulation using cloud computing
Power Distribution: Analysis, Synthesis, Methodology
– 3D IC pathfinder
Interconnect: Analysis, Synthesis
– Eye diagram prediction under power ground noises
Physical Layout
– Performance driven placement
Page 3
Research on Power Distribution Networks
Analysis
–Stimulus, Noise Margin, Simulation
Synthesis
–VRM, Decap, ESR, Topology
Integration
–Sensors, Prediction, Stability, Robustness
Page 4
Power Distribution Network Overview
Background: power distribution networks (PDN’s)
Analysis: worst-case PDN noise prediction
–Target Impedance
–Worst Current Loads
–Rogue Wave
Conclusions and future work
Page 5
Introduction: Motivation
Year gt Lnm
freqGHz
VddVolt
P=VIW
I=P/VAmp
Z=V/IOhm
2011 24 6.3 0.93 90 96 0.00964
2015 17 8.5 0.81 123 152 0.00533
2020 10.7 12.4 0.68 142 208 0.00326
2024 7.4 16.6 0.60 170 284 0.00211
ITRS Roadmap:MPU
Year gt Lnm
freqGHz
VddVolt
P=VIW
I=P/VAmp
Z=V/IOhm
2011 27 0.72 0.85 1.87 2.21 0.385
2015 17 1.66 0.75 4.04 5.38 0.139
2020 10.7 3.31 0.65 7.73 11.89 0.055
2024 7.4 5.32 0.60 12.92 21.53 0.028
SoC
Page 6
What is a power distribution network (PDN)
Power supply noise
– Resistive IR drop
– Inductive Ldi/dt noise
[Popovich et al. 2008]
Page 7
Resonant Phenomenon: One-Stage LC Tank w/ ESR’s
Y(jw) at current load:
If we ignore R1 and R2
Y(jw)=jwC+1/jwL=j(wC-1/wL)
When w= (CL)-1/2,
we have Y(jw) --> 0.
Impedance at load:
Z(jw)= 1/Y(jw) --> inf
Page 8
Introduction
Target Impedance = Vdd/Iload x 5%
–Production Cost
Negative Noise Budget
–Negotiation between IC and package
–Activity scheduling
Page 9
Analysis: Motivation
Target Impedance
–Impedance in frequency domain
Worst power load in time domain
–Slope of power load stimulus
Composite effect of resonance at multiple frequencies
Page 10
Target Impedance
PDN design
– Objective: low power supply noise
– Popular methodology: “target impedance”
[Smith ’99]
Implication: if the target impedance is small, then the noise will also be small
Page 11
Analysis: Formulation
Problems with “target impedance” design methodology
– How to set the target impedance?
• Small target impedance may not lead to small noise
– A PDN with smaller Zmax may have larger noise
Time-domain design methodology: worst-case PDN noise
– If the worst-case noise is smaller than the requirement, then the PDN design is safe.
• Straightforward and guaranteed
– How to generate the worst-case PDN noise
( ) ( ( ) ( ( )))v t IFT Z j FT i t FT: Fourier transform
Page 12
Analysis: Related Work
At final design stages [Evmorfopoulos ’06]
– Circuit design is fully or almost complete
– Realistic current waveforms can be obtained by simulation
– Problem: countless input patterns lead to countless current waveforms
• Sample the excitation space
• Statistically project the sample’s own worst-case excitations to their expected position in the excitation space
At early design stages [Najm ’03 ’05 ’07 ’08 ’09]
– Real current information is not available
– “Current constraint” concept
– Vectorless approach: no simulation needed
– Problem: assume ideal current with zero transition time
Page 13
Analysis: Formulation
Problem formulation I
PDN noise:
Worst-case current [Xiang ’09]:
max ( )
s.t. 0 i(t) b
v t
0
( ) ( ) ( )t
v t h i t d ( ): PDN impulse responseh
( ) for ( ) 0i t b h ( ) 0 for ( ) 0i t h
Zero current transition time. Unrealistic!
Page 14
Ideal Case Study: One-Stage LC Tank w/ ESR’s
Define:
Note
Under-damped condition:
1 2
1 LQ
R R C
11
1 LQ
R C 2
2
1 LQ
R C
0
1
LC
1 2
1 1 1
Q Q Q
21 2
4 1( )
2
LR R Q
C
Page 15
Ideal Case Study: One-Stage LC Tank w/ ESR’s (Cont’)
Step response:
where
Normalized step response:
1( ) 2 cos sintuv t K e A t B t
1 11
1 LK R
Q C 01 2
2 2
R R
L Q
2
01 22
1 4 14
2 2
R R
LC L Q
1 2 1 2
1 1
2 2
R R Q Q LA
C
2 2 2 2
1 2 1 2
2
1 22
1 12
2
14 2 42
R R C L Q Q LB
CR RLC QLC L
0 2 21 2
0 02 21 2 1
2
1 12
( ) 1 1 1 1 1cos 1 sin 1
4 4/ 12 1
4
tQuv t Q Q
e t tQ Q Q Q QL C
Q
Page 16
Ideal Case Study: One-Stage LC Tank w/ ESR’s (Cont’)
Local extreme points of the step response:
Normalized magnitude of the first peak:
2 22
22 2
0 2
1arctan
1 4 11arctan , 0,1, 2,
4 111
4
k
A Bt k
B A
Q Qk k
Q QQ
Q
0
202
1 1 2 2
( ) 1 1 11 1
/Quv t
e signQ Q Q QL C
Page 17
Ideal Case Study: One-Stage LC Tank w/ ESR’s (Cont’)
Normalized worst-case noise:
2 22
222 2
2
1 4 11arctan
4 14 1
1 1 2 4 1
1 11
/1
Q Q
Q QQQ
wc
Q
V e
Q Q QL Ce
Page 18
Ideal Case Study: One-Stage LC Tank w/ ESR’s (Cont’)
Impedance:
When [Mikhail 08]
Normalized peak impedance:
2 22 21 2 1 2
2 22 2 21 2
( )1
R R LC R R C LZ j
LC R R C
3Q0
2 2 2 21 2 1 2 1 2
1 2
( )
/ 1 1 11
/
peakZ Z j
L C
R R Q Q Q Q
L C LQ
R R C
/peakZ
QL C
Page 19
Analysis: Algorithms
Problem formulation II
0max ( ) ( ) ( )
s.t. 0 i(t) b
/
Tv T h i T d
di dt c
Transition time:
r
bt
c
T: chosen to be such that h(t) has died down to some negligible value.
* f(t) replaces i(T-τ)
Page 20
Proposed Algorithm Based on Dynamic Programming
GetTransPos(j,k1,k2): find the smallest i such that Fj(k1,i)≤ Fj(k2,i)
Q.GetMin(): return the minimum element in the priority queue Q
Q.DeleteMin(): delete the minimum element in the priority queue Q
Q.Add(e): insert the element e in the priority queue Q
Page 21
Proposed Algorithm: Initial Setup
Divide the time range [0, T] into m intervals [t0=0, t1], [t1, t2], …, [tm-1, tm=T]. h(ti) = 0, i=1, 2, …, m-1
u0 = 0, u1, u2, …, un = b are a set of n+1 values within [0, b]. The value of f(t) is chosen from those values. A larger n gives more accurate results.
h(t)
Page 22
Proposed Algorithm: f(t) within a time interval [tj, tj+1]
Ij(k,i): worst-case f(t) starting with uk at time tj and ending with ui at time tj+1
h(t)Theorem 1: The worst-case f(t) can be cons-tructed by determining the values at the zero-crossing points of the h(t)
Page 23
Proposed Algorithm: Dynamic Programming Approach
Define Vj(k,i): the corresponding output within time interval [tj, tj+1]
Define the intermediate objective function OPT(j,i): the maximum output generated by the f(t) ending at time tj with the value ui
Recursive formula for the dynamic programming algorithm:
Time complexity:
1
( , ) ( )( ( , )( ))j
j
t
j jtV k i h I k i d
0( , ) max ( ) ( )
where ( ) is all the possible ( ) that satisfies ( )
jt
i
i j i
OPT j i h f d
f f f t u
0
(0, ) 0 for all [0, ]
( 1, ) max( ( , ) ( , ))jk n
OPT i i n
OPT j i OPT j k V k i
2( )O n m
Page 24
Acceleration of the Dynamic Programming Algorithm
Without loss of generality, consider the time interval [tj, tj+1] where h(t) is negative.
Define Wj(k,i): the absolute value of Vj(k,i):
( , ) ( , )j jW k i V k i
Lemma 1: Wj(k2,i2)- Wj(k1,i2)≤ Wj(k2,i1)- Wj(k1,i1) for any 0 ≤ k1 < k2 ≤ n and 0 ≤ i1 < i2 ≤ n
Page 25
Acceleration of the Dynamic Programming Algorithm
Define Fj(k,i): the candidate corresponding to k for OPT(j,i)
Accelerated algorithm:
– Based on Theorem 2
– Using binary search and priority queue
( , ) ( , ) ( , )j jF k i OPT j k W k i
Theorem 2: Suppose k1 < k2, i1 [0,∈ n] and Fj(k1,i1)≤ Fj(k2,i1), then for any i2 > i1, we have Fj(k1,i2)≤ Fj(k2,i2).
( log )O nm n
Page 26
Analysis: Case Study
Case 1: Impedance => Voltage drop
–Transition Time
Case 2: Impedances vs. Worst Cases
Case 3: Voltage drop due to resonance at multiple frequencies.
Page 27
Case Study 1: Impedance
2.09mΩ @ 19.8KHz 1.69mΩ
@ 465KHz
3.23mΩ @ 166MHz
Page 28
Case Study 1: Impulse Response
0 0.2 0.4 0.6 0.8 1
x 10-7
-1
-0.5
0
0.5
1
1.5
2x 10
6
Time (sec)
Impu
lse
resp
onse
(V
)
0 0.2 0.4 0.6 0.8 1 1.2
x 10-4
-30
-20
-10
0
10
20
30
Time (sec)
Impu
lse
resp
onse
(V
)
0 0.2 0.4 0.6 0.8 1 1.2
x 10-5
-1000
-500
0
500
1000
1500
2000
Time (sec)
Impu
lse
resp
onse
(V
)
Impulse response: 100ns~10µs Impulse response: 10µs~100µs
Impulse response: 0s~100ns
High frequency oscillation at the beginning with large amplitude, but dies down very quickly
Mid-frequency oscillation with relativelysmall amplitude.
Low frequency oscillation with the smallest amplitude, but lasts the longest
Amplitude = 1861
Amplitude = 29
Amplitude = 0.01
Page 29
Case Study 1: Worst-Case Current
Current constraints:
0 ( ) 50
Minimum transition time: r
i t A
t
Zoom in
The worst-case current also oscillates with the three resonant frequencies which matches the impulse response.
Saw-tooth-like current waveform at large transition times
Page 30
Case Study 1: Worst-Case Noise Response
Page 31
Case Study 1: Worst-Case Noise vs.. Transition Time
The worst-case noise decreases with transition times.
Previous approaches which assume zero current transition times result in pessimistic worst-case noise.
Page 32
Case Study 2: Impedances vs. Worst Cases
0 i(t) 1
1.25rt ns
pd
d
10
30
R m
R m
pd
d
30
10
R m
R m
100
102
104
106
108
1010
0
0.02
0.04
0.06
0.08
0.1
0.12
Frequency (Hz)
Impe
danc
e (
)
100
102
104
106
108
1010
0
0.02
0.04
0.06
0.08
0.1
0.12
0.14
Frequency (Hz)
Impe
danc
e (
)
max 127.0Z m max 114.4Z m
224.3KHz
11.2MHz
98.1MHz
224.3KHz
10.9MHz
101.6MHz
Page 33
Case Study 2: Worst-Case Noise
for both cases: meaning that the worst-case noise is larger than Zmax.
The worst-case noise can be larger even though its peak impedance is smaller.
0 0.2 0.4 0.6 0.8 1 1.2
x 10-4
-0.05
0
0.05
0.1
0.15
Time (sec)
Wor
st c
ase
PD
N n
oise
(V
)
0 0.2 0.4 0.6 0.8 1 1.2
x 10-4
-0.05
0
0.05
0.1
0.15
Time (sec)
Wor
st c
ase
PD
N n
oise
(V
)
max
max
max max
127.0
139.3
/ 1.097
Z m
V mV
V Z
max
max
max max
114.4
146.8
/ 1.292
Z m
V mV
V Z
pd
d
10
30
R m
R m
pd
d
30
10
R m
R m
max max max/( ) 1V Z I
Page 34
Case 3: “Rogue Wave” Phenomenon
Worst-case noise response: The maximum noise is formed when a long and slow oscillation followed by a short and fast oscillation.
Rogue wave: In oceanography, a large wave is formed when a long and slow wave hits a sudden quick wave.
0 0.5 1 1.5 2
x 10-6
-0.03
-0.02
-0.01
0
0.01
0.02
0.03
0.04
Time (sec)
Vol
tage
(V
)
Low-frequency oscillation corresponds to the resonance of the 2nd stage
High-frequency oscillation corresponds to the resonance of the 1st stage
Page 35 100
102
104
106
108
1010
0
0.005
0.01
0.015
0.02
0.025
0.03
0.035
0.04
Frequency (Hz)
Impe
danc
e (
)
Two stage
Case 3: “Rogue Wave” Phenomenon (Cont’)
Equivalent input impedance of the 2nd stage at high frequency
100
102
104
106
108
1010
0
0.005
0.01
0.015
0.02
0.025
0.03
0.035
0.04
Frequency (Hz)
Impe
danc
e (
)
Two stage1st stage alone
100
102
104
106
108
1010
0
0.005
0.01
0.015
0.02
0.025
0.03
0.035
0.04
Frequency (Hz)
Impe
danc
e (
)
Two stage1st stage alone2nd stage alone
Page 36
Case 3: “Rogue Wave” Phenomenon (Cont’)
Input current i(t):
– Blue (I1): worst-case input stimulus
– Red (I2): low frequency part of I1
– Green (I3): high frequency part of I1
0 0.5 1 1.5 2
x 10-6
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
Time (sec)
Cur
rent
(A
)
Worst-case current
Worst-case current (I1)
Low -freq part (I2)
High-freq part (I3)
I1=I2+I3
Page 37
Case 3: “Rogue Wave” Phenomenon (Cont’)
Input current i(t) (zoom in):
0.96 0.97 0.98 0.99 1 1.01 1.02 1.03 1.04
x 10-6
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
Time (sec)
Cur
rent
(A
)Worst-case current
Worst-case current (I1)
Low -freq part (I2)
High-freq part (I3)
Page 38
Case 3: “Rogue Wave” Phenomenon (Cont’)
Noise response @ chip output
– Blue (V1): response of I1
– Red (V2): response of I2
– Green (V3): response of I3
0 0.5 1 1.5 2
x 10-6
-0.03
-0.02
-0.01
0
0.01
0.02
0.03
0.04
Time (sec)
Vol
tage
(V
)
Noise response
Worst-case noise response (V1)
Noise response of low-f req part (V2)
Noise response of high-f req part (V3)
Page 39
Case 3: “Rogue Wave” Phenomenon (Cont’)
Noise response (zoom in):
0.96 0.97 0.98 0.99 1 1.01 1.02 1.03 1.04
x 10-6
-0.03
-0.02
-0.01
0
0.01
0.02
0.03
0.04
Time (sec)
Vol
tage
(V
)Noise response
Worst-case noise response (V1)
Noise response of low-f req part (V2)
Noise response of high-f req part (V3)
Page 40
Remarks
Worst-case PDN noise prediction with non-zero current transition time
– Current model is crucial for analysis
– The worst-case PDN noise decreases with transition time
– Small peak impedance may not lead to small worst-case noise
– “Rogue wave” phenomenon
Adaptive parallel flow for PDN simulation using DFT
– 0.093% relative error compared to SPICE
– 10x speed up with single processor.
– Parallel processing reduces the simulation time even more significantly
Page 41
Summary
Power Distribution Network
– VRMs, Switches, Decaps, ESRs, Topology,
Analysis
– Stimulus, Noise Tolerance, Simulation
Control (smart grid)
– High efficiency, Real time analysis, Stability, Reliability, Rapid recovery, and Self healing
Page 42
Page 43
Publication List
• Power Distribution Network Simulation and Analysis[1] W. Zhang and C.K. Cheng, "Incremental Power Impedance Optimization Using Vector Fitting Modeling,“ IEEE Int. Symp. on Circuits and Systems, pp. 2439-2442, 2007.
[2] W. Zhang, W. Yu, L. Zhang, R. Shi, H. Peng, Z. Zhu, L. Chua-Eoan, R. Murgai, T. Shibuya, N. Ito, and C.K. Cheng, "Efficient Power Network Analysis Considering Multi-Domain Clock Gating,“ IEEE Trans on CAD, pp. 1348-1358, Sept. 2009.
[3] W.P. Zhang, L. Zhang, R. Shi, H. Peng, Z. Zhu, L. Chua-Eoan, R. Murgai, T. Shibuya, N. Ito, and C.K. Cheng, "Fast Power Network Analysis with Multiple Clock Domains,“ IEEE Int. Conf. on Computer Design, pp. 456-463, 2007.
[4] W.P. Zhang, Y. Zhu, W. Yu, R. Shi, H. Peng, L. Chua-Eoan, R. Murgai, T. Shibuya, N. Ito, and C.K. Cheng, "Finding the Worst Case of Voltage Violation in Multi-Domain Clock Gated Power Network with an Optimization Method“ IEEE DATE, pp. 540-547, 2008.
[5] X. Hu, W. Zhao, P. Du, A.Shayan, C.K.Cheng, “An Adaptive Parallel Flow for Power Distribution Network Simulation Using Discrete Fourier Transform,” IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC), 2010.
[6] C.K. Cheng, P. Du, A.B. Kahng, G.K.H. Pang, Y. Wang, and N. Wong, "More Realistic Power Grid Verification Based on Hierarchical Current and Power Constraints,“ ACM Int. Symp. on Physical Design, pp. 159-166, 2011.
Page 44
Publication List
• Power Distribution Network Analysis and Synthesis[7] W. Zhang, Y. Zhu, W. Yu, A. Shayan, R. Wang, Z. Zhu, C.K. Cheng, "Noise Minimization During Power-Up Stage for a Multi-Domain Power Network,“ IEEE Asia and South Pacific Design Automation Conf., pp. 391-396, 2009.
[8] W. Zhang, L. Zhang, A. Shayan, W. Yu, X. Hu, Z. Zhu, E. Engin, and C.K. Cheng, "On-Chip Power Network Optimization with Decoupling Capacitors and Controlled-ESRs,“Asia and South Pacific Design Automation Conference, 2010.
[9] X. Hu, W. Zhao, Y.Zhang, A.Shayan, C. Pan, A. E.Engin, and C.K. Cheng, “On the Bound of Time-Domain Power Supply Noise Based on Frequency-Domain Target Impedance,” System Level Interconnect Prediction Workshop (SLIP), July 2009.
[10] A. Shayan, X. Hu, H. Peng, W. Zhang, and C.K. Cheng, “Parallel Flow to Analyze the Impact of the Voltage Regulator Model in Nanoscale Power Distribution Network,” In. Symp. on Quality Electronic Design (ISQED), Mar. 2009.
[11] X. Hu, P. Du, and C.K. Cheng, "Exploring the Rogue Wave Phenomenon in 3D Power Distribution Networks,“ IEEE Electrical Performance of Electronic Packaging and Systems, pp. 57-60, 2010.
[12] C.K. Cheng, A.B. Kahng, K. Samadi, and A. Shayan, "Worst-Case Performance Prediction Under Supply Voltage and Temperature Variation,“ ACM/IEEE Int. Workshop on System Level Interconnect Prediction, pp. 91-96, 2010.
Page 45
Publication List (Cont’)
•3D Power Distribution Networks[13] A. Shayan, X. Hu, “Power Distribution Design for 3D Integration”, Jacob School of Engineering Research Expo, 2009 [Best Poster Award]
[14] A. Shayan, X. Hu, M.l Popovich, A.E. Engin, C.K. Cheng, “Reliable 3D Stacked Power Distribution Considering Substrate Coupling”, in International Conference on Computer Design (ICCD), 2009.
[15] A. Shayan, X. Hu, C.K. Cheng, “Reliability Aware Through Silicon Via Planning for Nanoscale 3D Stacked ICs,” in Design, Automation & Test in Europe Conference (DATE), 2009.
[16] A. Shayan, X. Hu, H. Peng, W. Zhang, C.K. Cheng, M. Popovich, and X. Chen, “3D Power Distribution Network Co-design for Nanoscale Stacked Silicon IC,” in 17 th Conference on Electrical Performance of Electronic Packaging (EPEP), Oct. 2008. [5]
[17] W. Zhang, W. Yu, X. Hu, A. Shayan, E. Engin, C.K. Cheng, "Predicting the Worst-Case Voltage Violation in a 3D Power Network", Proceeding of IEEE/ACM International Workshop on System Level Interconnect Prediction (SLIP), 2009.
[18] X. Hu, P. Du, and C.K. Cheng, "Exploring the Rogue Wave Phenomenon in 3D Power Distribution Networks,“ IEEE Electrical Performance of Electronic Packaging and Systems, pp. 57-60, 2010.