Power Neutral Performance Scaling for EnergyHarvesting MP-SoCs

Benjamin J. Fletcher, Domenico Balsamo and Geoff V. MerrettDepartment of Electronics and Computer Science

University of Southampton, UKEmail: {bjf1g13, d.balsamo, gvm}@ecs.soton.ac.uk

Abstract—Using energy ‘harvested’ from the environment topower autonomous embedded systems is an attractive ideal,alleviating the burden of periodic battery replacement. However,such energy sources are typically low-current and transient, withhigh temporal and spatial variability. To overcome this, largeenergy buffers such as supercapacitors or batteries are typicallyincorporated to achieve energy neutral operation, where the en-ergy consumed over a certain period of time is equal to the energyharvested. Large energy buffers, however, pose environmentalissues in addition to increasing the size and cost of systems.In this paper we propose a novel power neutral performancescaling approach for multiprocessor system-on-chips (MP-SoCs)powered by energy harvesting. Under power neutral operation,the system’s performance is dynamically scaled through DVFSand DPM such that the instantaneous power consumption isapproximately equal to the instantaneous harvested power. Powerneutrality means that large energy buffers are no longer re-quired, while performance scaling ensures that available poweris effectively utilised. The approach is experimentally validatedusing the Samsung Exynos5422 big.LITTLE SoC directly coupledto a monocrystalline photovoltaic array, with only 47mF ofintermediate energy storage. Results show that the proposedapproach is successful in tracking harvested power, stabilisingthe supply voltage to within 5% of the target value for over93% of the test duration, resulting in the execution of 69% moreinstructions compared to existing static approaches.

I. INTRODUCTION

With recent developments in compiler and runtime opti-misation, multicore systems are able to outperform single-core systems in both performance and power consumption[1]. As such, heterogeneous multiprocessor system-on-chips(MP-SoCs) are rapidly becoming the de-facto technology forpowering modern, high-performance embedded devices. Whenconsidering autonomous embedded devices, such as typicalInternet of Things (IoT) end-devices, maintaining a low power-budget is essential. This is due to the fact that they areoften battery powered, meaning that their lifetimes becomesrestricted by battery capacity and discharge rate [2]. Motivatedby the limited, finite lifetimes achievable using batteries, re-search has more recently looked to supplement, or even replacebatteries by means of energy harvesting (EH). This is wheredevices scavenge ambient energy from their environments [3](e.g. from vibrations, light, thermal gradients etc) in orderto be self-sufficient. Although this provides a sustainablesolution whereby lifetimes become potentially infinite [4], the

Experimental data used in this paper can be found atDOI:10.5258/SOTON/403155 (http://dx.doi.org/10.5258/SOTON/403155).

Time (HH:mm:ss)

00:00:00 04:00:00 08:00:00 12:00:00 16:00:00 20:00:00 00:00:00

Pow

er O

utpu

t (W

)

0.0

0.2

0.4

0.6

0.8

1.0

Macro Variability

Micro Variability

Fig. 1. Experimentally obtained data showing the varying power output of a250cm2 solar cell over the course of a day.

energy harvested from these sources is inherently transient andunpredictable.

Consider the power output of a solar cell array, shown inFig. 1. Here, the harvested power exhibits both ‘micro’ vari-ability (where the power changes rapidly due to shadowing)and ‘macro’ variability (where the power changes more slowlyover the course of the day). Conventionally, in order to dealwith this unpredictable energy harvest, an energy buffer isemployed between the harvester and the device to smooth VCCand make it appear relatively constant, similar to a battery-powered system. Typically, in EH systems this energy buffertakes the form of a supercapacitor due to their increased powerdensities and enhanced operational lifetimes [5]. Considering asimple EH system (Fig. 2), if the supercapacitor is sufficientlylarge that the microcontroller operates perpetually, this isknown as energy neutral operation. Under energy neutrality,the energy harvested in times of copious harvest compensatesfor the deficit when the harvest is diminished [6]. As suchthe energy consumed is equal to the energy harvested over aperiod of time, T (e.g. typically 24 hours for solar powereddevices).

Whilst energy neutral operation offers a viable method ofovercoming variability in EH supplies, it also has weaknesses.The addition of energy storage introduces energy losses due toparasitic leakage currents, causes deterioration in performanceover time [7], increases device size and cost [8] and requiresthe addition of maximum power point tracking (MPPT) cir-cuits and algorithms to operate efficiently.

To address these issues, research has targeted storagelesssystems powered directly by energy harvesting, without ad-ditional energy buffers. ‘SolarTune’ [9], demonstrates such asystem where a multicore CPU platform is coupled directlyto a photovoltaic (PV) EH source. SolarTune uses harvesting-

CPU

EH Source+

VC

RS

RPIL-

Equivalent Circuit Model

CVsource

Fig. 2. Schematic illustrating the circuit topology of a typical simple systempowered by solar energy harvesting.

aware runtime task scheduling (similar to [10]) to adapt per-formance with respect to the predicted availability of harvestedsolar energy such that no significant energy buffer is required[9]. These schemes, however, rely heavily upon accurateprediction of future availability of harvested power, makingthem unsuitable for use with sources exhibiting significant‘micro’ variability which is almost impossible to predict.

The power neutral operating paradigm [11], where a de-vice’s performance is dynamically modulated such that in-stantaneous power consumption matches the instantaneousharvested power, negates the need for energy storage. Theauthors demonstrate a practical implementation on an ultra-low power single-core MCU where power consumption iscontrolled through dynamic frequency scaling (DFS). Thisinstantaneous performance scaling approach has the advantagethat it does not rely upon the prediction of available harvestedpower, making it much more suitable for EH sources withsignificant ‘micro’ variability.

In this paper, we extend the concept of power neutraloperation to a heterogeneous multi-core applications processor,and propose a novel performance scaling approach (Section II)by controlling both DVFS (dynamic frequency and voltagescaling) and DPM (dynamic power management). The ap-proach is modelled (Section III) and experimentally validated(Sections IV and V) using energy harvested by photovoltaiccells.

II. POWER NEUTRAL PERFORMANCE SCALING USINGDVFS AND DPM

Fig. 3 illustrates the concept of power neutrality. Here,the EH system depicted in Fig. 2 is considered, where theharvested power varies sinusoidally such that the source istransient (shown in green). The addition of a tiny capacitanceresults in a marginal lifetime increase (shown in red), however,if the device’s performance (and hence power consumption) isgracefully reduced, a much more significant increase can berealised (shown in blue), potentially alleviating the burden ofsystem hibernation.

In MP-SoCs, this ‘on-the-fly’ performance scaling can bebest achieved through DVFS and DPM (in this work, weprovide DPM through the enabling and disabling of CPU coresat runtime, also known as core hot-plugging). The combinationof these two power management techniques results in avariety of operating performance points (OPPs), each withassociated power consumptions. Fig. 4 shows this for a typical

0 0.5 1 1.5 2 2.5 3 3.5 4Time /s

4

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5

5.5

6

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tage

/V

τPerformance Scaling

Vq

Vwidth

Input (Vsource)Behaviour (VC) with 'small' Supercapacitor C OnlyBehaviour (VC) with Power Neutral Performance Scaling

Minimum Operating Voltage

Vhigh

Vlow

Fig. 3. Behaviour of an EH system to a transient input (green), with (blue)and without (red) power neutral performance scaling.

Operating Frequency (GHz)

0.2 0.4 0.6 0.8 1.0 1.2 1.4P

ower

Con

sum

ptio

n (

W)

1

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1 x A7 Core2 x A7 Cores3 x A7 Cores4 x A7 Cores

4 x A7, 1 x A15 Cores4 x A7, 2 x A15 Cores4 x A7, 3 x A15 Cores4 x A7, 4 x A15 Cores

Fig. 4. Board power consumption vs operating frequency for multiple coreconfigurations, experimentally obtained for the ODROID XU4 embedded SoCplatform whilst running CPU intensive ray tracing software [12].

heterogeneous MP-SoC platform (the Samsung Exynos5422big.LITTLE SoC used for experimental validation in SectionIV, featuring four ‘big’ high performance ARM A15 cores,and four ‘LITTLE’ low-performance ARM A7 cores).

The challenge when devising an effective power neutralcontrol algorithm for heterogeneous MP-SoCs is quickly, andaccurately, identifying the correct OPP at any given instant,such that the consumed power is as close as possible to,without exceeding, the available harvested power.

A. Proposed Control Approach

The proposed approach uses two voltage thresholds, Vhighand Vlow, which are dynamically adjusted as shown in Fig.3. These thresholds monitor the input voltage VC across thesmall capacitor, C, which buffers any latency in the controlsystem (detailed in Section IV-A). Fig. 3 also introducestwo algorithmic parameters, Vwidth and Vq for which optimalvalues are selected through simulation in Section III.

Initially Vhigh and Vlow are calibrated such that they boundVC , with a voltage Vwidth between them, explicitly:

Vhigh(t = 0) = VC+Vwidth

2and Vlow(t = 0) = VC− Vwidth

2(1)

In the event of a reduction in harvested power, VC crossesthe Vlow threshold and the device moves to a lower OPP (asdetermined below). Following this, the thresholds are reducedby Vq . If the harvested power continues to fall, this processis repeated such that the thresholds follow VC , ‘tracking’ the

harvested power supply. A similar but opposite process occursas harvested power increases and VC crosses Vhigh.

B. Operating Performance Point Selection

Fig. 5 illustrates how the performance scaling response isdetermined in the event of a threshold being reached. Initially,as the latency associated with frequency scaling is typicallylower than that associated with core hot-plugging [13], DVFSis performed to deal with ‘micro’ variation in the harvestedpower supply. More specifically, linear control is applied, andthe system’s operating frequency is migrated to the next lowestof N predefined operating frequency levels (f0, f1 . . . fN−1).

Secondly, to deal with the ‘macro’ variation in the harvestedsupply, derivative control is applied to calculate a core hot-plugging response so that the number of active cores isproportional to dVC/dt.

To explain the way in which the core hot-plugging responseis determined, given that we are working within a heteroge-neous multicore architecture, it is useful to define two ternary‘core scaling factors’: Sb for ‘big’ cores, SL for ‘LITTLE’cores, where:

Sx =

1 denotes the addition of a core of type x0 denotes no alteration−1 denotes the removal of a core of type x

Two constant gradient threshold parameters α and β are alsodefined for ‘LITTLE’ and ‘big’ cores respectively, whichrepresent the minimum gradient required to warrant a changein the existing core configuration.

Sb =

1 if dVC

dt > β

−1 if dVCdt < −β

0 otherwise, SL =

1 if dVC

dt > α

−1 if dVCdt < −α

0 otherwise(2)

To minimise overhead, dVC/dt is approximated each time VCcrosses a threshold as:

dVCdt≈ ∆VC

∆τ=Vqτ

(3)

Where τ is the time which has elapsed since the previousapproximation, as shown in Fig. 5. Substituting this into (2)and considering the case when the Vlow threshold is crossed,the core scaling response is:

Sb =

{−1 if τ < Vq

β

0 otherwise, SL =

{−1 if τ < Vq

α

0 otherwise

A ‘big’ core is removed if the rate of change in VC is greaterthan β, a ‘LITTLE’ core is removed if the rate of changein VC is greater than α, else, the core configuration remainsconstant. Again, a similar but opposite control flow occurs inthe event of an increase in harvested power.

III. SYSTEM MODELLING AND SIMULATION

To obtain values for parameters Vwidth, Vq, α and β, theproposed approach was simulated using Matlab-Simulink. Amodel describing the power-OPP characteristics of the MP-SoC platform was created using experimentally obtained data.

Wait for VC to cross a voltage

threhsold

switch(y)

case high: Increace fclk

case low: Decreace fclk

switch(y) case high: Add ‘big’ Core

case low: Remove ‘big’ Core

VC = Vy

N

Y

Start/Reset Timer

( )

Start

Where y represents

‘high’ or ‘low’

N

switch(y) case high: Add ‘LITTLE’ Core

case low: Remove ‘LITTLE’ Core

Y

switch(y) case high: Increment Thresholds

case low: Decrement Thresholds

DVFS Response

Core

Hot-Plugging

Response

Fig. 5. Flowchart depicting the principles of the power neutral performancescaling approach using DVFS and core hot-plugging.

Num

ber

of C

ores

0

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tage

(V

)

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Number of active 'big' coresNumber of active 'LITTLE'' coresVC behaviour with proposed control scheme

VC behaviour without proposed control scheme

Time (s)2 4 6 8

Fre

quen

cy

(GH

z)

0.00.40.81.21.6

VhighVlow

Vmin

Fig. 6. Simulation showing operation of the control algorithm. ParametersVwidth=0.2V; Vq=80mV; α=0.1Vs-1; and β=0.12Vs-1.

This model was used in conjunction with the standard Sim-scape blockset to realise the proposed system shown in Fig.2. The PV EH source was modelled using the solar cellequivalent circuit shown, described mathematically by:

I = Il − I0(

exp(V +RsI

NVT

)− 1

)− V +RsI

Rp(4)

where I0 is the diode saturation current, Rs and Rp are theseries and parallel resistances, VT is the thermal voltage, Nis the quality factor, and Il is the solar generated current. Rs,Rp and N were selected to approximate the behaviour of thePV array used for experimental validation in Section IV, andexperimentally obtained solar irradiance data was used for Il.

Two congruent systems were developed: one where OPPsare selected by a C program implementing the proposed con-trol approach, and one where the performance is static. EightDVFS frequencies corresponding to linearly spaced powerconsumption nodes were chosen, these are 0.2, 0.45, 0.72,0.92, 1.1, 1.2, 1.3 and 1.4GHz. Simulations were performedusing the Matlab ODE23 solver for multiple parameter com-binations whilst assessing the control strategy’s performance.

'LITTLE' A7 Cores Only

Board Power Consumption (W)

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form

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0.25

4 x A7 and 2 x A15 Cores4 x A7 and 1 x A15 Cores4 x A7 and 3 x A15 Cores4 x A7 and 4 x A15 Cores

Fig. 7. Raytrace performance vs power consumption for the operating pointsin Fig. 4, obtained experimentally for the ODROID XU4 platform.

ODROID XU4Multicore SoC

Platform

Monocrystalline PV Array

+

VC-

Voltage MonitoringHardware

(See Fig. 9)

C

Fig. 8. Schematic of the proposed system architecture.

Fig. 6 shows the simulated behaviour of each system ina period of sudden shadowing. The blue line shows the be-haviour of the system with static performance, and the magentaline shows the behaviour using the proposed approach. Here,the control algorithm is effective in scaling performance suchthat VC does not fall below the minimum operating voltage,Vmin, as would happen without it. Through analysing thestability in VC , more specifically the proportion of time spentwithin 5% of the target voltage, best performing values forparameters Vwidth, Vq, α and β were determined as 144mV,47.9mV, 0.120Vs-1 and 0.479Vs-1 respectively.

IV. EXPERIMENTAL VALIDATION

The proposed approach was implemented on the ODROIDXU4 development board, built around the SamsungExynos5422 big.LITTLE SoC. The processor features 8CPU cores (4× ‘LITTLE’ ARM A7 cores and 4× ‘big’ARM A15 cores), and operates between 4.1V and 5.7V.The platform was benchmarked using a CPU intensive raytracing application (smallpt [12]) to provide a parallelisableand intensive workload. Fig. 7 illustrates how the board’sperformance varies with power consumption across multipleOPPs. The performance metric used here is the number offrames rendered per second (FPS) at a quality of 5 samplesper pixel.

Fig. 8 shows a schematic of the proposed system consistingof three parts: an EH source (in this case a PV array), acapacitor to buffer any latency in the control system (detailedin Section IV-A) and the load, an ODROID XU-4 running thepower budgeting software proposed in this paper. In order tominimise software overhead, external low-power circuitry isused to generate hardware interrupts corresponding to Vhighand Vlow. A schematic of this hardware is shown in Fig. 9.Here, a potential divider is used to coarsely reduce the inputvoltage to a level appropriate for the analogue comparator.An SPI controlled digital potentiometer is then used to more

470K

100K

Vc +1.8V(From ODROID Board)

Interrupt Signal

R3

Internal 400mV reference

LT6703HVIS5-3

MCP4131R4

R1

R2

1M

1M

Vc

From ODROID Board

To ODROID Board

SD

I/SD

OS

CK

/CS

Fig. 9. Schematic of the voltage monitoring hardware.

finely reduce the voltage as directed by the processor, henceallowing the processor to set and adjust the threshold voltages.A comparator generates the interrupt signal which is passedthrough an n-channel MOSFET stage to convert the signallevel for compliance with the development board. Overall, twoof these circuits were used in order to facilitate both the ‘Low’and ‘High’ dynamic voltage thresholds.

A. Required Buffer Capacitance

Whilst this work aims to negate the need for the largeenergy buffers which are employed in energy neutral systems,some additional capacitance is required to support the systemthrough the latency period when performing DVFS or core hot-plugging. Fig. 10 shows the overheads associated with bothDVFS and core hot-plugging on the ODROID XU4. Usingthis data, an estimate of the additional required capacitance(C in Fig. 8) can be obtained by considering the worst casescenario, where it is necessary for the system to modulateits performance from the highest OPP (and hence maximumpower consumption) to the lowest OPP (minimum powerconsumption). If the system capacitance can harbour sufficientenergy to tide the processor across this interval, it shouldrespond robustly to any input, provided that it is within thebounds of feasible operation.

There are two ways in which the system may reduce itsperformance in response to a sudden drop in available power. Itmay, (a) perform DVFS followed by core hot-plugging, or (b)perform core hot-plugging followed by DVFS. Both of thesescenarios were practically evaluated and the results are shownin Table I, in addition to the capacitance which would berequired to support the board in each scenario whilst operatingat the lowest voltage. It can be observed from Table I that, ofthe two approaches, approach (b) significantly outperforms (a),and hence the additional required capacitance (C in Fig. 8) is15.4mF. A 47mF supercapacitor was used for the experimentsin this paper to provide a safety margin and to align withavailable components.

V. RESULTS AND ANALYSIS

A. Response to a Controlled Supply

Initial tests were performed using a controlled power supplywithout the additional capacitor C. This permitted verificationthat the SoC’s performance adapts correctly to a changinginput voltage. An example of a single data set is illustrated

Number of Active CPU Cores (Transition)

1 Ë 2 Cores 2 Ë 3 Cores 3 Ë 4 Cores 4 Ë 5 Cores 5 Ë 6 Cores 6 Ë 7 Cores 7 Ë 8 Cores

Lat

enc

y (m

s)

0

10

20

30

40

Operating Frequency = 200MHz

Operating Frequency = 800MHz

Operating Frequency = 1.4GHz

Frequency (Transition in GHz)0.4 Ë 0.2 1 Ë 0.8 1.4 Ë 1.2 0.4 Á 0.2 1 Á 0.8 1.4 Á 1.2

Late

ncy

(ms)

0

1

2

3

1 x A7 Core4 x A7 Cores

4 x A7 Cores, 1 x A15 Core4 x A7 Cores, 4 x A15 Cores

Fig. 10. Latency to switch number of active CPU cores using hot-plugging(top) and to change the operating frequency (bottom), obtained experimentallyfor the ODROID XU4 SoC platform.

TABLE ITIME AND CURRENT EXPENDED WHILST TRANSITIONING FROM THE

HIGHEST TO THE LOWEST OPP.

Scenario TransitionTime, δ (ms)

∫ δ0Idt =

Q (C)Required

Capacitance, C (mF)

(a) Frequency, Core 345.42 0.1299 84.2

(b) Core, Frequency 63.21 0.0461 15.4

Vsu

pply

(V

)

4.4

4.8

5.2

5.6

Fre

quen

cy (

MH

z)

250500750

10001250

Time (s)40 60 80 100 120 140 160

Num

ber

of

Act

ive

Co

res

02468

Number of Small CoresTotal Number of Active Cores

A

B

Fig. 11. System performance using a controlled variable voltage supply.Parameters Vwidth=335mV; Vq=190mV; α=0.238Vs-1; β=0.633Vs-1.

in Fig. 11. Here, large values of Vq and Vwidth have beenchosen for clarity of illustration. The system can be observedresponding as desired, modulating performance in correlationwith the supply voltage. It can also be observed that corescaling is applied less often than frequency scaling, implyingthat the system is selecting long term and transient perfor-mance responses well. For example, minor fluctuations at ‘A’are dealt with through DVFS only, whereas the response to thesudden reduction at ‘B’ involves the disabling of some ‘big’and ‘LITTLE’ cores in addition to DVFS.

B. Response to Energy Harvesting Supply (PV Array)

The system was then tested using energy harvested from a1340cm2 monocrystalline silicon PV array. Fig. 12 shows the

Time (HH:mm:ss)

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paci

tor

Vol

tage

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)

4.0

4.5

5.0

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VcVc,targetVc,target +/- 5%

Fig. 12. VC over time whilst testing the system under full sun conditions.

Voltage (V)1 2 3 4 5 6 7

Cu

rren

t (A

)

0.0

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Per

cent

age

Tim

e (%

)

0

20

40

60

80

Solar cell array current (A)Solar cell array power (W)Time spent at each operating voltage

Fig. 13. IV characteristics of the PV array and the proportion of time spentat each operating voltage.

response of the system over a six hour period, and illustratesthe stabilisation effect that the scheme has on VC in full-sunconditions. The use of the proposed power neutral energybudgeting scheme results in VC remaining almost entirely(93.3% of the time) within ±5% of the target voltage. Thetarget voltage was set at the solar cell’s calibrated maximumpower point (MPP), Pmax, of 5.3V. Fig. 13 illustrates the ef-fectiveness of the scheme’s voltage stabilisation with referenceto the IV characteristics of the PV array, ensuring that theboard is always working at, or close to, the MPP. This negatesthe need for additional sizeable MPPT hardware.

The extent to which power neutrality is achieved by theproposed scheme is shown in Fig. 14 where the estimatedpower available and power consumed over the course of a dayare both plotted for comparison. Available power estimationwas performed by logging the open circuit voltage, Voc(t)of an identical, contiguous PV array, and using experimen-tally obtained IV data to determine corresponding values forPmax(t). The board’s power consumption can be seen tomatch closely the available power supply indicating that thesystem is making good use of the available harvested powersupply, without exceeding it. Testing was performed for over20 hours in a variety of weather conditions (full-sun, partial-sun, cloud, and hail) to examine performance. It was foundthat, in all cases, the system successfully managed to modulateits own performance with respect to the immediately availableharvested power such that (provided the harvested supply wassufficient) the device could perpetually sustain operation.

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15:

00

Pow

er (

W)

1.5

2.0

2.5

3.0

3.5

Power consumed by ODROID XU4Estimated Available Harvested Power

Fig. 14. Available (estimated) and consumed power over the course of a day.

TABLE IIPERFORMANCE OF POWER MANAGEMENT SCHEMES IN A 60 MINUTE TEST.

Power ManagementScheme

Avg.performance(Render/min)

LifetimeDuring Test

(mm:ss)

InstructionsCompleted(Billions)

Linux Conservative 1.0127 00:05 24.0

Linux Powersave 0.1456 60:00 2485.6

Proposed Approach 0.2460 60:00 4200.4

C. Comparison with Linux Governors

The proposed performance scaling approach was also com-pared to each of the default Linux power management gover-nors whilst harvesting energy from the solar PV array. Duringa one hour test, the results shown in Table II were obtained(Performance, Ondemand, and Interactive governors could notsupport any operation due to their high current requirements).The proposed performance scaling approach outperforms allof the available static Linux power management governors,allowing the system to operate for the full testing duration inaddition to exhibiting enhanced performance when comparedto the Powersave governor (which statically reduces perfor-mance to a minimum [14]), completing an estimated 69.0%more instructions over the same time period.

D. Overheads of Proposed Approach

Fig. 15 illustrates the CPU usage of the proposed approachcompared to that of the target application. Due to the interruptbased approach, the impact of the control scheme on CPU timeis very low, averaging at 0.104% over the full testing duration.The power consumption of the additional voltage monitoringhardware was also measured, and found to be 1.61mW, lessthan 0.82% of the minimum system power consumption (and0.01% of the maximum).

VI. CONCLUSIONS

This paper has proposed a novel approach for achievingpower neutral operation in energy harvesting multicore embed-ded systems. The power neutral performance scaling approachtracks harvested power through the use of two dynamic voltagethresholds, and alters performance accordingly through DVFSand DPM. The approach has been validated through both sim-ulation and practical experimentation using a monocrystallinePV array. Results demonstrate effective voltage stabilisation

Time (HH:mm:ss) 14:22:00 14:27:00 14:32:00 14:37:00

Ava

ilabl

e C

PU

Usa

ge (

%)

0

1

2

3

97

98

99

100

CPU Usage of Other System TasksCPU Usage of Power Budgeting SoftwareCPU Usage of Ray Tracing Application

Fig. 15. CPU usage over time, showing overhead of proposed approach.

under all weather conditions, allowing the system to operateperpetually without the large energy buffers associated withconventional energy harvesting systems.

ACKNOWLEDGMENT

This work was supported in part by EPSRC GrantsEP/L000563/1 and EP/K034448/1 (the PRiME Programmewww.prime-project.org).

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