Power, Noise and Reliability Analysis for Automotive Electronic Systems
2012 Automotive Simulation World Conference
Environment
Safety
Networking
Affordability
Interference
Scalability
Energy Efficiency
Reliability
“Megatrends” in Automotive Electronics
• Connectivity• Compliance
• Electro-mobility• Powertrain
Control
• Reliability• Smart Sensors
• Cost• Robustness
Motivation for Power ReductionESL Design
Physical Design
Logic Synthesis
GDSII
RTL Design
“Automotive OEMs are demanding lower power-consuming devices with smaller footprints and better performance to address broader concerns about the environment and fuel consumption.” Renesas, EETimes Europe, July 2012
“Automotive OEMs are demanding lower power-consuming devices with smaller footprints and better performance to address broader concerns about the environment and fuel consumption.” Renesas, EETimes Europe, July 2012
Automotive Applications Containing Microcontrollers2008 Faculty of Engineering and Applied Science,
Queen's University Kingston, Ontario, Canada
Chip Temperature
Chip Power Density
Motivation for Power Integrity AnalysisDriver: Airbag Safety
• Operation of safety (airbag) systems depend on MCU speed
• Operating speed of MCU depends on quality of power supply it receives
Design Impact: MCU Performance• Poor PCB design can cause 100+mV drop• Can reduce MCU performance by more than 40-60MHz
• Must design PCB considering MCU and impact on its performance
Voltage Drop Electromigration
“… power consumption is the main driver for the move to dual-core MCUs … to handle next-generation power train control.”
“… power consumption is the main driver for the move to dual-core MCUs … to handle next-generation power train control.”Freescale, EETimes, 10/12/2011
Airbag Control Unit based on MCU (Bosch)
IC-Level Power Integrity Analysis Maps
Motivation for System Thermal“…the auto industry is migrating from purely mechanical and hydraulic systems to electromechanical or mechatronicsystems. This requires locating sensors, signal conditioning, and control electronics closer to heat sources.”Analog Devices, Analog Dialogue, April 2012
Thermal Challenges of Automotive Electronics• System-wide issue for Automotive Electronics• Close proximity of on-board electronics creates
cooling challenge• Materials with high thermal conductivity may be used
(and need to be modeled in analysis) Thermal Simulation Requirements• Chip Thermal Model• Thermal Boundary Conditions• Package/PCB Thermal Modeling• Thermal Back-annotation to IC
Evans, et al. IEEE Trans. on Electronics Packaging Manufacturing, Vol. 27, No. 3, 2004
Max. temperature ranges in automotive systems
Average semiconductor content of automobile increases 15% per year• EMI is a key safety concern• Traditional EMI modeling neglects core noise
Requirements for Electronic Systems:EMI / EMC Compliance
Simulation Requirements• Chip emission modeling (core, I/O)• Package/PCB/cable radiation
analysisIncreasing need to predict the true post-silicon EMC behavior vs. increasingly aggressive EMC targets dictated by marketing, customers, and international standardsDr. Davide Pandini, ST Microelectronics
Increasing need to predict the true post-silicon EMC behavior vs. increasingly aggressive EMC targets dictated by marketing, customers, and international standardsDr. Davide Pandini, ST Microelectronics
System EMI
ST Microelectronics, Doriol et al., DAC 2009ST Microelectronics, Doriol et al., DAC 2009
Components in Automotive Electronics
MCU:Chip inside wire-bond package
Printed circuit board (PCB) with multiple package chips Chip (IC)
Package
PCB
Design Flow for Power/Thermal Management
• Power-Performance-Area Trade-offs• Identify and eliminate power bugs
RTL PowerChip Architecture
PowerArtist
• Early Grid Prototyping• Power Integrity Verification
IC PowerRedHawk/Totem Chip Design
Sentinel/Icepak • System PI, SI, EMI, thermal• Cost down and risk mitigation
System PowerSystemDesign
CPM /CTM
Chip
Netlist
PowerArtist : RTL Power Management
Synthesis
Power Consumption
Debug
AutomaticAnalysis-Driven
Power Reduction
Design Flow for Power/Thermal Management
• Power-Performance-Area Trade-offs• Identify and eliminate power bugs
RTL PowerChip Architecture
PowerArtist
• Early Grid Prototyping• Power Integrity Verification
IC PowerRedHawk/Totem Chip Design
Sentinel/Icepak • System PI, SI, EMI, thermal• Cost down and risk mitigation
System PowerSystemDesign
CPM /CTM
Power Integrity Impact Analysis
Chip (IC)Package
PCB
PackageParasitic
Model(SIwave)
PCBParasitic
Model(SIwave)
Chip Power Model(RedHawk-CPM)
V
Yellow ~ voltage at MCU with pkg/PCBRed ~ voltage at MCU/pkg but no PCB
-100+mV drop from PCB- MCU speed lower by 40MHz
• CAD flow independent (GDS/DEF/Netlist/Models)• Operate on industry standard formatsIP Modeling
• Only solution for on-die ‘L’ extraction and simulation• Silicon validated down to 22nmSoC Integration
• Pico-second resolution• Best-in-class performanceSimulation
• Enable automatic and user-guided debug• Interactive ‘what-if’ and incremental simulation
Root Cause Identification
• Single-step model creation out of RedHawk• Multi-domain, distributed and coupled
Chip Power Model
SoC Power Supply Noise Analysis StepsChip (IC)
Package
PCB
SoC Power Noise Analysis Requirements
Capacity
• Multi-core switching• Hierarchical modeling• Package inclusion
Analysis
• Functional / Scan / IR• Low-power• Power / Signal EM
Accuracy
• Power gate turn-on/off• 28/20nm extraction• Pico-second resolution
Yong et al, DAC 2010
RedHawk: Chip-Package-System EnablementChip
Package
PCB
Kaisheng (Klaus) Hu et al, Ciena, DAC 2012
Without PKG/PCB
With PKG/PCB
System-Aware IC IC-Aware System
AC Impedance Analysis
Package Voltage Drop
Totem: Custom Analog and RF Designs‘Analog Mixed-Signal Support’
• Complex RF Designs• Custom Analog Designs• PMIC Designs• I/O Designs : DDR , SERDES
Totem Totem Totem
S-parameter Model Support for PKG+PCB
Mixed-Signal SupportEmbedded LDO
Power Gated Designs
Reliability: Noise Analysis for Automotive• Today’s auto chips combine high-voltage switching and 1V CPUs
– E.g. engine controller with actuator outputs• How to prevent high-V noise from upsetting low-V circuits?
– Use IC processes with special isolation features for DC isolation, AC shielding– Careful chip/package/system design to limit noise coupling
• Totem Substrate analysis enables chip designers to analyze noise impact– Substrate-conducted noise– Inject, simulation, measure noise– Visualize noise levels to suggest solutions
IPwith nwell guard ring
User Defined Noise PWL Waveform
p+ n+ n+ p+ p+ n+
Gnd DVdd
n+ n+ p+ p+
Analog Block I/O Ring
Isub
Digital Block
AGnd
epi
p-well n-well
Bulk
n+
n-well Ring
Guard Ring
p-well
p+
AVdd
n-well
Design Flow for Power/Thermal Management
• Power-Performance-Area Trade-offs• Identify and eliminate power bugs
RTL PowerChip Architecture
PowerArtist
• Early Grid Prototyping• Power Integrity Verification
IC PowerRedHawk/Totem Chip Design
Sentinel/Icepak • System PI, SI, EMI, thermal• Cost down and risk mitigation
System PowerSystemDesign
CPM / CTM
18
Electrical Co-Design of Chip-Package-System
• Chip Power Model (CPM)– Captures chip current and RLC parasitics– SPICE-ready– Direct CPM import enablement
• Co-Design Enablement:– AC, DC, Transient Analysis– Package, PCB de-cap planning and
optimization– Thermal Analysis– System-level EMI, Far Field, Near Field
Chip Design
Prototype
Design
Sign-off
Package / PCB Design
Selection, Planning
Package Design
System Sign-off
Chip ModelsPower, Signal, Thermal, EMI
Co-Design Enablement of Chip-Package-System
Full-wave Package/Board SolutionsHybrid
Board + PackagePackage
SIwave
Fast 3D
Sentinel PSI
• Fast FEM using prism elements • Tailored for PI package analysis• Complements SIwave for those problems with arbitrary 3D effects
• FAST Hybrid method for PKG/BRD• Handles many, but not all 3D effects
FastIC PackagesGood Trade-off of Speed
With 3D Accuracy
Arbitrary 3DArbitrary 3D Electro-magnetics
HFSS
• Golden Accuracy Simulator• Solves Any 3D geometry• Powerful for Critical Nets
Any GeometryGold Standard Accuracy
SPEED
21
System ACSimulationSystem ACSimulation
Package/PCBDC AnalysisPackage/PCBDC Analysis
Capacitor in packageCapacitor in board
BGA Package Bulk capacitorCPM
Chip-Package-System PDN Analysis
Capacitor placementCapacitor placement Time domain system analysisTime domain system analysis
Traditional thermal simulation• May/may not include chip power signature• Will not consider power-thermal loop• Will not include chip metal density
Benefits of using Chip Thermal Model• Multi-layer detailed thermal model• Highly granular• Provides accurate thermal model for system- level (Icepak) simulation
With CTMLayout, activity power profile
Chip Thermal Profile
IC Simulation(RedHawk)
Package Simulation(Sentinel-TI)
System Simulation(Icepak)
CTM
Conv. Power MapBoard current(1)
Temperature Map
Heat transfer co-efficient
Chip-aware package and
system thermal analysis
System-aware package and chip
thermal and reliability analysis
Thermal Management Flow for Automotive
• Cooling simulation for single and rack mounted boards
• Import EDA layout data from a variety of board layout tools
• Detailed thermal conductivity map for PCB layers
• Import Chip Converged Power Map• Export temperatures to ANSYS Mechanical
for thermal-stress
Printed Circuit Board Thermal Analysis
Motivation for EMI Analysis
Proj
ect D
evelo
pmen
t Pha
se
EMI needs to be improved in all of above levels
Currently EMI checks done here only
*ST Microelectronics, Doriol et al., DAC 2009
ANSYS-Apache CPS EMI Flow
CPM
HFSS/SIwave/Sentinel-PSI
Near/Far Field Radiation
Apache
Chip-Package-System EMI SimulationIC
-leve
l EMI
Ho
tspo
t Ana
lysis
Smartphone EMI Simulation in HFSS
CPM from RedHawk
Smartphone EMI Simulation in HFSS
CPM from RedHawk
Sentinel-PSI Package EMI MapSentinel-PSI Package EMI MapSentinel-PSI Package EMI Map
2nd harmonic2nd harmonic 5th harmonic5th harmonic2nd harmonic 5th harmonic
Chip
-awa
re S
yste
m
EMI A
nalys
is
RedHawk: EMI Source Maps
System ESD Immunity Simulation
LeadframePackage PCBPCB
I/O Ring Power GroundMacro-Model
VRM
Termination
I/O Cell
ESDIO
I/O Cell
Decap
Stimulus
Chip Discharge Model
IEC-61000-4-2
Addressing Power Noise Challenges for Automotive Electronics
Analysis Design Impact
Power Budgeting Ensure MCU meets power envelope
Power Integrity Ensure MCU will operate at desired clock frequency
EMI Meet regulatory EMI/EMC requirements for system
Thermal Simulation Develop thermal management solution necessary to achieve performance and reliability target
Reliability (ESD) Protect components during assembly and operation
Comprehensive Chip-Package-System simulation solutions
Architecture IP SoC Package PCB
Enable design prototypingIdentify errors early in the process
Reduce overall system cost
Enabling ‘Converged’ Electronic Designs for Automotive Applications