Power Supply DesignParameters Prediction for High
Performance IC Design FlowM. Graziano, M. Delaurenti, G. Masera, G. Piccinini, M. Zamboni
Electronics Department, Politecnico di Torino
April, 8-9 2000
Summary.
Summary
�Introduction: noise in VLSI circuits�IR drop and � ������ causes, scale and consequences�Proposed methodology to face these problems�Power Supply Model�Noise cost function�Conclusions
1M. Graziano, M. Delaurenti, G. Masera, G. Piccinini, M. Zamboni.Power Supply Design Parameters Prediction for High Performance IC Design FlowApril, 8-9 2000
Introduction.
Introduction: noise in VLSI circuits
Technology scaling down leads to:�increasing chip size�increasing clock frequency�increasing interconnect density�
noise jeopardizes UDSM circuits functionality:�crosstalk�electromigration�ground bounce
� � �������IR drop
2M. Graziano, M. Delaurenti, G. Masera, G. Piccinini, M. Zamboni.Power Supply Design Parameters Prediction for High Performance IC Design FlowApril, 8-9 2000
IR drop and L dI/dt .
IR drop causes
Transistor and interconnection scaling down causes�increased gate number w/o area change�
greater number of gates in a rowgrowing current on power supply lines�
increased line resistance
�
increased GND and VDD area for electromigration�rise of IR drop
3M. Graziano, M. Delaurenti, G. Masera, G. Piccinini, M. Zamboni.Power Supply Design Parameters Prediction for High Performance IC Design FlowApril, 8-9 2000
IR drop and L dI/dt .
����� causes
Transistor sizes scaling down causes:�increased frequency of the clock signal�
higher gate switching activityhigher electromigration riskdecreased clock rise time: higher � ������ foron chip and package inductances
4M. Graziano, M. Delaurenti, G. Masera, G. Piccinini, M. Zamboni.Power Supply Design Parameters Prediction for High Performance IC Design FlowApril, 8-9 2000
IR drop and L dI/dt .
IR drop and����� influences on Power Supply
�Higher sensibility of gates to noise spikes:
delay, charge alteration, reduced � ��Crosstalk towards neighbor lines�EMI problems towards neighbor circuits�Ground bounce injected into the substrate
5M. Graziano, M. Delaurenti, G. Masera, G. Piccinini, M. Zamboni.Power Supply Design Parameters Prediction for High Performance IC Design FlowApril, 8-9 2000
IR drop and L dI/dt . Simulations
IR drop influence: simulations
gnd
vdd
gnd
vdd
gnd
vdd
vdd
gnd
6M. Graziano, M. Delaurenti, G. Masera, G. Piccinini, M. Zamboni.Power Supply Design Parameters Prediction for High Performance IC Design FlowApril, 8-9 2000
IR drop and L dI/dt . Simulations
IR drop: simulation parameters
�AND2 TSPC, 0.25 � m, 2.5V, 1Ghz�Growing number of cells: from 200 up to 600�Different parasitic inductance conditions: on chip
distributed (0.2pH), package (1pH – 10pH)�Distributed parasitic resistance function of electromigration
sizing
7M. Graziano, M. Delaurenti, G. Masera, G. Piccinini, M. Zamboni.Power Supply Design Parameters Prediction for High Performance IC Design FlowApril, 8-9 2000
IR drop and L dI/dt . Simulations
IR drop: simulations results
0.2pH, Dist.
1pH, Pack.10pH, Pack
2
2.5
3
3.5
300 400 500 600 700 800 900
Noi
se O
vers
hoot
[V
]
200 gates
600 gates400 gates
Noise Width [ps]
1.5
1
0.5
8M. Graziano, M. Delaurenti, G. Masera, G. Piccinini, M. Zamboni.Power Supply Design Parameters Prediction for High Performance IC Design FlowApril, 8-9 2000
Methodology.
Verification or prediction?
�Verification of noise failures has expensive time-to-market
aftereffects�Countermeasures are strongly joined to designer
intervention�It’s basic to develop design tools facing early in the
design sequence the
potential noise generation
9M. Graziano, M. Delaurenti, G. Masera, G. Piccinini, M. Zamboni.Power Supply Design Parameters Prediction for High Performance IC Design FlowApril, 8-9 2000
Methodology.
Noise Cell Views and Cost Function
EME
CELL VIEWDE
SCR
IPT
ION
AND PLAC
ALG
NT
TH
OR
IM
S
FLOORNING
PLAN
NetlistNoise Injection
Cell View
Cell ViewNoise Tolerance
HDL
Layout
Interconnect Density
DelayPower
NOISE COST FUNCTION
Area
10M. Graziano, M. Delaurenti, G. Masera, G. Piccinini, M. Zamboni.Power Supply Design Parameters Prediction for High Performance IC Design FlowApril, 8-9 2000
Methodology.
Methodology: instruments
Synergy among tools related to different design phases is
needed:�transistor sizing optimization tool�gate noise tolerance analysis�cell model with noisy power supply references�
row of cells model: the influences between the cell
and its environment
11M. Graziano, M. Delaurenti, G. Masera, G. Piccinini, M. Zamboni.Power Supply Design Parameters Prediction for High Performance IC Design FlowApril, 8-9 2000
Power Supply Model.
Power Supply Model: uniform sizing
I II
Z
I s1
p1 p pN
Is I s I si i+1 N I sN+1
Z1
I
Is i-1
Ipi+1
VZiZi-1ZZ1 VN N+1Ni+1i+1Vi+1i-1VV
pi-1 i
The maximum current is����� � ����� ����� � �! #"
while the worst overvoltage is
� � � �%$ � � & ����� �'��� ( ���� �)��� ��� �� *+� �'�-,. & /"0� ( ���� #"
12M. Graziano, M. Delaurenti, G. Masera, G. Piccinini, M. Zamboni.Power Supply Design Parameters Prediction for High Performance IC Design FlowApril, 8-9 2000
Power Supply Model. Uniform sizing
Uniform sizing, noise prediction
Maximum noise overvoltage is known from the number of
cells inserted on the line, or vice-versa
As a drawback the area of a GND line is:1 243+576 � � �98;:=< � 6 �?> @ ACB
13M. Graziano, M. Delaurenti, G. Masera, G. Piccinini, M. Zamboni.Power Supply Design Parameters Prediction for High Performance IC Design FlowApril, 8-9 2000
Power Supply Model. Optimized dimensioning
Area optimization without noise worsening
�Area waste due to worst current value used to
dimension the whole line�Ideal sizing: GND and VDD line width for cell D proportionalto the maximum current at point D�Real sizing: a controlled and optimized line segmentation is
proposed
14M. Graziano, M. Delaurenti, G. Masera, G. Piccinini, M. Zamboni.Power Supply Design Parameters Prediction for High Performance IC Design FlowApril, 8-9 2000
Power Supply Model. Optimized dimensioning
Optimized dimensioning
g ( M - 1 )wmax - wmin
g ( M - 1 ) = M - 1
∆ w =
cellsM
Ncells
M M
NNcells cells
M
N
Mcells
N
Mcells
N
Mcells
N
Mcells
N
Mcells
N
cellsM
N
row1
row2
VD
D
0
wm -> Rm
node
nodenodeN
GN
DG
ND
node
VD
D
0
N
15M. Graziano, M. Delaurenti, G. Masera, G. Piccinini, M. Zamboni.Power Supply Design Parameters Prediction for High Performance IC Design FlowApril, 8-9 2000
Power Supply Model. Optimized dimensioning
Optimized dimensioning: gain and loss
The area gain is E A � F 2HG. > @ ACB F > @ � �and the noise loss due to increased resistance is:
E �I � ����� �'�� ��� J@
K L �NM KF J � ="� ��� � JO J � � J �
� @K L � M K
� � .@
K L �QPF R S M K F
� � JOwhere T K � U V
8 ��
J> @ ACB M K W R XQ> @ � � X�Y P R F J S[Z
16M. Graziano, M. Delaurenti, G. Masera, G. Piccinini, M. Zamboni.Power Supply Design Parameters Prediction for High Performance IC Design FlowApril, 8-9 2000
Power Supply Model. Optimized dimensioning
Optimized dimensioning: overvoltage control∆
Ν Τ∆
ΑLosses at node N when optimizing for area: N parametric
area gain
2 cells for block m
w_min = w_MAXW_MIN
100 cells for block m
w_min = TEC_MIN
20 cells for block m
17M. Graziano, M. Delaurenti, G. Masera, G. Piccinini, M. Zamboni.Power Supply Design Parameters Prediction for High Performance IC Design FlowApril, 8-9 2000
Power Supply Model. Optimized dimensioning
Optimized dimensioning: design parameters
Using a good number of segments with increasing dimen-
sions the number of cells does not influence the loss in noise
safety.
The designer has control on area and noise, varying�number of gates in a row
��
number of segments having different width�width at the line endpoints
> @ ACB XQ> @ � �
18M. Graziano, M. Delaurenti, G. Masera, G. Piccinini, M. Zamboni.Power Supply Design Parameters Prediction for High Performance IC Design FlowApril, 8-9 2000
Power Supply Model. Noise Reduction
Noise reduction: distributed capacitors
0.25
0.350.4
0.450.5
0.550.6
0.650.7
0.750.8
400 gates
200 gates
0.3
200 400 600 800 10000
Distributed capacitance [fF]
Maximum overvoltage versus distributed capacitorsO
vers
hoot
[V
]
600 gates
19M. Graziano, M. Delaurenti, G. Masera, G. Piccinini, M. Zamboni.Power Supply Design Parameters Prediction for High Performance IC Design FlowApril, 8-9 2000
Power Supply Model. Noise reduction
Decreased current to shrink resistance
b)
c)
a)
Isi
Isi Isi+1
Isi+1
Ip Ic
Ip
Isi = Ip + Isi+1
l cap
l gate
l gate
Isi = (Ip - Ic) + Isi+1
20M. Graziano, M. Delaurenti, G. Masera, G. Piccinini, M. Zamboni.Power Supply Design Parameters Prediction for High Performance IC Design FlowApril, 8-9 2000
Power Supply Model. Noise reduction
Distributed capacitors: loss and gain
Noise overshoot variation
� � \\\\]0^`_?ab
Power Supply Model. Noise reduction
Distributed capacitors design parameters
If the line width is chosen between
� W =" F b Z J � 8 :=< � 68 b
Future model developments.
Future model developments
�conjunction of optimized dimensioning and of distributed
capacitors insertions� " � � " P �QS and � � � � � P �QS�clock skew modeling in the current superposition and
overvoltage evaluation�package influence on row model�extension to S.O.C. designs
23M. Graziano, M. Delaurenti, G. Masera, G. Piccinini, M. Zamboni.Power Supply Design Parameters Prediction for High Performance IC Design FlowApril, 8-9 2000
Noise Cost Function.
Noise Cost Function
A Noise Cost Function to be introduced in a placement algo-
rithm is influenced as shown before byNoise overvoltagePower supply lines areaElectromigrationNumber of cells in a rowDistributed optimized capacitorsNumber of optimized segments
24M. Graziano, M. Delaurenti, G. Masera, G. Piccinini, M. Zamboni.Power Supply Design Parameters Prediction for High Performance IC Design FlowApril, 8-9 2000
Conclusion.
Conclusions
�The aim is to create a NOISE COST FUNCTION to be inserted
in a placement algorithm�it is based on:�
a cell description with noise characteristics�a cell environment description with noise generation
parameters�it is of basic impact to face early in the design sequence the
potential noise aftereffects
25M. Graziano, M. Delaurenti, G. Masera, G. Piccinini, M. Zamboni.Power Supply Design Parameters Prediction for High Performance IC Design FlowApril, 8-9 2000