Pseudo-Random SequencesA truly random sequence of binary symbols (ones and zeros, for simplic-

ity) would be one for which a knowledge of the complete past history of thesequence would be of no assistance in predicting the next symbol, i.e. theprobability that the next symbol would be a one or zero would still be one-halfeven if the complete sequence of previous output were available. Such a se-quence would have to be produced by passing an analog noise source througha comparator sampled at regular clock intervals or some other scheme such astossing a fair coin. Such a sequence is sometime referred to as digital noise.

Figure 1: Pseudo-Random Sequence Generator

A pseudo-random sequence is one that appears to be perfectly randomfor K output symbols but then repeats, i.e. it is periodic with a cycle timeof K symbols. If K can be made large enough, this is not a great limitation;any interval up to K symbols will appear to be perfectly random. Sucha sequence can be constructed using shift registers and EXCLUSIVE-ORgates. Shown in Fig. 1 is an N stage shift register. Each time a clock pulseis applied the state of the shift register shifts one stage to the right; the stateof the �nal stage [N] is lost and the input to the �rst stage [1] is obtainedby EXCLUSIVE-ORing a set of the stages of the shift register. Typically,stage N provides one of the EXCLUSIVE-OR inputs, while the other inputis drawn from stage M; other possibilities involve the EXCLUSIVE-OR ofthe �nal and a number of lower stages. The output sequence is usuallyconstructed by taking the consecutive values of any one stage; stage N ismost commonly used. These circuits or machines are known as feedbackshift registers or pseudo noise generators.If the feedback taps (stages chosen as inputs to the EXCLUSIVE-OR

gate) are properly chosen, a maximal length shift register sequence can beobtained. For an N stage shift register, K = 2N � 1 for a maximal length

1

shift register sequence. Such a circuit goes by a number of names: pseudo-random sequence generator or maximal-length shift register sequence gener-ator, pseudo-random bit sequence generator, pseudo-randon noise generator,or a pseudo-noise generator. Not all settings produce a maximal-length se-quence, viz. they have cycle periods less than K. The selection of the propertaps to produce a maximal-length pseudo-random sequence for an N stageshift register is an arcane topic in higher mathematics.Assuming that the taps have been selected to produce a maximal-length

pseudo-random sequence, the state machine or circuit shown in Fig. 1 wouldproduce an output sequence having one more 1 than zero�all theN bit binarynumbers from 1 to N ones would be present in the N bit shift register fordi¤erent clock pulses (all zeros is excluded because it would cause the shiftregister to latch-up in the all zero state). If the EXCLUSIVE-OR gate isfollowed by an inverter, the complement of the previous output sequence willbe obtained which will have one more zero than one. The state of the shiftregister for various clock cycles assumes all of the N bit binary numbers withthe exception of the all zeroes state.Because K depends exponentially on N , this makes it possible to have

very long pseudo-random sequences. For instance, with a 33-bit (stage) reg-ister clocked at 1 MHz the cycle time would be over 2 hours and with a100-bit register clocked at 10 MHz the cycle time would be around 27,000times the estimated age of the universe which is 15 billion years. Thus, evenat relatively high clock rates, it is possible to produce pseudo-random se-quences that would take centuries to repeat. They can be used as randombinary sequences for any time interval less than the cycle time.Pseudo-random sequences have numerous applications in electrical and

computer engineering�especially telecommunications. A pseudo-random ana-log noise source can be obtained by low-pass �ltering the output of thepseudo-random sequence where the cuto¤ frequency of the �lter should bemuch less than the clock frequency of the sequence generator. Such a se-quence may be used to scramble data for security reasons (EXCLUSIVE-ORing the data stream with the pseudo-random sequence at the trans-mitter and then reversing the procedure at the receiver with the identicalpseudo-random sequence which is known only to the valid users). Digitalpseudo-random sequences are used extensively in error-correcting and de-tecting codes. Because they have very peaked autocorrelation properties,they are widely used radar ranging and GPS systems. The almost randombut repeatable nature of pseudo-random sequences are widely used in spread

2

spectrum communications systems such as digital cell phones that use CDMAtechnology to, among other things, give each digital cell phone a unique code.

Procedure� The only dc power supply buses that will be used in this experimentare +5 V and ground. The ICs are TTL digital ICs which wouldbe incinerated by other voltages. The 100 Ohm resistor and 100 �Fcapacitor should be used on the +5 V bus.

� Each ECE 3042 Parts kit has 2 74LS74 D �ip �ops. The 74LS164 eightbit shift register and 74LS86 EXCLUSIVE OR will be supplied. Returnthem to the lab instructor when no longer needed.

� Using either the 74LS74 �ip �op IC or the 74LS164 shift register ICassemble several shift registers having lengths from 2 to 8 and exper-imentally determine the feedback taps that produced maximal lengthPN sequences. Plot the time domain and frequency domain displaysand use either Benchlink or Intulink to make plots for inclusion in thereport.

� If necessary use the LM 311 comparator to clean up the output se-quence.

� Listen to the sound produced by the connecting a small speaker tothe output of the sequence. Experiment with making the sound moremelodious by inserting a �lter between the output of the sequence andthe speaker.

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