Practical Digital Pre-Distortion Techniques for PA ...LTE DPD simulation for a memoryless nonlinear...

Practical Digital Pre-Distortion

Techniques for PA Linearization

in 3GPP LTE

Copyright Agilent Technologies 2010SystemVue DPD

Jinbiao XU1

Agenda

• Digital PreDistortion----Principle

• Crest Factor Reduction

• Digital PreDistortion Simulation

• Digital PreDistortion Hardware Verification

Copyright Agilent Technologies 2010

2

Digital Pre-Distortion----- Principle

outP

Linear Response

Input Power

Output PowerSaturation

Psat

pd-outP Operating region

with predistortion

Operating region

without predistortion

o-pd = k out

Input Power

Output Phase

Pi Pi-pd

Desired Output Linear Output


3


4

Actual Amplifier Amplitude ResponseDPD Amplitude Response Linear PA Amplitude Response

DPD PA PA

PA-1

input x y input x

Digital Predistortion function brings in distortions out of phase with those

generated by the PA/TRx nonlinearities.

Need to model the PA behavior accurately and

efficiently for successful DPD deployment



Predistorter

(Copy of A)PA

input x(n) y(n)

• Step 1: Understand the physical mechanisms behind the

PA’s behavior. Extract nonlinear coefficients from PA input

and PA output waveform.

• Step 2 :Based on Step1, Construct a model to accurately

capture both the static nonlinearity and the memory

effects

Predistorter

(Training A)

1/SSG

e(n)

x’(n)

x(n): PA input signal

y(n): PA output signal

x’(n) : simulated PA input signal

e(n): error signal

SSG: Small Signals Gain


5

Digital Pre-Distortion----- Memory Polynomial

• Memory Polynomial reduces Volterra’s model complexity

while retaining its comprehensive modeling capability

• It leaves only the dominant distortion terms of the Volterra

series; the diagonal kernels by ignoring the cross‐terms

• It represents a good trade‐off between complexity and

model accuracy, especially when used to construct a DPD

• It is expressed as:

N: Nonlinearity order

M: Memory order

1

0

1

1

1)()()(

M

p

N

q

q

pq pnxpnxany


6

Crest Factor Reduction (CFR)

• Signals with high spectral efficiency have high peak-to-average power

ratios (PAPR).– Multi-carrier signals.

– CDMA (WCDMA, CDMA2000)

– OFDM (LTE, WiMAX).

• Crest factor reduction (CFR) of wide bandwidth signals

– Power amplifiers can operate closer to saturation.

– Higher power added efficiency.

– Must comply with spectral mask and EVM specifications

CFR Algorithm

• Clip and filter– Find peaks above a threshold and create a clipped error.

– Band limit clipped error and subtract it from waveform.

• Constellation extension– Map opposing constellation points to one symbol.

• Tone reservation– Transmit on unused sub-carriers to reduce peaks.

• Partial transmit sequence, selective mapping– Phase shift blocks of sub-carriers to reduce peaks.


7

Crest Factor Reduction (CFR)----Clip and Filter for

OFDM• Control EVM and band limit in frequency domain.

– Constrain the degradation on individual sub-carriers.

• Do not degrade pilots, reference signals, or P-SS, SSS.

• Constrain constellation errors to avoid bit errors.– Allow QPSK sub-carriers to be degraded more than 64 QAM sub-carriers.

S/PZero

PadCFR IFFT

Add

CPP/S DAC

IFFT Clip FFTEVM

ControlFilter


8

LTE CFR (Crest Factor Reduction)

LTE Downlink 10MHz,

Sampling Rate 61.44MHz,

QPSK,

EVM threshold 10%

Simulation Results

FFT

FreqSequence=0-pos-neg

Direction=InverseSize=4096 [DFTSize]

FFTSize=4096 [DFTSize]ifft2

0+0*j

Value=0 [0+0* j]zeros

Gain=1

G3

Gain=1

G2

A

BlockSizes=1;300;3495;300 [[1,Half_UsedCarriers,DFT_zeros,Half_UsedCarriers]]

A3

A

BlockSizes=300;300 [[Half_UsedCarriers, Half_UsedCarriers]]

A2

FFT


Direction=ForwardSize=4096 [DFTSize]

FFTSize=4096 [DFTSize]

fft

FFT


Direction=InverseSize=4096 [DFTSize]

FFTSize=4096 [DFTSize]

ifft1

0+0*j

Value=0 [0+0* j]

DC

DPD_Radius Clip

input out put

ClippingThreshold=16.5e-6 [ClippingThreshold]

DPD_RadiusClip

DPD_LTE_CFR_Post Pr oc

input

r ef

SC_St at us

Qm

out put

OutOfBandAlgorithm=Armstrong algorithm

EVM_Threshold_64QAM=0.1 [EVM_Threshold_64QAM]EVM_Threshold_16QAM=0.1 [EVM_Threshold_16QAM]

EVM_Threshold_QPSK=0.1 [EVM_Threshold_QPSK]

SSS_Ra=0 [SSS_Ra]PSS_Ra=0 [PSS_Ra]

UEs_Pa=0;0;0;0;0;0 [UEs_Pa]

PDSCH_PowerRatio=p_B/p_A = 1 [PDSCH_PowerRatio]PDCCH_Rb=0 [PDCCH_Rb]

PDCCH_Ra=0 [PDCCH_Ra]PBCH_Rb=0 [PBCH_Rb]

PBCH_Ra=0 [PBCH_Ra]

PHICH_Rb=0 [PHICH_Rb]PHICH_Ra=0 [PHICH_Ra]

PCFICH_Rb=0 [PCFICH_Rb]

RS_EPRE=-25 [RS_EPRE]OtherUEs_MappingType=0;0;0;0;0 [OtherUEs_MappingType]

UE1_MappingType=0;0;0;0;0;0;0;0;0;0 [UE1_MappingType]CyclicPrefix=Normal [CyclicPrefix]

OversamplingOption=Ratio 4 [OversamplingOption]

Bandwidth=BW 10 MHz [Bandwidth]D1


9

DPD Simulation Workspace

Step 1 is to Generate Waveform for DPD

Step 3 is for DUT Model Extraction

Step 4 is for DPD Response

Compared with hardware verification tool,

simulation tool does not include Step 2

and Step 5.

Hardware verification toll will be

introduced later.


10

LTE DPD simulation for a memoryless nonlinear PA

Gain=0 [mPowers(1)]

G18 {Gain@Data Flow Models}

MathPow10

FunctionType=Pow10

M4 {Math@Data Flow Models}

MathPow10

FunctionType=Pow10


MathPow10

FunctionType=Pow10


MathPow10

FunctionType=Pow10


MathPow10

FunctionType=Pow10


MathPow10

FunctionType=Pow10


MathPow10

FunctionType=Pow10


MathPow10

FunctionType=Pow10M11 {Math@Data Flow Models}

Gain=2 [mPowers(3)]


Gain=1 [mPowers(2)]


Gain=4 [mPowers(4)]


MathPow10


Gain=31.623 [mPars(1)]


Gain=-72.068 [mPars(2)]


Gain=254.726 [mPars(3)]


Gain=-1107.963 [mPars(4)]


Gain=2956.358 [mPars(5)]


Gain=-4462.485 [mPars(6)]


Gain=3782.968 [mPars(7)]G9 {Gain@Data Flow Models}

Gain=-1653.647 [mPars(8)]


Gain=281.85 [mPars(9)]


A1 {Add@Data Flow Models}

MathPow10


MathPow10

FunctionType=Pow10


MathPow10


MathPow10

FunctionType=Pow10


MathPow10

FunctionType=Pow10


Gain=6 [pPowers(5)]


Gain=4 [pPowers(4)]


Gain=2 [pPowers(3)]


Gain=1 [pPowers(2)]


Gain=0 [pPowers(1)]G28 {Gain@Data Flow Models}

Gain=-1.159 [pPars(1)]G23 {Gain@Data Flow Models}

Gain=0.917 [pPars(2)]


Gain=-1.746 [pPars(3)]


Gain=0.992 [pPars(4)]


Gain=-0.155 [pPars(5)]

G19 {Gain@Data Flow Models} A2 {Add@Data Flow Models}

Gain=14 [mPowers(9)]


Gain=12 [mPowers(8)]


Gain=10 [mPowers(7)]G12 {Gain@Data Flow Models}

Gain=8 [mPowers(6)]


Gain=6 [mPowers(5)]


Mag

Phase

C2 {CxToPolar@Data Flow Models}

MathLog10

FunctionType=Log10M17 {Math@Data Flow Models}

MathLog10

FunctionType=Log10M2 {Math@Data Flow Models}

LimiterType=linear

Top=0.788 [mXmaxVolt]

Bottom=0K=1

L2 {Limit@Data Flow Models}

LimiterType=linear

Top=0.86 [pXmaxVolt]

Bottom=0K=1

L3 {Limit@Data Flow Models}

M1 {Mpy@Data Flow Models}

Gain=1G29 {Gain@Data Flow Models}

Mag

Phase

P1 {PolarToCx@Data Flow Models}

Bus=NO

Data Type=Complex

PA_OUT {DATAPORT}

A3 {Add@Data Flow Models}

10e-201

Value=1e-200

C1 {Const@Data Flow Models}

Bus=NOData Type=Complex

PA_IN {DATAPORT}

DPD_PAModel

PA_IN PA_OUT

DPD_PAModel_1

T

SampleRate=122.9e+6Hz [SamplingRate]S4

Fc

EnvCx

Fc=2GHzC3

DPD_PreDistorterDPD_Input

DPD_Coef

DPD_Output

NumOfInputSamples=61440 [NumOfInputSamples]NonlinearOrder=9MemoryOrder=7

D1

Spectrum Analyz er

SegmentTime=50μs

Start=0sMode=TimeGate

AfterDPD

Fc

CxEnv

E1

Re

Im

R6

Periodic=YESFile='Step3_DPD_Coefficients_Imag.txt

R5

Periodic=YES

File='Step3_DPD_Coefficients_Real.txtR4

T

SampleRate=122.9e+6Hz [SamplingRate]

S1

Fc

EnvCx

Fc=2e+9Hz [FCarrier]

C2

Spectrum Analyz er

SegmentTime=50μsStart=0s

Mode=TimeGateAfterDPD_PA

EVM (dB)

ACLR (dB)


11

LTE DPD simulation for a nonlinear PA with memory

EVM (dB)

ACLR (dB)

DPD_PreDis torterDPD_I nput

DPD_Coef

DPD_O ut put

NumOfInputSamples=61440 [NumOfInputSamples]

NonlinearOrder=9

MemoryOrder=7

D1

Fc

CxEnv

E4

Amplifier

MaxFallTC=16.28e-9s [MaxFallTC]

MaxRiseTC=16.28e-9s [MaxRiseTC]

PdBmMaxMem=10 [PdBmMaxMem]

PdBmNoMem=-30 [PdBmNoMem]

dBc1out=10dBm

GCType=none

NoiseFigure=0

Gain=30 [GaindB]

GainUnit=dB

Amplifier1

T

SampleRate=122.9e+6Hz [SamplingRate]

S1

Fc

EnvCx

Fc=2e+9Hz [FCarrier]

C2

Spectrum Analyzer

SegmentTime=50μs

Start=0s

Mode=TimeGate

AfterDPD_PA

Fc

EnvCx

Fc=0.2e6Hz

C8

Re

Im

R6

Periodic=YES

File='Step3_DPD_Coeffic ients_Imag.txt

R5

Periodic=YES

File='Step3_DPD_Coeffic ients_Real.txt

R4

Fc

CxEnv

E1

Fc

CxEnv

E1 {EnvToCx@Data Flow Models}

M ag

Phase

C3 {CxToPolar@Data Flow Models}

M ag

Phase

P1 {PolarToCx@Data Flow Models}

Fc

EnvCx

Fc=0.2e6Hz

C1 {CxToEnv@Data Flow Models}

Bus=NO

Data Type=Floating Point (Real)

control {DATAPORT}

Bus=NO

Data Type=Envelope Signal

output {DATAPORT}

Bus=NO

Data Type=Envelope Signal

input {DATAPORT}

RiseFallTCv in v out

RefR=50Ω [RefR]

MaxFallTC=100e-6s [MaxFallTC]

MaxRiseTC=10e-6s [MaxRiseTC]

PdBmMaxMem=30 [PdBmMaxMem]

PdBmNoMem=10 [PdBmNoMem]

R1 {RiseFallTC@SV_VC_TC Models}

Amplifier

NoiseFigure=0 [NoiseFigure]

Gain=1

A1 {Amplifier@Data Flow Models}

Amplifier

Gain=1 [Gain]

GainUnit=voltage [GainUnit]

A2 {Amplifier@Data Flow Models}


12

DPD Hardware Verification Flowchart

Create DPD Stimulus

Capture DUT Response

DUT Model Extraction

DPD Response

Verify DPD Response

DPD HW Flowchart consists of 5 steps:

• Step 1 (Create DPD Stimulus) is to download

waveform (LTE or User defined) into

ESG/MXG.

• Step 2 (Capture DUT Response) is to capture

both waveforms before power amplifier and

after power amplifier from PSA/MXA/PXA by

using VSA89600 software.

• Step 3 (DUT Model Extraction) is to extract

PA nonlinear coefficients based on both

captured PA input and PA output waveforms

and then to verify DPD by using PA nonlinear

coefficients.

• Step 4 (DPD Response) is to download the

waveform (LTE or User Defined) after pre-

distorter (by using PA nonlinear coefficient

from Step 3) into ESG/MXG, this real signal

passes through the PA DUT, capture PA

output waveform from PSA/MXA/PXA by

using VSA89600 software.

• Step 5 (Verify DPD Response) is to show the

performance improvement after DPD.


13

DPD Hardware Verification Workspace Structure


14

DPD Hardware Verification Platform

10MHz Reference

10MHz Reference

External Trigger

External Trigger

Attenuator

1. PA input signal capture

2. PA output signal capture

Signal source:

LTE 10MHzAgilent MXG/ESG PSA/MXA/PXA

PSA/MXA/PXAMXG/ESG


15

DPD Hardware Verification – LTE (Step 1)

Step 1: Create Stimulus The CFR must be enable in LTE

source.

LTE paramters (such as bandwidth,

Resource Block allocation and etc)

can be set.

The download waveform transmit

power, length also can be set.


16

Step 2: Capture DUT Response


Firstly, connect the ESG directly

with the PSA/PXA and click the

“Capture Waveform” button in the

“Capture PA Input” panel in the

GUI. The captured signal is the

input of the PA DUT.

Then, connect the ESG with the

DUT, and then connect the DUT

with the PSA/PXA and click the

“Capture Waveform” button in the

“Capture PA Output” panel in the

GUI. The captured signal is the

output of the PA DUT.

These I/Q files are stored for

further usage.


17

Step 3: DUT Model Extraction


This step is to extract

PA nonlinear

coefficient from the

PA input and PA

output waveform and

get the coefficients of

the DPD model.

DPD Verification AM-AM


18


Step 4: DUT Response This step is to apply the DPD model extracted in

Step 3. The generated LTE downlink signal is

firstly pre-distorted by the extracted model, and

then downloaded into the ESG.


19


Spectrum

EVM

ACLR

Step 5: Verify DUT Response

This step is to verify the performances

of the DPD (including spectrums of the

DUT output signal w/ and w/o DPD,

EVM and ACLR).

EVM (dB)

ACLR (dB)


20

EVM (dB)

ACLR (dB)

Hardware Verification Results of Doherty PA


21

References

1. Lei Ding, Zhou G.T., Morgan D.R., Zhengxiang Ma, Kenney J.S., Jaehyeong Kim, Giardina

C.R., “A robust digital baseband predistorter constructed using memory polynomials”,

Communications, IEEE Transactions on, Jan. 2004, Volume: 52, Issue:1, page 159-165.

2. Lei Ding, “Digital Predistortion of Power Amplifiers for Wireless Applications”, PhD Thesis,

March 2004.

3. Roland Sperlich, “Adaptive Power Amplifier Linearization by Digital Pre-Distortion with

Narrowband Feedback using Genetic Algorithms”, PhD Thesis, 2005.

4. Helaoui, M. Boumaiza, S. Ghazel, A. Ghannouchi, F.M., “Power and efficiency

enhancement of 3G multicarrier amplifiers using digital signal processing with experimental

validation”, Microwave Theory and Techniques, IEEE Transactions on, June 2006, Volume:

54, Issue: 4, Part 1, page 1396-1404.

5. H. A.Suraweera, K. R. Panta, M. Feramez and J. Armstrong, “OFDM peak-to-average power

reduction scheme with spectral masking,” Proc. Symp. on Communication Systems,

Networks and Digital Signal Processing, pp.164-167, July 2004.

6. Zhao, Chunming; Baxley, Robert J.; Zhou, G. Tong; Boppana, Deepak; Kenney, J.

Stevenson, “Constrained Clipping for Crest Factor Reduction in Multiple-user OFDM”, Radio

and Wireless Symposium, 2007 IEEE Volume , Issue , 9-11 Jan. 2007 Page(s):341- 344.


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Practical Digital Pre-Distortion Techniques for PA ...LTE DPD simulation for a memoryless nonlinear...

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