Practical Implementation of Flying Capacitor Based Multilevel ...€¦ · I would like to give...

Practical Implementation of Flying Capacitor BasedMultilevel Converters On-Chip and a Practical

Single-Mode Controller with Near Minimum DeviationTransient Response

by

Tom Moiannou

A thesis submitted in conformity with the requirementsfor the degree of Master of Applied Science

The Edward S. Rogers Sr. Department of Electrical and ComputerEngineering

University of Toronto

c© Copyright 2018 by Tom Moiannou

Abstract

Practical Implementation of Flying Capacitor Based Multilevel Converters On-Chip and

a Practical Single-Mode Controller with Near Minimum Deviation Transient Response

Tom Moiannou

Master of Applied Science

The Edward S. Rogers Sr. Department of Electrical and Computer Engineering

University of Toronto

2018

The work presented in this thesis focuses on the practical implementation of techniques

to reduce the volume of the output filter capacitor and inductor. The first area of focus

will be the on-chip implementation of flying-capacitor based multilevel converters, which

have been shown to reduce inductor volume. One such converter, the 7 Switch Flying

Capacitor (7SFC) Buck, is implemented with gate driving on-chip. In doing so, floorplan-

ning and layout strategies for multi-level converters were developed and are described.

As compared to conventional solutions, the volume is reduced while achieving better ef-

ficiency for most operating points. Also presented is a simplified single-mode controller

with near minimum deviation transient response for output capacitor volume reduction.

This controller achieves similar volume reduction as compared to multi-mode solutions

while eliminating dual-mode operation and associated toggling and issues. This con-

troller is demonstrated in a single-phase buck converter based prototype with extensions

to other topologies proposed.

ii

Acknowledgements

I would like to give thanks to my labmates through the past 2 and a half years. Parth,

Maryam, Behzad, Ahsan, Amr, Shadi, Abrar, Mia, Tim, Nenad, Samuel, Yuqing, Jas-

mine, Michael, Gianluca, Ivan, Sandy, and Basil. I have learned a great deal from all of

you and have grown as an engineer and as a person as a result. I’d also like to thank

Zhe for being a patient friend and a helpful colleague. I would also like to thank group

alumnus Aleksandar Radic for the guidance he has provided me with. I’d like to give

special thanks to Lindsey for being both an intellectual and emotional boost. I’d also

like to give special thanks to my colleague Andrija Stupar for his close cooperation and

support. Special thanks are also extended to Mahmoud Shousha and Martin Haug of

Wurth Elektronik for closely supporting my project and providing much needed guid-

ance at critical intervals. I would like to thank Wurth Elektronik generally for financially

backing this work. Lastly I would like to give extra special thanks to my supervisor

professor Aleksandar Prodic who has helped me tremendously during my time here. His

guidance and the laboratory environment he has worked hard to create has enabled me

to grow and become a substantially more effective engineer. I feel the past two years of

my life have been without question the most valuable ones thus far both professionally

and personally and I do not feel I could have grown in this way anywhere else.

iii

Contents

Acknowledgements iii

Table of Contents iv

List of Tables vii

List of Figures viii

List of Abbreviations xiii

1 Introduction 1

1.1 Fundamentals of Switch Mode Power Supplies . . . . . . . . . . . . . . . 2

1.2 Control of SMPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.3 Thesis Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.4 Thesis Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2 Prior Art and Motivation 7

2.1 Topologies for Volume Reduction . . . . . . . . . . . . . . . . . . . . . . 7

2.1.1 Interleaved Buck Converter . . . . . . . . . . . . . . . . . . . . . 7

2.1.2 Three-Level Buck Converter . . . . . . . . . . . . . . . . . . . . . 11

2.1.3 High Step-Down Interleaved Buck Converter . . . . . . . . . . . . 14

2.1.4 7 Switch Flying Capacitor (7SFC) Buck . . . . . . . . . . . . . . 16

2.2 Review of Control Methods . . . . . . . . . . . . . . . . . . . . . . . . . 20

2.2.1 Voltage Mode Control . . . . . . . . . . . . . . . . . . . . . . . . 20

2.3 Fast Transient Controllers . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2.3.1 Time-Optimal Controllers . . . . . . . . . . . . . . . . . . . . . . 20

2.3.2 Minimum Deviation Controllers . . . . . . . . . . . . . . . . . . . 21

iv

3 Integrated Circuit Implementation of Emerging Topologies 23

3.1 Challenges Pertaining to Integration of Modern Topologies . . . . . . . . 25

3.1.1 Losses in Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

3.1.2 Layout Challenges . . . . . . . . . . . . . . . . . . . . . . . . . . 26

3.2 Power stage Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

3.2.1 Total Area Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

3.2.2 Realistic Technology Parameters for Area Selection . . . . . . . . 27

3.2.3 Transistor Sizing . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

3.3 Floorplanning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

3.4 Top Metal Utilization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

3.5 Gate Driving . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

3.5.1 Low Side Gate Driver . . . . . . . . . . . . . . . . . . . . . . . . . 35

3.5.2 High Side Gate Driver . . . . . . . . . . . . . . . . . . . . . . . . 36

3.5.3 Gate Driver Layout . . . . . . . . . . . . . . . . . . . . . . . . . . 40

3.6 Top-Level Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

3.7 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

3.7.1 Switching Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . 43

3.7.2 Conventional Solutions and Passive Volume Comparison . . . . . 45

3.7.3 Efficiency Results and comparison . . . . . . . . . . . . . . . . . . 46

4 Single-Mode controller with Near Minimum Deviation Transient Re-

sponse 50

4.1 Review of Fast Transient Controllers . . . . . . . . . . . . . . . . . . . . 51

4.2 Principle Of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

4.2.1 Analysis of Switching Period Variation . . . . . . . . . . . . . . . 56

4.2.2 Stability for Small Perturbations . . . . . . . . . . . . . . . . . . 57

4.2.3 Extension to Multi-Phase Operation . . . . . . . . . . . . . . . . 58

4.2.4 Extension to Indirect Energy Transfer Converters . . . . . . . . . 59

4.3 Practical Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

4.4 Experimental and Simulation Results . . . . . . . . . . . . . . . . . . . . 62

5 Conclusions and Future Work 66

5.1 Integrated Implementation of Emerging Topologies . . . . . . . . . . . . 66

5.1.1 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

5.2 A Single-Mode Load-Tracking Voltage Mode Controller with Near Mini-

mum Deviation Transient Response . . . . . . . . . . . . . . . . . . . . . 67

5.2.1 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

v

A Bootstrapping Scheme 68

B Additional waveforms for IC 70

C Efficiency Curves 76

D Alternate Level Shifter Topologies 78

vi

List of Tables

3.1 Device Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

3.2 Driver Chain Strength . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

3.3 Level Shifter Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

3.4 Inductor Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

3.5 Other Important Components . . . . . . . . . . . . . . . . . . . . . . . . 43

3.6 Volume Comparison Between 7SFC and Similar Products . . . . . . . . . 45

3.7 PCB Area Comparison Between 7SFC and Similar Products . . . . . . . 46

4.1 Parameters of fast transient prototype . . . . . . . . . . . . . . . . . . . 62

vii

List of Figures

1.1 Taken from IPAD teardown. Shown highlighted in green are passives re-

lated to power management. Shown in blue are silicon devices related to

power management [1]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.2 Schematic of a buck converter in a simple voltage mode control loop . . . 2

1.3 Simplified schematic of linear regulator (LDO), voltage divider formed

between transistor and load, transistor effective resistance adjusted by op-

amp such that load equals reference . . . . . . . . . . . . . . . . . . . . . 3

1.4 Two to one switched-capacitor circuit for step down . . . . . . . . . . . . 4

2.1 Schematic of an interleaved buck converter . . . . . . . . . . . . . . . . . 8

2.2 States for conversion ratios less than 0.5 . . . . . . . . . . . . . . . . . . 8

2.3 Switching waveforms for conversion ratios less than 0.5 . . . . . . . . . . 9

2.4 Interleaved buck converter switching states for conversion ratios greater

than 0.5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.5 Switching waveforms of an interleaved buck converter for conversion ratios

greater than 0.5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.6 Schematic of a 3-Level Buck . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.7 Switching states of a 3-level buck converter . . . . . . . . . . . . . . . . . 13

2.8 Switching waveforms of 3-level buck . . . . . . . . . . . . . . . . . . . . . 13

2.9 Schematic of the High step-down buck . . . . . . . . . . . . . . . . . . . 14

2.10 Switching states of HSD Buck . . . . . . . . . . . . . . . . . . . . . . . . 15

2.11 Switching waveforms of HSD buck converter . . . . . . . . . . . . . . . . 15

2.12 Schematic of the 7SFC. Adapted from schematic in [2] . . . . . . . . . . 17

2.13 Switching states and waveforms for 7sfc as 2-phase buck. Taken from [2] 17

2.14 Switching states and waveforms for the 7sfc operating as a three level buck.

Taken from [2] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.15 Switching states and waveforms for 7sfc as a 2-phase HSD buck. Taken

from [2] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

viii

2.16 Switching waveform of time-optimal transient response showing recovery

of lost charge with one switching action . . . . . . . . . . . . . . . . . . . 21

2.17 Waveforms for minimum deviation style controller correcting inductor cur-

rent within one cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.1 A: Simplified top level schematic of IC developed, containing power-stage

and gate drivers. High side drivers shown for Q1,3,4,5,7, low-side drivers

from Q2,6 B: Schematic of 7SFC showing power transistors only, device

naming for power transistors corresponds to devices shown in A . . . . . 24

3.2 A: Layout of transistor ignoring maximum density rules for active layer.

Only valid for small devices. B) Layout of device considering maximum

density rules for active layer, device broken up into several smaller devices

and spaced apart such that the amount of the active layer in the given

area is smaller than the density limit. Total device width equal to device

shown in A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

3.3 Pie chart showing area of transistors . . . . . . . . . . . . . . . . . . . . 29

3.4 Graph showing peak currents on interconnect between transistors and pads 31

3.5 A: Floorplan, shows the placement of the switches on the die B: Shows

how critical loops may be placed on a PCB . . . . . . . . . . . . . . . . . 32

3.6 Shows the metal thickness of the technology utilized. The top metal layer

is 8x thicker than the low metal layer, and can handle 8x more current. It

is rated for 8 mA/μm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

3.7 A: Shows the area where top metal usage is reserved for specific nets. For

instance, the area colored red is where top metal usage is assigned to the

net labelled IND2. The brown bars indicate where nets pads are connected

using lower metal layers exclusively. B: shows the corresponding color

coded nets in the schematic. . . . . . . . . . . . . . . . . . . . . . . . . . 34

3.8 Block diagram showing schematic of low-side gate driver . . . . . . . . . 35

3.9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

3.10 Showing function of high side driver, when on, output must remain 5 V

above source voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

3.11 Selected level shifter using cross-coupled topology . . . . . . . . . . . . . 39

3.12 Process and temperature simulations for the level-shifter operated for

Vs/VB of 0/5 and 48/53 . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

3.13 Layout of gate driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

3.14 Top Level layout of 7SFC including gate drivers and transistors . . . . . 41

ix

3.15 Switches and gate drivers boxed in using black, pads shown in red . . . . 41

3.16 Photo of chip in package with lid removed . . . . . . . . . . . . . . . . . 42

3.17 Waveforms for 7SFC operating as a HSD Buck, showing inductor currents

and switching node voltages. Inductor currents measured with same offset

to show interleaved nature and equal current sharing. Ch1: Switching

node 1 voltage, 5 V/div. Ch2: Switching node 2 voltage, 5 V/div. Ch3:

Current of L1, 500 mA/div. Ch4: Current of L2, 500 mA/div. The time

scale is 500 ns/div. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

3.18 Waveforms for 7SFC operating as 3-Level Buck, showing inductor currents

and switching node voltage,as inductor waveforms are nearly identical dif-

ferent offset was used to show difference clearly. Ch1: Switching node 1

voltage, 10 V/div. Ch2: Switching node 2 voltage, 10 V/div. Ch3: Cur-

rent of L1, 500 mA/div. Ch4: Current of L2, 500 mA/div. The time scale

is 500 ns/div . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

3.19 Waveforms for 7SFC operating as 2-phase interleaved buck, showing induc-

tor currents and switching node voltages. Ch1: Switching node 1 voltage,

10 V/div. Ch2: Switching node 2 voltage, 10 V/div. Ch3: Current of L1,

500 mA/div. Ch4: Current of L2, 500 mA/div. The time scale is 500 ns/div 45

3.20 Efficiency curves for the 7SFC using 2.2μH inductors in a 1210 package.

Title indicates input and output voltages as well as operating mode (3LB

= 3 Level Buck, HSD = High Step Down Buck). Frequencies indicated in

legend. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

3.21 Efficiency curves for the 7SFC using the 2.2μH inductors in an 0806 LR

package. Title indicates input and output voltages as well as operating

mode (3LB = 3 Level Buck, HSD = High Step Down Buck). Frequencies

indicated in legend. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

4.1 Block diagram of the proposed controller used in a single-phase buck con-

verter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

4.2 Ideal waveforms of the proposed control scheme operating in steady-state.

From top to bottom are the output voltage and nominal output voltage

on the same axis, the inductor current and load current on the same axis,

the capacitor current, the output of the polarity detector, gating signal of

Q1, and gating signal of Q2. . . . . . . . . . . . . . . . . . . . . . . . . . 53

x

4.3 Ideal waveforms of the proposed control scheme operating during a light-

to-heavy load step. From top to bottom are the output voltage and nomi-

nal output voltage on the same axis, the inductor current and load current

on the same axis, the capacitor current, the output of the polarity detector,

gating signal of Q1, and gating signal of Q2 . . . . . . . . . . . . . . . . . 55

4.4 Voltage recovery after load transient for single-mode controller . . . . . . 56

4.5 Showing response of controller in multi-phase case . . . . . . . . . . . . . 58

4.6 Controller modified to be used in a boost converter, note modulator re-

mains same, only difference is capacitor time constant estimator replaced

with 2 sensors and digital potentiometer . . . . . . . . . . . . . . . . . . 59

4.7 Showing waveforms for control scheme applied in boost converter . . . . 59

4.8 Structure of the RC time constant estimator and zero-crossing detection

circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

4.9 Block diagram of half-duty modulator . . . . . . . . . . . . . . . . . . . . 61

4.10 Simulation of controller for 4 A load step, depicting output voltage, in-

ductor current, and load current. . . . . . . . . . . . . . . . . . . . . . . 63

4.11 A: Oscilloscope screenshot showing output capacitor voltage and inductor

current after 4 A light to heavy load step, (ILoad 0.6 to 4.6A). Ch1 vout(t)

, 100 mV/div. Ch2 iL(t), 2 A/div. Timescale is 2 us/div. B: Zoomed out

version of A showing voltage recovery phase, timescale set to 500 us/div.

C: Identical loadstep, except going from heavy to light, D: zoomed out

loadstep shown in C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

4.12 A: Controller responding to consecutive load steps. Ch1 vout(t), 100 mV/div.

Ch2 iL(t), 1 A/div, timescale is 5 μs B: Reference step indicating con-

troller’s stability. Ch1 vout(t), 1 V/div, timescale is 1 ms . . . . . . . . . 64

4.13 A: Depicts a load-step for the control scheme applied to a 2-phase con-

verter. B: Depicts a load-step for the control scheme applied to a Boost

converter, showing the output voltage and scaled inductor current such as

would be seen at the output of the digital potentiometer. . . . . . . . . 65

A.1 The bootstrapping scheme used for power the gate drive circuits in the

designed power stage of the 7SFC . . . . . . . . . . . . . . . . . . . . . . 69

B.1 Showing gate waveforms for Q1 and Q2 as well as the two main switching

nodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

B.2 Switching waveforms for HSD mode of operation, showing gate of switch

4 and 6, as well as switching node 2 . . . . . . . . . . . . . . . . . . . . . 71

xi

B.3 Switching waveforms for HSD, showing gate of switch 3, 1, and vsw1(t) . . 72

B.4 Switching waveforms for HSD, showing gates of switches 7 and 1 as well

as vsw1(t) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

B.5 Switching waveforms for HSD, showing gate of switch 5, 4, and vsw2(t) . . 74

B.6 Switching nodes and low-side gating signals when operating in HSD mode

for 42 V input voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

C.1 Additional efficiency curves using the inductors in the 0806 LR package . 76

C.2 Additional efficiency curves using using the inductors in the 1210 size package 77

D.1 Pulsed SR Latch based level-shifting topology . . . . . . . . . . . . . . . 79

D.2 Simulation showing output swing of pulsed SR latch across process and

temperature corners . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

D.3 Modified level shifter to limit swing to less than 5 V . . . . . . . . . . . . 80

D.4 Simulation showing level shifter perforamance across several corners . . . 81

D.5 Schematic of bootstrapped level shifter . . . . . . . . . . . . . . . . . . . 82

xii

List of AbbreviationsSMPS Switch Mode Power Supply

PID Proportional Integral Derivative

CCP Current Correction Phase

RRP Ripple Reconstruction Phase

IC Integrated Circuit

7SFC 7 Switch Flying Capacitor

HSD High Step Down

3LB 3 Level Buck

IB Interleaved Buck

CCM Continuous Conduction Mode

DCM Discontinuous Conduction Mode

PFM Pulse Frequency Modulation

ESD Electrostatic Discharge

LDO Low Dropout Regulator

PoL Point of Load

CPM Current Programmed Mode Control

PCB Printed Circuit Board

xiii

Chapter 1

Introduction

Switch-Mode power supplies are virtually ubiquitous in modern consumer electronics.

DC-DC power supplies are used to regulate the electric power supplied to one or more

functional blocks. These supplies consume large amounts of PCB area and contribute

substantially to the total volume of many modern electronic devices. This can be seen

in Fig 1.1, using the results of an Ipad teardown taken from [1].

Figure 1.1: Taken from IPAD teardown. Shown highlighted in green are passives relatedto power management. Shown in blue are silicon devices related to power management[1].

Semiconductor portions of the power supplies are shaded in blue. Passives related to

power management are shaded in green. As can be seen, these components, particularly

the passives, consume large amounts of area. Emerging technologies present opportunities

to reduce the volume of such passive components. This includes new topologies to reduce

inductor volume and control schemes to reduce output filter capacitor volume. Doing so

creates room to add or improve other features on such devices, or otherwise permits the

shrinking of electronic devices altogether.

1

Chapter 1. Introduction 2

1.1 Fundamentals of Switch Mode Power Supplies

Switch-mode power supplies are popular choices for converting power from one form to

another. They consist of three basic components. A switching network, an output filter,

and a controller. Fig 1.2 depicts a buck converter in a voltage mode control loop as an

example. The switching network modulates the input of the filter, passing it rectangular

pulses equal to Vg and ground, of durations DTs and (1-D)Ts respectively. Where Ts

is the switching period and D the duty cycle. The output filter functions as a low pass

filter, causing the average value of the voltage to appear at the output. This value is

equal to VgDTs.

Figure 1.2: Schematic of a buck converter in a simple voltage mode control loop

The output filter components shown in Fig. 1.2 correspond to the passives shown

in Fig. 1.1, which were highlighted in green. The semiconductor portions of the buck

(i.e. the two transistors) are included the semiconductor portions of Fig. 1.1. Most

of the semiconductor portions of Fig. 1.1 are in the form of power management inte-

grated circuits, or PMICs. These integrate both transistors, as well as ancillary circuitry

such as gate drivers and control circuits into a single package. This reduces the volume

overhead associated with separately packaged transistors and is frequently done to im-

prove performance and avoid wasting space, and is very desirable in volume sensitive

applications.

Switch-mode power supplies compete with two existing technologies in the area of DC-

DC conversion. One example is the linear regulator which is shown in Fig. 1.3. Linear

regulators place a variable resistor (often realized as a MOSFET) in series with the load.


The resistance is varied such that the divider formed between it and the load provide

the load with the desired voltage. Unlike switch-mode power supplies this approach may

only be used to step-down a voltage, not step up one. Furthermore it is intrinsically

lossy, as all of the excess energy is burnt off resistively as opposed to being stored. Its

theoretical maximum efficiency is equal to the load voltage divided by the input voltage

[3]. Hence such regulators have been largely replaced by switch-mode power supplies in

most applications as these can theoretically achieve 100% efficiency for any conversion

ratio. Although, LDOs are still popular for low-step down (conversion ratios close to 1)

and low-power applications. They are also popular when extremely tight regulation of

the output voltage is required and/or very little supply noise can be tolerated. In such

cases they are often used downstream of an SMPS.

Figure 1.3: Simplified schematic of linear regulator (LDO), voltage divider formed be-tween transistor and load, transistor effective resistance adjusted by op-amp such thatload equals reference

SMPS also compete with switched-capacitor circuits which can multiply or divide a

voltage by a fixed amount. The schematic of a two to one step down switched capaictor

circuit is depicted in Fig. 1.4. Like SMPS, these can theoretically acheive very high

efficiencies [4]. Unlike SMPS however, they have difficulty providing tight regulation.

These circuits work by multiplying or dividing the input by a fixed number. Control

techniques can be applied to adjust the output, but this degrades efficiency considerably

[4]. Hence these converters are best suited for applications where the input is fixed or

very tight regulation of the output is not required.


Figure 1.4: Two to one switched-capacitor circuit for step down

The size of the components in power supplies is determined by a number of factors.

The size of the inductor is determined by both efficiency and EMI specifications, as

larger inductance values lead to reduced ripple and thus lower rms current (losses) and

less electromagnetic interference. The size of the output capacitors may be determined

by either the steady-state ripple or the transient response of the converter. In cases where

load transients are a concern, this is usually the dominant factor.

Emerging technologies present an opportunity to reduce the volume of switch-mode

power supplies. New topologies for power conversion permit reduced passive volume,

particularly that of the output filter inductors. Advanced control schemes offer the

ability to reduce the size of the output capacitors by improving the transient response of

converters, such that regulation requirements may be met using smaller capacitors.

1.2 Control of SMPS

Traditionally, switch-mode power supplies are controlled using a linear control scheme,

such as voltage-mode control. A block diagram for this control scheme was shown in

figure 1.2. The converter is placed in a loop. A reference voltage is provided to the error

generator, which compares it to the output voltage and generates an error signal. The

error is supplied to the linear compensator, typically a PI or PID. The compensator then

adjusts the duty cycle command, which is used to generate the appropriate pulse-width


modulated gating signals to control the output voltage.

This controller may be implemented in either an analog or mixed-signal manner. It

is increasingly popular to use digital compensators as they require less silicon area to im-

plement in modern technology, while also permitting more aggressive control techniques

(such as tuning coefficients based on operating conditions).

Control schemes such as the one described have less than ideal transient performance.

New control schemes which do not rely solely on linear compensators have been proposed

to achieve a more aggressive transient response. Such technologies include minimum de-

viation and time-optimal controllers. Minimum-deviation and time-optimal controllers

generally use dual-mode operation, having one mode for steady-state and one for load-

transients. This can lead to issues where repeated toggling occurs between modes de-

grading performance. These controllers will be discussed in greater detail in chapter

2.

1.3 Thesis Objectives

This thesis will discuss the practical implementation of emerging volume-reduction tech-

niques for switch-mode power supplies. Shown first will be the on-chip implementation

of a recently developed topology, the Seven Switch Flying Capacitor Buck, which is ca-

pable of reducing volume for comparable efficiency. This converter belongs to a class

of converters known as multi-level flying capacitor converters. As will be discussed in

chapter two, these converters show great promise for reducing inductor volume, but have

rarely been integrated on-chip. Integration of such converters is necessary for their wider

adoption in volume sensitive applications. There are many challenges to integrating such

converters which must be addressed. One of the main aims of this thesis is to address

these challenges. Some key objectives of this aspect of the thesis are listed below.

1. Discuss the sizing of devices in emerging topologies

2. Formulate and provide practical guidelines for the floorplanning and metal routing

of modern step-down topologies of high complexity

3. Show the suitability of low-power gate drive circuits

4. Demonstrate reduced volume for comparable efficiency when compared to IC mod-

ules employing the conventional buck converter


This thesis will also aim to address one of the main limitations associated with min-

imum deviation style controllers, that is, dual-mode operation. Proposed in this thesis

is a single-mode controller that offers near minimum deviation transient response. This

eliminates the risk of toggling issues and the instability that can result. This aspect of

the thesis will aim to do the following.

1. Describe algorithm for single-mode controller with near minimum deviation tran-

sient response

2. Demonstrate implementation of controller in a single-phase buck converter based

prototype

3. Propose extension to additional converter topologies

1.4 Thesis Overview

Chapter 2 will review prior art and technologies. First topological innovations will be

discussed. This will focus on “multilevel” converters, which enable a reduction in inductor

volume by reducing the voltage swing at the switching node of a SMPS. Afterwards, fast

transient control schemes which permit a reduction in the output capacitor volume will

be discussed.

Chapter 3 will look at the on-chip implementation of a multilevel converter. The

process will be explored in detail and efficiency results including comparison to existing

conventional products will be done. The design and layout of the power stage and gate

drivers will be discussed. Efficiency results measured from the fabricated chip will be

presented and discussed.

Chapter 4 will look at a new, practical, single-mode near minimum deviation control

scheme. Its implementation will be discussed, and experimental results for a buck con-

verter based prototype will be presented. The extension of this control scheme to other

topologies will also be discussed and simulation results will be presented.

Chapter 5 will present conclusions and discuss future work.

Chapter 2

Prior Art and Motivation

Many technologies have been developed for the purpose of reducing volume in switch-

mode power supplies. In this chapter, topological and control techniques will be reviewed.

2.1 Topologies for Volume Reduction

2.1.1 Interleaved Buck Converter

Numerous topologies have been devised to reduce the size of passive elements in switching

converters. One such group of topologies are phase-interleaved converters [5]. This

technique works by essentially splitting the switching network and inductor into several

parallel stages. The stages are operated out of phase such that they are charging and

discharging at different times. This reduces the amplitude of the output capacitor current,

thus reducing the converter’s ripple. This can reduce the output capacitor volume [6], [7].

This technique can also reduce the volume of the input filter by reducing the amplitude

of the current pulses drawn from this branch [6], [7]. Furthermore, the net reduction

in current ripple at both the input and the output results in lower RMS currents and

can lead to an improvement in efficiency [6], [7]. Lastly, phase interleaving can better

distribute losses in a converter and reduce local heating.

A 2-phase interleaved buck is shown in Fig 2.1. This converter can follow two different

sets of switching states. One set of switching states allows for conversion ratios less than

0.5, the other is for conversion ratios above it. For conversion ratios less than 0.5,

switching states are shown in 2.2 and switching waveforms are shown in Fig 2.3. For

greater than 0.5, the states and waveforms are shown in Figs 2.4 and 2.5 respectively.

7

Chapter 2. Prior Art and Motivation 8

Figure 2.1: Schematic of an interleaved buck converter

Figure 2.2: States for conversion ratios less than 0.5


Figure 2.3: Switching waveforms for conversion ratios less than 0.5


Figure 2.4: Interleaved buck converter switching states for conversion ratios greater than0.5

Figure 2.5: Switching waveforms of an interleaved buck converter for conversion ratiosgreater than 0.5

A single switching cycle consists of 4 states. For conversion ratios less than 0.5, when

in its first state, switches 1 and 4 are on, the others are off. Inductor L1 is charging up,


L2 is discharging. Upon entering its second state, switches 2 and 4 are on, both inductors

are discharging. Upon entering its third state, switches 2 and 3 are on, and inductor L2

is charging up. Its fourth state is a repeat of state 2.For conversion ratios greater than

0.5, states 1 and 3 have both inductors charging, states 2 and 4 set inductors L1 and L2

into rectification respectively.

2.1.2 Three-Level Buck Converter

Another technique which has emerged in the past 2 decades and is beginning to see

broader adoption is the usage of flying capacitor based multilevel converters. These

converters use one or more flying capacitors to reduce the voltage swing at the various

switching nodes. Hence the inductor volume can be reduced considerably while main-

taining the same inductor ripple frequency and peak current [8].

The schematic of a three-level buck is shown in Fig 2.6 [9]. It functions similarly to

a conventional buck converter. However, there are two additional switches and a flying

capacitor. The flying capacitor voltage is typically about one-half the input voltage,

although it may deviate from this value in the absence of a controller to keep it there.

Depending on start-up conditions, this converter may be implemented with switches rated

for one half of the input voltage, which consume substantially less area than switches

rated for the full input voltage. This can be better explained by looking at the Figure

of Merit (FOM) of the transistor. The most commonly used FOM is the product of its

on-resistance and gate charge, RDSON · QG. Typically, the FOM of transistor is related

to VDS in the following manner, FOM = αV 2DS, where α is a constant of proportionality

[8]. Hence, halving the voltage rating improves the FOM by a factor of 4. As a result,

it is theoretically possible to implement multilevel converters with no increase in silicon

area [8].


Figure 2.6: Schematic of a 3-Level Buck

The switching states of this converter are shown in Fig 2.7. Corresponding switching

waveforms for this converter are shown in Fig 2.8. During the first portion of the cycle

switches 1 and 3 are on, switches 2 and 4 are off. The input voltage is passed through the

flying capacitor to the output filter. As the flying capacitor voltage is equal to half the

input voltage the switching node sees the input voltage minus half of its value. During

phase 2, switch 4 is on, and all other switches are off, the switching need is zero. During

phase three, switches 2 and 4 are on. The flying capacitor voltage is passed to the output

filter. Phase four is identical to phase 2.


Figure 2.7: Switching states of a 3-level buck converter

Figure 2.8: Switching waveforms of 3-level buck

The conversion ratio of this converter is equal to DTs, where Ts is the period of time

it takes for all four phases to complete. DTs is equal to the duration of phases 1 and

3 individually (i.e. the sum of the 2 is 2DTs). As compared to a conventional buck


converter operating with an equal Ts, the inductor current ripple is half the value. This

allows one to use smaller inductors with all other things being kept constant.

2.1.3 High Step-Down Interleaved Buck Converter

Another multilevel flying capacitor based topology is the High Step-Down Interleaved

Buck Converter [10]. A schematic of this converter is shown in figure 2.9. Like the

3-level buck converter, this topology uses a flying capacitor whose voltage is equal to

that of one half the input voltage. This topology has several advantages over the 3-

level buck. First and foremost, as a multiphase converter, it will see reduced output

capacitor voltage ripple. As the inductance requirements are otherwise equal this does

not impact overall inductor volume, as its output filter is two inductors each rated for

half the current. Unlike the 3-level buck converter, the flying capacitor voltage does not

deviate significantly from half of the input voltage. This is because Inductor Volt-Second

Balance (IVSB) may only be satisfied in each inductor if the voltage is exactly half of the

input voltage (in the absence of losses). If the losses along each path of this converter are

not equivalent, a small voltage imbalance in the flying capacitor will appear to correct

them. However this is typically just a few percent of its nominal value. The switching

states of this converter are provided in Fig. 2.10 and switching waveforms in Fig. 2.11.

Figure 2.9: Schematic of the High step-down buck


Figure 2.10: Switching states of HSD Buck

Figure 2.11: Switching waveforms of HSD buck converter

This converter has a conversion ratio of D/2. Where D is defined as the of the

duration of phase 1 (which is equal to that of phase 3) divided by the switching period


Ts. This ties into yet another benefit of the double step-down buck converter. It has duty

cycle extension, which makes it useful for high-step down. As its duty cycle is longer,

it relaxes switching speed requirements for very high conversion ratios M(D) < 0.1. If

digital control is used, this also reduces requirements on the resolution of the DPWM.

This converter also has benefits over the conventional interleaved buck converter. As

each phase must have equal current in order for the flying capacitor voltage to settle to

half the input voltage, the inductor currents in each phase balance inherently. Whereas

there is nothing in a conventional interleaved converter that forces the currents in each

phase to match each other.

This converter does however have drawbacks when compared to the 3-level buck.

The inductor current ripple will be twice that of the 3-level buck for the same conversion

ratio. It also requires switch two be rated for the full input voltage regardless of the

startup condition. As its conversion ratio is D/2, and its maximum duty cycle is 0.5, it

is incapable of achieving conversion ratios greater than 0.25. which makes it unsuitable

for applications requiring wide output range or low conversion ratios (M(D) > 0.25).

2.1.4 7 Switch Flying Capacitor (7SFC) Buck

The 7SFC is a flying capacitor based topology that can be configured to operate as any

of the previously presented topologies [11]. A schematic of it is shown in Fig. 2.12. All

switches in it may be rated for half the input voltage. It selects its operating mode based

on the conversion ratio required. It typically operates as a 3-level buck, a high step-down

buck or a interleaved buck converter. This allows it to harness the powerful benefits of

the high step down topology while still being able to achieve wide-range operation.

When operating as a three-level buck, both inductors are ran in parallel and treated

like a single inductor. When operating as a double step down or interleaved buck it

operates just as those converters do as described above. One caveat is that if it is imple-

mented using half-rated switches it may only use the interleaved buck mode if operated

for an input voltage less than one half of its fully rated input voltage. When operating

as the three aforementioned converters the switching nodes and inductor currents will

behave as described for those converters. Switching states and waveforms for the three

different modes are provided in Figs. 2.13, 2.14, and 2.15.


Figure 2.12: Schematic of the 7SFC. Adapted from schematic in [2]

Figure 2.13: Switching states and waveforms for 7sfc as 2-phase buck. Taken from [2]


Figure 2.14: Switching states and waveforms for the 7sfc operating as a three level buck.Taken from [2]


Figure 2.15: Switching states and waveforms for 7sfc as a 2-phase HSD buck. Taken from[2]


2.2 Review of Control Methods

Numerous control methods have been developed to regulate the output voltage of SMPS

controllers and improve their load-transient response. This includes, steady-state con-

trollers, like voltage mode controllers, and fast transient controllers, like time-optimal

and minimum deviation style controllers. These will be discussed in this section.

2.2.1 Voltage Mode Control

A block diagram for a voltage mode controller was shown in Fig. 1.2. In essence a voltage

mode controller reads the output voltage and adjusts the duty cycle until it reaches the

desired value. It is the simplest control scheme typically used for power converters and is

highly flexible and easy to implement. However, voltage mode controllers cannot provide

the best transient response.

2.3 Fast Transient Controllers

In recent years, numerous fast load-transient response controllers have been proposed.

Examples include time-optimal [12],[13],[14],[15],[16] and minimum deviation controllers

[17],[18],[19]. For direct energy transfer converters, such as a buck converter, the usage of

such controllers results in what is practically the minimum achievable voltage deviation

for a given converter and load-step [11]. This presents the opportunity to drastically

reduce the output capacitor volume. Still, the presented approaches suffer from a few

drawbacks that have slowed down their wider adoption in particular targeted applications.

2.3.1 Time-Optimal Controllers

Time-optimal controllers are fast transient controllers that aim to recover lost output

voltage in the minimum amount of time possible. Fig. 2.16 shows the waveforms during a

transient. Normally, the converter operates using a linear control scheme, such as voltage

mode control. When a load transient is detected, the inductor current begins charging

up until the output voltage ceases to drop. Once this happens, a peak inductor current

value is calculated such that the lost voltage is recovered. This is done by determining

a peak value such that charge Q2 is equal to charge Q1. This means that the charge

deposited back into the capacitor by the increased inductor current is equal to that lost

during the transient. This returns the output voltage to its nominal value. The controller

then resumes normal operation.


Figure 2.16: Switching waveform of time-optimal transient response showing recovery oflost charge with one switching action

This control scheme provides the fastest possible transient response but suffers from

several problems. First off, it is computationally intensive, calculating the peak current

requires large amounts of digital circuitry. It also requires power hungry high speed

ADCs which consume substantial amounts of power and silicon area. Thirdly, it requires

the inductor used be rated according to the peak current the controller requires. Next,

it has difficulty responding to successive transients, which can lead to toggling between

its transient response and steady state control modes [20]. Losses and non-ideal effects

in real converters can also result in errors in its transient response and lead to toggling

problems [20]. Lastly it requires knowledge of converter to parameters to work properly

limiting its utility and making it susceptible to variations in these parameters [20].

2.3.2 Minimum Deviation Controllers

Minimum deviation controllers address many of the issues with time-optimal controllers

at the cost of a slower voltage recovery time. These controllers focus on correcting the

inductor current as quickly as possible during a load transient such that it matches

the load. Ideal waveforms for this control scheme are shown in 2.17. In the event of

a load transient, a minimum deviation controller simply forces the inductor current to


match that of the load. This avoids some of the issues of time-optimal converters. As

no calculations are required, the digital hardware requirements are eliminated. As the

inductor current is not ramped past the desired steady-state value, the inductor need only

be sized as per its steady state requirements. There is also no need to sense the inductor

current digitally, eliminating a high-cost ADC from the equation. This controller gives

the minimum achievable voltage deviation possible for a given load transient.

Figure 2.17: Waveforms for minimum deviation style controller correcting inductor cur-rent within one cycle

Chapter 3

Integrated Circuit Implementation

of Emerging Topologies

Emerging topologies have rarely been implemented on-chip. This thesis will show the

implementation of the 7SFC into a on-chip power module with integrated gate drivers.

In addition to conventional topics like gate driving, challenges that are unique to more

complex topologies will be discussed. One example is device sizing. As the converter

operates in many different modes, the manner in which silicon area need be assigned

is a more complicated topic than it is in other converters. Another challenge is floor-

planning. As many conduction paths exist, and different modes will see different paths

conducting large amounts of current, special care must be taken to optimize the arrange-

ment of devices. This is necessary to minimize the contribution of metallization to the

on-resistance of the devices, which as will be shown is a significant contributor, and to

meet electromigration requirements.

The power stage is designed as a wide-input, step-down, point-of-load module, which

must be able to interface with input BUS voltages ranging from 5V - 42V, outputting

voltages from 0.8 V to 12 V (but not exceeding the input voltage of the converter). The

maximum output current of this design is to be 2 A. A block diagram of the IC developed

is provided in Fig. 3.1, the functional blocks of this chip will be discussed in the sections

below. This operating range is desirable for consumers seeking a single product to deliver

power to a variety of loads from different bus voltages. Products with similar operating

ranges are compared to the implemented converter.

23

Chapter 3. IC Implementation of Emerging Topologies 24

Figure 3.1: A: Simplified top level schematic of IC developed, containing power-stageand gate drivers. High side drivers shown for Q1,3,4,5,7, low-side drivers from Q2,6 B:Schematic of 7SFC showing power transistors only, device naming for power transistorscorresponds to devices shown in A


3.1 Challenges Pertaining to Integration of Modern

Topologies

There are many challenges that are intrinsic to the on-chip implementation of SMPS that

are exacerbated by the complexity of modern emerging topologies. One major goal of

this thesis is to address how to approach these challenges.

3.1.1 Losses in Devices

In a conventional buck converter, there are two transistors, a high-side, and a low-side

device. For conversion ratios closer to 1, the high-side device will conduct the majority

of the current. For conversion ratios closer to zero, the low-side device will conduct the

majority of the current. This is shown using the following expressions [21].

PHS =

√D · (I2OUT +

I2Ripple

12) ·RDSON (3.1)

PLS =

√(1 −D) · (I2OUT +

I2Ripple

12) ·RDSON (3.2)

Where PHS and PLS are the conduction losses of the high and low side devices respec-

tively. Hence the losses in each switch is strictly related to the duty cycle and thus the

conversion ratio. This is not true for the 7SFC. For instance Q7 will nominally conduct no

current in the HSD mode of operation for all conversion ratios. However, when operating

as a 3-Level Buck or as an interleaved buck, will experience current stresses similar to a

high-side switch in a conventional buck converter. Conduction losses in Q2 and Q3 are

directly proportional to 1-D in the interleaved buck mode of operation, but proportional

to Ts/2 + (1-D) in the 3-level buck and HSD modes of operation. This complicates the

sizing of these devices. The conduction losses of Q3 are shown in equations 3.3 and 3.4

for the interleaved buck and high-step down modes respectively.

PCOND Q3 IB =

√(1 −D) · ((0.5 · IOUT )2 +

I2Ripple

12) ·RDSON

(3.3)


PCOND Q3 HSD =

√(D) · ((0.5 · IOUT )2 +

I2Ripple

12) ·RDSON

+2 ·

√(1 −D) · ((0.5 · IOUT )2 +

I2Ripple

12) ·RDSON

(3.4)

This problem is further complicated by gate-drive losses and Coss losses. As some

devices switch in some modes and not others, and Q6 will switch at twice the nominal

switching frequency in the 3-level buck mod of operation.

3.1.2 Layout Challenges

Related to the number of devices and different current stresses is the interconnect between

devices and pads. Unlike an on-chip buck converter, which contains two transistors,

interfacing to 3 power related external connections (input voltage, output filter, and

ground),the 7SFC, contains 7 devices, which interface with 7 external connections (two

separate ground ports, the input voltage, one port per inductor, and one port connecting

to either side of the flying-capacitor. Making matters worse there is the electromigration

phenomenon. Electromigration is a long-term failure mechanism which can lead to open

circuits forming on metal pathways due to the tendency of metal to “migrate” in the

direction of current flow [22]. There are maximum current density specifications which

need to be satisfied to ensure this does not happen within the devices expected lifetime

[22]. This is particularly challenging in the 7SFC due to the many current paths leading

to and from most devices, many of which experience high current in one mode but not

others. One example of this is the connection between Q1 and Q4. In the HSD and 3-

Level Buck modes of operation this path conducts no current. However in the interleaved

buck mode of operation this pathway can conduct up to the full-load current.

Another important thing to consider is the layout of the printed circuit board which

the IC will be soldered to. One important thing about this is minimizing the length and

loop area of the switching node loops. This is important to minimize parasitic inductance

and EMI related problems [23]. If possible the IC should be laid out in such a way that

the power path all be done on one layer so that inductance not be added by using vias

to jump layers [23].


3.2 Power stage Design

3.2.1 Total Area Usage

The area required for the converter is based on that used by similar products. This figure

was provided to us by Wurth Elektronik who was sponsoring the project, and was set to

5mm2.

3.2.2 Realistic Technology Parameters for Area Selection

There are several parameters which are useful when sizing power transistors. These

parameters are listed as follows.

1. Rsp - The specific on-resistance of a given technology, that is the on-resistance of a

1mm2 transistor made in this techonology, given in mΩ·mm2

2. Coss density - the drain to source capacitance density of the technology used (pF/mm2)

3. Cin density - the gate to source capacitance density of the technology (pF/mm2)

The foundry provides nominal values for these parameters, however this number is not

very accurate as it does not take into account layout considerations. The figure provided

does not take into account layer density rules which limit the amount of active transistor

area that can be placed in a given area. Hence it is only accurate for very small devices.

This can be understood by looking at Fig 3.2


Figure 3.2: A: Layout of transistor ignoring maximum density rules for active layer.Only valid for small devices. B) Layout of device considering maximum density rules foractive layer, device broken up into several smaller devices and spaced apart such thatthe amount of the active layer in the given area is smaller than the density limit. Totaldevice width equal to device shown in A.

In order to accurately estimate area, a device should be laid out according to its

maximum density rules, and its resistance extracted. This produces a better estimate for

the specific on resistance. In this case it was found that the value was about 20% higher

than the one provided by the foundry.

The input capacitance and output capacitance of the transistor are extracted as well.

These are used to determine Coss density and Cin density. These three parameters can be

used to determine conduction losses, switching losses, and gate drive losses.

3.2.3 Transistor Sizing

The sizing of each transistor was determined using a convex optimization procedure as

described in [2]. A summary of this process is described below.

A fixed area amount of 3.5 mm2 was used. This area was based on the amount of area

which would be available after other components including esd protection, the padframe,

and the gate drivers were included.

The script initially sizes each device equally. The script than optimizes efficiency for

a single operating point while also ensuring the efficiency remains above certain other


targets for other operating points. The parameters extracted previously are used to

determine conduction losses, Coss losses and gate drive losses.

It iteratively runs simulations for that point and adjusts device sizings until the

solution converges on the optimal distribution of silicon area for that operating point.

As the converter is targeted for wide input and output range operating conditions, several

points of optimization were selected, and simulations were run in Cadence to determine

which was the most desirable across all operating points. The design ultimately selected

was the one optimized for the 24 V to 5 V operating point as this was able to produce

satisfactorily high efficiencies for high-step down while still performing well for conversion

ratios closer to one. A simplified testbench to accurately capture the losses while being

relatively quick to run was constructed. As this testbench simulates real devices, the

technology parameters are automatically modeled. This includes conduction, switching,

Coss losses, and gate drive losses. The DC resistance of the inductor is taken from

the datasheet. As no SPICE model was available for the selected inductor, a simple

ripple-dependent model was used by taking core loss values from Wurth Elektronik’s

REDEXPERT tool for different ripple values and fitting them to a curve. These losses

were then included in the efficiency measurement. The final device sizes are shown in

3.3. Parameters for the seven transistors are provided in table 3.1. Both pre-layout and

post-layout parameters are included. The post-layout resistance includes the resistance

added by the metal to route to the next device. As can be seen this can increase the

resistance of some devices by up to 25%.

Figure 3.3: Pie chart showing area of transistors


Table 3.1: Device Parameters

Pre-Layout Post-LayoutRon (mΩ) Cin (pF) Coss (pF) Ron (mΩ) Cin (pF) Coss (pF)

Q1 79.8 292 141 95.7 327 165Q2 55.9 417 174 75.85 468 229Q3 51.44 452 188 67.5 512 251Q4 80.6 289 120 99.6 324 159Q5 76.6 303 127 101.6 344 128Q6 78.8 295 125 91.1 330 165Q7 104.3 224 92 131 250.5 125

3.3 Floorplanning

An integrated power stage will have numerous connections both between silicon devices

on-chip and between these devices and external components. The complexity of the

topology requires that special attention be paid to its floorplan. Failing to floorplan

properly can result in increased routing resistance and poorer efficiencies. In this section,

a strategy for proper floorplanning of integrated power stages will be described. The

following principles were developed to describe what a suitable floorplan would look like

and how to achieve it.

1. Place devices in locations which are pad accessible,

2. Arrange devices to minimize routing resistance and inductance between devices,

3. Permit peak current requirements be met from an electromigration perspective,

4. Whenever possible, arrange devices in such a manner which simplifies the layout of

the PCB both in terms of the power stage and connecting passive elements.

In order to create a good floorplan, it is important to consider the highest average

currents in all branches. In Fig. 3.4 the highest average currents are shown in graph

form. The vertices of the graph being pads and switches, and the edges connecting them

being conduction paths. Using this figure a desirable floorplan becomes clearer. Devices

should be arranged in such a way that they can conduct high current to both related

devices and pads. The following principles were developed to migrate from this graph to

a proper floorplan.


Figure 3.4: Graph showing peak currents on interconnect between transistors and pads

1. Devices should share their perimeters with switches and pads they connect to,

2. Devices which have high current paths to the same pads should be both adjacent

and share an edge of the die. This ensures both devices have access to the pads, re-

duces the number of pads requires and helps reduce losses by sharing metal between

the two devices,

3. The shared perimeter of devices which conduct current with each other, as well as

that between pads and devices conducting with them, should be maximized.

In accordance with the principles above, it becomes clear that all devices must share

their perimeters with the pad-ring as all have high-current paths to one or more pads.

Furthermore, to maximize efficiency and simplify the floorplan as much as possible, de-

vices which conduct high-current to multiple separate pads are placed at the corners of

the die. This means two edges of each of these devices have contact with the padframe,

maximizing the space which can be used to route out to the padframe.


From this point there are several distinct floorplans which could be used. The one

shown in Fig. 3.5 was selected as it seemed to be the best fit out of the possible options

from a PCB-layout perspective. It allows both inductors to be placed adjacent to one

side of the chip simplifying the path to the output, and preserves small current loops for

the input and flying capacitors. It also offered reduced metal resistance for Q5 and Q7

as it allowed them to share metallization. In addition to this the pads connecting to the

inductors, flying capacitors, and input voltage capacitors are all on different edges of the

chip, preventing the crossing of high current paths, simplifying the PCB layout. This

also permits the various switching nodes and high didt

loops in the main power path, to

be placed on a single-layer of the PCB as shown in Fig. 3.5b. This is beneficial as it is

important to minimize the loop inductance of these paths, and generally ill-advised to

via to multiple layers.

Figure 3.5: A: Floorplan, shows the placement of the switches on the die B: Shows howcritical loops may be placed on a PCB


3.4 Top Metal Utilization

In the available technology six metal layers were used. The top metal layer has very high

current carrying capacity, exceeding that of all other layers combined, as such it should

be distributed with special attention. This is illustrated in Fig. 3.6. Fig. 3.7 shows the

distribution of the top metal layer in the layout. The colors on the figure represent which

net corresponds to which on the schematic. It is also important to remember the metal

is not placed as one sheet covering the entire indicated area. The indicated areas simply

show which net the usage of the top metal is reserved for in a given area.

Figure 3.6: Shows the metal thickness of the technology utilized. The top metal layer is8x thicker than the low metal layer, and can handle 8x more current. It is rated for 8mA/μm

Due to the complex nature of the topology the lower metal layers are also utilized

extensively. They are most frequently utilized to distribute current laterally across an

individual device, but are sometimes also used to conduct current to other devices when

it is too problematic to do so using the top metal layers. The brown bars in 3.7 indicate

where lower metal layers are used to route between devices (or between devices and pads).

This was done between Q6 and ground, Q2 and ground, and between Q4 and both Q5/7.


Figure 3.7: A: Shows the area where top metal usage is reserved for specific nets. Forinstance, the area colored red is where top metal usage is assigned to the net labelledIND2. The brown bars indicate where nets pads are connected using lower metal layersexclusively. B: shows the corresponding color coded nets in the schematic.

For most devices, top metal is reserved for the drain at the input of the device and for

the source at the output of the device. The proportion for each gradually shifts from the

drain to the source as the device moves from its input to its output. Lower metals are

used to pass current in cases where the shared perimeter is very broad, and the direction

of current flow makes it inconvenient to share the top metal between the drain and the


source.

3.5 Gate Driving

3.5.1 Low Side Gate Driver

The low side gate driver, pictured in Fig. 3.8 consists of a low-voltage (0-5V) level

shifter and an inverter chain. On chip the high current power ground and low current

signal ground are completely separated. Signals which come on chip are referenced to

the signal ground. As there may be a small dc offset between the signal ground and the

power ground a level shifter is needed to ensure safe translation, a standard CMOS level

shifter is used for this purpose.

Figure 3.8: Block diagram showing schematic of low-side gate driver

The driver chain consists of a series of CMOS buffers using a fanout of four. A fanout

of four was used as this is the commonly quoted optimal number to minimize delay

[22]. The sizing of the gate driver has several consequences. A gate driver that is too

weak increases switching losses by reducing the switching time of the power transistor.

However, oversizing the gate driver has several drawbacks as well.

1. Greater area consumption,

2. Can cause EMI related problems and worsen ringing,

3. High current spikes can increase the risk of latch-up.

Thus, depending on area constraints, it is desirable to make the gate-driver just slightly

stronger than it needs to be. This is because the strength of the driver can easily be re-

duced after the fact by adding a supply/bootstrap resistor to limit the maximum amount

of current which can be pulled into the driver. Table 3.2 shows losses for different gate-

source rise times, for a high-side switch operating for a 24 V input voltage and 2 A

load current. As can be seen, for the selected frequency, the losses cease to increase


significantly for rise times of less than 13 nanoseconds, hence a rise time less than this

value is desirable. Some margin is provided to account for increases in resistance due

to parasitics, so the inverter chain was designed for a 10%-90% rise time of 10ns, for

the largest device on the chip Q3. Doing so also allows the frequency the prototype’s

switching frequency to be increased if desired without incurring unduly high switching

losses.

Table 3.2: Driver Chain Strength

Rise time (ns) SWloss (mW)

42 6636 63.130 60.520 5713 53.456 52.89

3.5.2 High Side Gate Driver

The high side gate driver is more sophisticated than the low-side one. High-side gate

drivers are used to drive so called high-side devices. These are used to drive NMOS

devices whose source nodes are not necessarily tied to ground. The challenges of this

can best be explained referring to Fig. 3.9 This figure shows a simple half-bridge. For

the technology the transistors are made out of, the maximum permissible gate-source

voltage is 5 V. This can be understood by looking at a buck converter for the case when

the converter is transitioning from the state where its low-side device Q2 is on and its

high-side device Q1 is off to the state where Q1 is on and Q2 is off. When Q1 turns

on, its source is initially zero volts. When the device is on, the source should rise to 12

V. This requires the gate voltage to be 17 V, in order for the transistor to be fully-on.

This is accomplished by using a 5 V supply referenced to the source node of the the

transistor, that is, the gate driver supply voltage is always 5 V higher than the source

of the transistor. When the device is to be shut-off, the gate driver outputs the source

voltage. Q1,3,4,5,7 all require high-side gate drivers.

The scheme for powering the high-side gate driver shown in 3.9 is referred to as

bootstrapping. It is used when the source of a n-type power device is switching between

ground and another potential. A supply charges the bootstrap capacitor while the source

is pulled to ground. When the source rises above ground, the bootstrap voltage rises with


it, and the diode becomes reverse biased. More details of the bootstrapping scheme used

for the 7SFC are included in Appendix A, which was previously described in [11].

Figure 3.9

A block diagram of this driver is shown in Fig 3.10. There are three basic components,

a level-shifter, a schmitt trigger, and a driver chain, which is identical to the driver chain

used in the low-side gate driver. Unlike the low-side level shifter, which is only shifting

the signal with respect to its logic-low supply, the high-side shifter is shifting the signal

with respect to both its logic-low and logic-high supply. The logic-low voltage is shifted

from ground, to a voltage VS, which may be anywhere from 0 V to 42 V. The logic-

high supply is being shifted from 5 V, to a value VB, which is equal to VS + 5V . The

output of the shifter must stay between VS and VB, otherwise it may damage stages

downstream of the level-shifter (and possibly the shifter itself) by exposing transistors to

overvoltage conditions. This is because the maximum permissible gate-source voltage is

5 V regardless of the rating for the drain voltage of the device. It is also desirable that

there be no static-current draw between VB and ground, as this potential difference may

be as high as 47 V and thus result in high power consumption.


Figure 3.10: Showing function of high side driver, when on, output must remain 5 Vabove source voltage

The selected level shifter is the one described in [24]. The schematic is shown in Fig

3.11. This shifter uses a differential pair of transistors which has no static tail current.

When the input of Q1 goes high, it pulls the voltage VOut low. Transistor Q3 prevents

this voltage from going below VS +Vthreshold, where Vthreshold is the threshold value of the

PMOS device. This prevents the output from dropping below VS and exposing devices

downstream of the shifter to an overvoltage condition. This branch going low causes Q8

to turn on and pull VOutB high. This turns Q7 off and Q5 on. This causes Vout to be

pulled all the way down to VS. As Q7 is off, no current will run through the circuit

at this point. When the input is low, the reverse happens, where VOutB goes low and

VOut goes high. The output swing of this level shifter is shown for a number of process

and temperature corners below 3.12. Characteristics of the level-shifter and gate driver

are shown in table 3.3. As current is drawn only when the circuit is being switched,

or when VS is changing, there is no static current draw, which greatly limits the power

consumption. Unlike with competing designs discussed in Appendix D, the inputs are

always active, and will work to keep the circuit in its desired state regardless of whatever

disturbances effect it.


Figure 3.11: Selected level shifter using cross-coupled topology

Figure 3.12: Process and temperature simulations for the level-shifter operated for Vs/VB

of 0/5 and 48/53

Downstream of the level shifter are the schmitt trigger and the driver chain. The


schmitt trigger is used to provide hysteresis. This is important as the power supply may

be very noisy, especially as the supply is floating, and not sitting at a single potential

as referenced to the ground used on the chip. Hysteresis helps prevent the possibility of

the shifter from spontaneously switching back during a transition. The driver chain is

identical to the driver chain used in the high-side gate driver.

Table 3.3: Level Shifter Parameters

Parameters Min Max

Power (μW) 46 360Rise Time (ns) 6 12

Propagation Delay - Gate Driver (ns) 9 34

3.5.3 Gate Driver Layout

The layout of high side driver is shown below. As this is a circuit which will draw very

large amounts of current very suddenly, and contains both n and p devices, special care

was taken during its layout. The n and p devices were placed in separate “deep trenches.”

These trenches consist of large insulators inserted into the substrate to separate it from

the surrounding area. Although this increases the amount of area consumed, it helps

prevent latch-up, where current injected into the substrate causes a positive feedback

loop to form between parasitic devices in the circuit eventually resulting a low-impedance

path directly between the supply voltage and ground.

Figure 3.13: Layout of gate driver


3.6 Top-Level Layout

The top level layout of the chip is shown below in Fig. 3.14.

Figure 3.14: Top Level layout of 7SFC including gate drivers and transistors

Figure 3.15: Switches and gate drivers boxed in using black, pads shown in red


Table 3.4: Inductor Parameters

Manufacturer Part Number Inductance DCR Package Name Volume

Wurth 74479299222 2.2μH 106 mΩ PMCI 1210 9.6mm3

Wurth 74479276222C 2.2μH 135 mΩ PMCI 0806 LR 3.52mm3

In Fig. 3.15 the power transistors, gate drivers, and high-current pads are labeled.

The devices are arranged in the manner of Figs. 3.5 and 3.7.

3.7 Experimental Results

The IC was fabricated in a 0.18 μm 80 V technology (using 24 V devices). Fig.3.16 shows

a photo of the die taken after receiving it back from the foundry.

Figure 3.16: Photo of chip in package with lid removed

The chip was placed in a 48 pin QFN package. A PCB was developed to test this chip.

Measurements were made on the chip using two different sets of inductors. Properties

for these inductors are listed in Table 3.4. The volume provided refers to the volume of a

single inductor of that class, hence the total inductor volume used by 7SFC is twice that

value. Listed in 3.5 are additional components that were used for the 7SFC. There are

the bootstrap diodes, bootstrap capacitors, flying capacitor, and output capacitor. The


Table 3.5: Other Important Components

Part # Used Part Number Parameter Volume

Bootstrap Diode 5 CUS05S40 40 v 4.1mm3

Bootstrap Capacitor 5 GRM155R62A104KE14 100 nF 0.275mm3

Flying Capacitor 2 C2012X5R1H475K125AB 4.7μF 1.1mm3

Output Capacitor 1 C1210C476M4PACTU 47μF 22.4mm3

bootstrap diodes can be integrated on-chip, but it was decided for this prototype to use

off-chip diodes to permit more flexibility during testing. The bootstrap capacitors cannot

be easily integrated on-chip and thus must be used as an external components. The total

volume of 5 bootstrap capacitors is 1.375 mm3, which is insignificant as compared to

other parts of the converter.

3.7.1 Switching Waveforms

The switching nodes and inductor currents for the three major operating modes are

shown below. Additional waveforms showing the gate voltages are provided in Appendix

B. Fig. 3.17 shows the HSD Buck operating region for an input voltage of 12 V. As can

be seen the swiching node voltages go between 0 and 6 V. Fig. 3.18 shows waveforms

for the 3-level buck. The two inductor current waveforms are virtually identical for this

mode, so they are shown with different offsets. The switching waveform is about 6 V as

well. Fig 3.19 shows waveforms for the interleaved buck for an input voltage of 5 V. As

can be seen the switching node voltages are 5 V each as expected. This indicates the IC

is working as expected. Extensive tests were run for a wide range of operating points, the

switching nodes for 42 V operation is shown for the HSD operating mode in Appendix

B as well.


Figure 3.17: Waveforms for 7SFC operating as a HSD Buck, showing inductor currentsand switching node voltages. Inductor currents measured with same offset to show inter-leaved nature and equal current sharing. Ch1: Switching node 1 voltage, 5 V/div. Ch2:Switching node 2 voltage, 5 V/div. Ch3: Current of L1, 500 mA/div. Ch4: Current ofL2, 500 mA/div. The time scale is 500 ns/div.

Figure 3.18: Waveforms for 7SFC operating as 3-Level Buck, showing inductor currentsand switching node voltage,as inductor waveforms are nearly identical different offsetwas used to show difference clearly. Ch1: Switching node 1 voltage, 10 V/div. Ch2:Switching node 2 voltage, 10 V/div. Ch3: Current of L1, 500 mA/div. Ch4: Current ofL2, 500 mA/div. The time scale is 500 ns/div


Table 3.6: Volume Comparison Between 7SFC and Similar Products

Part Number Inductor Flying Capacitor Packaged Silicon Total

LM25011[25] 450mm3 0 37.17mm3 487.17mm3

LMR24220[26] 251.3mm3 0 3.45mm3 254.75mm3

7SFC 1210 19.2mm3 2.2mm3 30.24mm3 51.64mm3

7SFC 0806 7.04mm3 2.2mm3 30.24 mm3 32.928mm3

Figure 3.19: Waveforms for 7SFC operating as 2-phase interleaved buck, showing inductorcurrents and switching node voltages. Ch1: Switching node 1 voltage, 10 V/div. Ch2:Switching node 2 voltage, 10 V/div. Ch3: Current of L1, 500 mA/div. Ch4: Current ofL2, 500 mA/div. The time scale is 500 ns/div

3.7.2 Conventional Solutions and Passive Volume Comparison

Efficiency results for conventional solutions were provided to us by Wurth Elektronik.

These results were gathered using the evaluation boards provided by the companies. The

volume of these solutions are compared to that of the 7SFC when implemented with

0806 inductors and 1210 inductors in Table 3.6. Table 3.7 compares the surface area

consumed as well. Packaged silicon area refers to the area of silicon devices including

packaging used in the various solutions. For the LM25011 this includes an external diode

also placed on the board (as this IC does not contain a synchronous rectifier). In the

following section, the efficiency of the 7SFC will be compared to that of these solutions.

The volume and area comparisons of Tables 3.6 and 3.7 do not include the bootstrap


diodes and capacitors. As mentioned before the diodes can be integrated and thus not

a major concern. The bootstrap capacitors generally cannot be integrated on-chip. In

terms of bootstrap capacitor volume, the 7SFC will require about 5 times more volume

than a conventional buck. However, as this value is quite small, this is not a major

concern in and of itself. The presence of these caps does present a drawback that is more

difficult to quantify. They must be placed and routed to, which can lead to consuming a

larger amount of pcb area then they nominally do. They also require more pads be added

to the IC, which is critical in certain applications. Hence, despite being small overall,

they still detract from the merits of the 7SFC.

Table 3.7: PCB Area Comparison Between 7SFC and Similar Products

Part Number Inductor Flying Capacitor Packaged Silicon Total

LM25011 100mm2 0 28.79mm2 128.792

LMR24220 57.76mm2 0 8.64mm2 66.4mm2

7SFC 1210 19.2 mm2 4.8mm2 36 mm2 56.8 mm2

7SFC 0806 5 mm2 4.8mm2 36mm2 45.8 mm2

3.7.3 Efficiency Results and comparison

Efficiency results for the 7SFC are presented below. The “target” curve refers to the

best efficiency measured from the products the 7SFC is compared to. That is, mea-

surements were taken from a number of existing solutions and the best efficiencies were

compiled into the target curve provided above. Figure 3.20 shows efficiency results us-

ing the PMCI 1210 inductors on the 7SFC where 3.21 shows results using the smaller

PMCI 0806 LR inductors. Generally speaking the 7SFC beats all efficiency targets for

medium to heavy load when using the 1210 inductors. Most targets are met at medium-

heavy load using the smaller 0806 LR inductors. All efficiency results for the 7SFC were

gathered in forced Continuous Conduction Mode (CCM). This is the mode of operation

available in synchronous converters where the inductor current is allowed to go negative.

Discontinuous conduction mode (DCM) on the other hand is where conduction ceases

when the inductor current reaches zero. DCM occurs naturally in bucking topologies

where the low-side devices are implemented as diodes, as these cannot conduct negative

current. In synchronous converters the inductor current must be sensed and the low-side

switch switched off just before the current goes negative in order to achieve DCM. As

neither DCM nor Pulse Frequency Modulation (PFM) were implemented, the light-load

efficiencies listed are pessimistic. PFM is a technique where the frequency is reduced


while operating at light-load in DCM to reduce switching and gate drive losses while

still meeting ripple specifications. If DCM or PFM are implemented the efficiency could

improve considerably although it is unknown if it will be better than competing products

operating in that mode.

Generally speaking, for the HSD mode, lower input voltages and higher output volt-

ages favor higher frequencies, and vice versa. More precisely, lower input voltages but

higher inductor current ripples favour higher frequencies. This is because higher frequen-

cies reduce RMS current by reducing the ripple, but increases Coss losses, which are made

worse by higher voltages. The other operating modes should also work better for higher

switching frequencies when the inductor current ripple is high and the input voltage is

low.


Figure 3.20: Efficiency curves for the 7SFC using 2.2μH inductors in a 1210 package.Title indicates input and output voltages as well as operating mode (3LB = 3 LevelBuck, HSD = High Step Down Buck). Frequencies indicated in legend.


Figure 3.21: Efficiency curves for the 7SFC using the 2.2μH inductors in an 0806 LRpackage. Title indicates input and output voltages as well as operating mode (3LB = 3Level Buck, HSD = High Step Down Buck). Frequencies indicated in legend.

Chapter 4

Single-Mode Controller with Near

Minimum Deviation Transient

Response

Modern switch-mode power supplies (SMPS), especially those used in point-of-load (PoL)

applications, need to meet challenging requirements for both steady state and dynamic

voltage regulation [27], [28]. In targeted applications, for converters processing from

a fraction of a watt to tens of watts, the dynamic performance of SMPS controllers

have a dominant influence on the sizing of the output filter capacitor [20]. As required

output voltages decrease and load currents increase, meeting output voltage regulation

requirements during transients usually requires greatly increased output capacitance

[20],[29],[30],[31]. Power supplies in portable applications have already been shown to

consume a significant portion of PCB real estate [20]. Supply voltages for processors and

other integrated circuits have been continuously decreasing. As output voltages decrease,

and load currents increase, the required size of output filter capacitors continues to grow

[30]. Therefore, it is important to improve the dynamic performance of controllers as

much as possible to limit this growth in area consumption.

This chapter introduces the practical single-mode minimum-deviation concept based

controller of Fig. 4.1. Unlike previous solutions, it uses only one mode of operation for

both steady state operation and during transients, eliminating potential mode transition

related stability problems while also further simplifying the hardware implementation

requirements.

50

Chapter 4. Single-Mode Near Minimum Deviation Controller 51

Figure 4.1: Block diagram of the proposed controller used in a single-phase buck converter

4.1 Review of Fast Transient Controllers

As discussed in section two many fast-transient controllers have been developed. Two

kinds are minimum deviation controllers and time-optimal controllers. Time-optimal

controllers aim to recover voltage in the fastest amount of time possible. They do this by

calculating the current over/undershoot required to recover lost charge within a single

cycle and then returning the inductor current to its steady-state value. However, they

suffer from high computational complexity and require the usage of power hungry high-

speed analog to digital converters [20]. Furthermore they are very sensitive to non-ideal

behavior in converters (losses and parasitics)and small variations in the inductor used

can greatly impact the transient response and lead to voltage overshoots and undershoots

[20]. This in turn can cause the converter to toggle back and forth between its transient

controller and steady-state controller for a single transient.

Several minimum deviation controllers have been proposed. These controllers respond

to load transients in the fastest possible time. They do not suffer from the computational


complexity of time-optimal controllers and have reduced requirements for analog hard-

ware [20]. Furthermore they do not require accurate knowledge of converter parameters

and are mostly insensitive to losses and parasitics. They are however still sensitive to

delays which can result in current over/undershoots. This in turn can lead to toggling

problems. Partly as a result of concerns such as these, control schemes such as these

have not been widely adopted.

This chapter will introduce a single-mode minimum deviation controller. This con-

troller is not susceptible to the toggling issues present in two-mode solutions and is

simpler to implement due to lack of mode-changing and transient detection circuitry.

4.2 Principle Of Operation

The introduced controller is shown in Fig. 4.1. It is a modification of a voltage mode

controller where the conventional pulse width modulator (PWM) is replaced by the load

tracking modulator block. This block consists of two half duty digital pulse width modu-

lator blocks (DPWM1 and DPWM2) and one capacitor current polarity detection block.

The half-duty modulators use information about the capacitor current polarity to gate

the power transistors (Q1 and Q2) such that the inductor current is made to match the

load current cycle by cycle while also reconstructing the desired inductor current ripple.

It does this by splitting both the on-time (Q1 on, Q2 off, inductor charging) and the

off-time (Q1 off, Q2 on, inductor discharging) into two separate phases each. These are

called the current correction phase (CCP) and ripple reconstruction phase (RRP).

The functionality of the controller can be better understood with the help of Figs. 4.2

and 4.3. Fig. 4.2 depicts the operation of a buck converter running with the introduced

control scheme in steady-state. At point 0, the converter enters its on-state. Q1 is on, Q2

is off, and the inductor current is charging up. This first segment is its on-state current

correction phase (CCP). This phase runs until the inductor current equals (or otherwise

exceeds) the load current (point 1 in Fig. 4.2), which in turn causes the capacitor current

polarity to change and become positive. This sends the output of the polarity detector,

vvpd(t) high. This sets the half-duty modulator DPWM1 which marks the beginning of

the on-time ripple reconstruction phase (RRP). Once set, DPWM1 keeps the converter

in its on-state for an additional DTs nom/2 in order to reconstruct its ripple. At this

point the output of DPWM1 will go high and push the converter into its off-state. This

is marked by point 2 in Fig. 4.2. Now, Q1 is turned off, Q2 is turned on and the inductor

current is discharging. The first portion of its off-state is again a current correction


phase. It will remain in its current correction phase until the instantaneous inductor

current equals (or otherwise is less than) the load current. Which occurs at point 3.

The capacitor current again experiences a change in polarity, setting vpd(t) low. The

converter is again in a ripple reconstruction phase. This activates DPWM2 which keeps

the converter in its off-state for an additional (1-D)Ts nom/2 to reconstruct the ripple.

This is point 4 in Fig. 4.2. The output of DPWM2 then goes high, putting the converter

back into its on-state, and the cycle repeats.

Figure 4.2: Ideal waveforms of the proposed control scheme operating in steady-state.From top to bottom are the output voltage and nominal output voltage on the sameaxis, the inductor current and load current on the same axis, the capacitor current, theoutput of the polarity detector, gating signal of Q1, and gating signal of Q2.

In the event of a transient, the controller still operates just as it does in steady-state.

However, the load-tracking modulator will extend either the on-time or the off-time

(depending on the transient) and thus the period for that cycle to address the transient.

This is shown in Fig. 4.3 for a light-to-heavy transient. As the output of the polarity

detector cannot go high until the inductor current equals (or exceeds) the load current,


the duration of the CCP of the on-state is automatically extended. Once the inductor

current has increased to the point that it equals the load current, the converter enters

its RRP and the controller proceeds as before. Heavy to light transients are addressed

similarly, however it is the CCP of the off-state that is extended as opposed to that of

the on-state. From this it can be seen that this control method requires no special blocks

to detect load transients, it simply responds to them as part of its normal operation.


Figure 4.3: Ideal waveforms of the proposed control scheme operating during a light-to-heavy load step. From top to bottom are the output voltage and nominal output voltageon the same axis, the inductor current and load current on the same axis, the capacitorcurrent, the output of the polarity detector, gating signal of Q1, and gating signal of Q2

As shown in Fig. 4.3, there will be an error in the voltage even after the inductor

current has been corrected. This happens because some charge is lost before the inductor

current is corrected. Voltage recovery is handled by the compensator afterwards as

shown in Fig. 4.4, this is similar to conventional voltage mode control. The speed of this

recovery depends on the compensator implemented. This controller may be thought of as


a voltage mode controller with one major difference, it is capable of correcting inductor

current within a single cycle thus achieving near minimum output voltage deviation.

Experimental results taken from a physical prototype are presented in the final section.

Figure 4.4: Voltage recovery after load transient for single-mode controller

4.2.1 Analysis of Switching Period Variation

As the gates are not modulated by fixed-frequency signal, the period/frequency can

vary slightly with perturbations. This section will describe the extent to which this can

happen by. Analysis will also be presented to show that in the absence of perturbations

the period will be equal to the nominal period described above.

For the converter’s on-time, the duration of the current correction phase can be

determined using the following Equation

TON = DTsnom +∆iLtransVg−Vout

L

(4.1)

Where ΔiLtrans is the magnitude of any load step that may have occurred. During steady-

state operation ΔiLtrans=0, thus the converter’s on-time which is equal to the sum of its

CCP and RRP during steady-state operation is found by the following equation

TON SS =DTsnom

2+DTsnom

2= DTsnom (4.2)

Similarly, in the absence of load-steps, the CCP and RRP of the off-time have equal


durations of (1 −D)Tsnom/2. The sum of these provide the off-time.

TOff SS =DTsnom

2+DTsnom

2= DTsnom (4.3)

Hence the effective steady-state period TSW SS defined as the duration required to com-

plete steps 0 through 4 in the absence of disturbances, will be equal to Ts nom.

TSW SS = (1 −D)Tsnom +DTsnom = Tsnom (4.4)

In the case of a load change between points 0 and 1, shown in Fig. 4.2, the switching

period of the converter changes over one switching cycle. In this case, the switching

period can be, calculated using the same procedure and taking the non-zero value of

iL trans into account, i.e.

TSW trans = (1 −D)Tsnom +DTsnom +∆iLtransVg−Vout

L

(4.5)

Similar calculations can be made for a heavy-to-light transient.

TSW trans = (1 −D)Tsnom +DTsnom +∆iLtrans

Vout

L

(4.6)

In general the period of the converter will be extended only when a transient occurs.

Otherwise, it will be equal to Tsnom.

4.2.2 Stability for Small Perturbations

Certain control schemes, like peak current mode control can be made unstable by small

perturbations in certain operating regions. For a buck converter this happens for con-

version ratios greater than 0.5. This happens because only the on-time of the converter

is related to a physical measurement (the peak current). Whereas the off-time consists

simply of the remaining time in the switching period. If the flux-linkage across the induc-

tor is larger during the off-time, than the on-time, errors in the duration of the on-time

get passed to the off-time, causing the error in the inductor current to increase leading

to bifurcation. The proposed control scheme does not suffer from such issues as both the

on-time and the off-time are related to the point where a polarity change in the capacitor

current is detected. Hence small perturbations are rejected within a half a cycle.


4.2.3 Extension to Multi-Phase Operation

This control scheme can be extended to multi-phase converters (such as the 2-phase

interleaved buck. This can be accomplished by comparing the inductor current in each

phase to half of the load current as opposed to using the estimated capacitor current. Fig.

4.5 shows key waveforms for the two-phase case where the period is 2Ts. The modulator

behaves much the same as it does in the single-phase case, however instead of using the

zero crossing point of the capacitor current (which corresponds to a shift in polarity) it

uses the point where the inductor current equals half the load current. Furthermore, the

second phase may not enter its on-state until Ts has elapsed after the first phase entered

its on-state. Following this approach this control scheme may be extended to n-phases

by comparing the current in each phase to the load current divided by n. An added

benefit of this control scheme is that it ensures currents are shared equally in multi-

phase converters, as it forces the average current of each phase to equal iLoad(t)/n. This

eliminates the need for a current-balancing algorithm, simplifying the system. However,

unlike the single-phase implementation, it might not be possible to implement with a

single non-intrusive sensor.

Figure 4.5: Showing response of controller in multi-phase case


4.2.4 Extension to Indirect Energy Transfer Converters

Figure 4.6: Controller modified to be used in a boost converter, note modulator remainssame, only difference is capacitor time constant estimator replaced with 2 sensors anddigital potentiometer

Figure 4.7: Showing waveforms for control scheme applied in boost converter


This control scheme can theoretically be extended to converters employing indirect energy

transfer, examples being a boost or buck-boost converter. In such converters, the inductor

current does not equal the load current, however it is proportional to it. Hence it may

be possible to apply this scheme by comparing the scaled inductor current to the load

current (or vice versa). A schematic depicting how this would look is shown in Fig 4.7.

This scheme takes advantage of the following expression.

iL(t) = iLoad(t)/(1 −D)

Hence, whereas in a buck converter, the inductor current will be equal to the load

current mid-cycle, in the boost, the inductor current will equal the load current, divided

by (1 − D) at this point. Using this to trigger the half-duty modulators instead of the

zero-crossing point of the capacitor current allows the controller to be implemented in

the same way. There are many possible ways to implement it. Fig 4.7 is one possible

implementation. Where 1 − D is passed to a digital potentiometer, which divides the

inductor by 1/(1−D). This is then passed to a comparator, which compares it with the

load current. the output of this is used to trigger the half-duty modulators in the same

way the polarity detector did previously.

It is important to note however this relationship is not perfectly accurate as all con-

verters are lossy. In very lossy converters the difference between this expression and the

true one accounting for losses can be dramatic and could possibly complicate our prevent

the successful implementation of such a controller.

4.3 Practical Implementation

This section will describe implementation details for this controller as applied to a conven-

tional single-phase buck converter. Discussed is the structure of the half-duty modulator

and the implementation of capacitor current estimation techniques.

This control scheme makes use of the capacitor current. More specifically, this con-

troller requires the accurate detection of changes in the polarity of the output capacitor

current. To avoid placing an intrusive sensor in series with the capacitor an estimation

circuit is used. This is done by placing an RC circuit in parallel with the output ca-

pacitor whose time constant is matched with that of the output capacitor and its ESR

[32],[33],[34]. This is shown in Fig. 4.8. Previous implementations have demonstrated

that auto-matching implementations of this approach can accurately detect the capacitor

current polarity and zero current crossing points with a low silicon area [16].


Figure 4.8: Structure of the RC time constant estimator and zero-crossing detectioncircuit

Fig. 4.9 depicts a block diagram of the half-duty DPWM cell. It consists of a counter

and a digital comparator. The set pin is triggered by a pulse of any duration. It causes

the counter to begin counting up. The output of the half-duty DPWM cell goes high

once the counter exceeds the value of the reference supplied to it. The reset pin can also

be triggered by a pulse of any duration, and causes the counter to reset to zero. After a

reset, the counter will not count until another set pulse has been received. The counter

may only be set if the output of the DPWM is low and only reset if the output of the

DPWM is high.

Figure 4.9: Block diagram of half-duty modulator


4.4 Experimental and Simulation Results

To verify the effectiveness of the introduced method an experimental prototype was made

based on the diagrams of Figs. 4.1, 4.8 and 4.9. A single-phase buck converter based

prototype was made with a switching frequency of 600 kHz. Several properties of this

prototype are shown in Table 4.1. The digital controller is implemented using an FPGA

based system, while the additional analog components, shown in Figs. 4.1 and 4.8 are

implemented using off-the-shelf ADCs, comparators and operational amplifiers. Fig. 4.10

depicts simulation results whereas Figs. 4.11 and 4.12 are physical measurements. Fig.

4.10 shows a simulation of the controller responding to a 4 A , 15% to 100% light to heavy

load step. Fig. 4.11a and 4.11b shows experimental results taken from the prototype

for the same transient, while Fig. 4.11c and 4.11d shows its response to an opposite

transient. As in Fig. 4.10, it can be seen that after the current has been corrected, the

voltage ceases to change. This indicates that the current has been correctly adjusted.

It can be seen in both Figs. 4.11c and 4.11d that the inductor current does not change

significantly after the initial correction. The compensator then works to recover the

voltage difference.

Table 4.1: Parameters of fast transient prototype

Parameter Value

Frequency 600 kHzVg 12 V

Cout 100 μFVout 3.3 VPout 15 WResr 10mΩL 3.3 μH


Figure 4.10: Simulation of controller for 4 A load step, depicting output voltage, inductorcurrent, and load current.

Figure 4.11: A: Oscilloscope screenshot showing output capacitor voltage and inductorcurrent after 4 A light to heavy load step, (ILoad 0.6 to 4.6A). Ch1 vout(t) , 100 mV/div.Ch2 iL(t), 2 A/div. Timescale is 2 us/div. B: Zoomed out version of A showing voltagerecovery phase, timescale set to 500 us/div. C: Identical loadstep, except going fromheavy to light, D: zoomed out loadstep shown in C


Figure 4.12: A: Controller responding to consecutive load steps. Ch1 vout(t), 100 mV/div.Ch2 iL(t), 1 A/div, timescale is 5 μs B: Reference step indicating controller’s stability.Ch1 vout(t), 1 V/div, timescale is 1 ms

Fig. 4.12a shows the response of the controller for consecutive load transients. After

the first 1.2 A transient occurs the voltage begins to drop, the drop ceases occurring

once the current has been corrected. A second 1.6 A transient then occurs which causes

the voltage to again drop until the current is corrected. Fig. 4.12b shows the output

voltage during a reference voltage step. This transition occurs smoothly indicating the

controllers stability.

It can be seen that the single mode controller reconstructs the inductor current to its

new steady state value over a single switching cycle with near minimum output voltage

deviation. Also, it can be seen that due to the single mode of operation a smooth settling

of the voltage is achieved without toggling problems often existing in dual mode solutions.

Fig. 4.13a shows simulation results for a load-step on a 2-phase converter utilizing

the introduced control scheme. In this simulation the control scheme is implemented

as described previously. It can be seen that the sum of the inductor currents are made

to match the load in just one switching action (per phase) while otherwise causing the

converter to behave like a conventional 2-phase interleaved buck converter.

Fig 4.13b shows simultion results for a boost converter controlled in the manner

described previously responding to a load-step as well. Plotted in the simulation are the

output voltage, load current, and scaled inductor current (as would be at the output of

a digital potentiometer). As can be seen the scaled current is made to match the load

current cycle by cycle.


Figure 4.13: A: Depicts a load-step for the control scheme applied to a 2-phase converter.B: Depicts a load-step for the control scheme applied to a Boost converter, showing theoutput voltage and scaled inductor current such as would be seen at the output of thedigital potentiometer.

Chapter 5

Conclusions and Future Work

5.1 Integrated Implementation of Emerging Topolo-

gies

An integrated multi-level converter of significant complexity was designed and imple-

mented. It was designed for wide-input and output operating range conditions. The

on-chip power stage consisted of seven power transistors and seven gate drivers to drive

them.

The implementation of such converters requires careful floorplanning and layout.

Carefully planning the arrangement of devices, using the help of a graph detailing peak

average currents on interconnecting branches was shown to be useful in this regard. Us-

ing such techniques, the added routing resistance could be made a small fraction of the

nominal resistance of the device in most cases, despite using only a single thick metal

layer. High voltage level shifters were shown to be implementable while consuming only

a small fraction of the nominal output power of the IC. This is done by using a topology

that consumes no static current. The size of the transistors used were optimized for good

efficiency across the operating range. The efficiency of the on-chip implementation was

compared to the best achievable efficiency of several competing products on the market.

For most operating points it was superior despite using a much smaller total volume.

This indicates the optimization was successful.

5.1.1 Future Work

The chip remains to be tested in discontinuous conduction mode. Doing so will most

likely improve the efficiency of the converter in light load and may allow it to reach

66

Chapter 5. Conclusions and Future Work 67

performance targets it is currently shy of. Integrating a controller on-board the chip as

well in addition to the power-stage would complete the picture.

5.2 A Single-Mode Load-Tracking Voltage Mode Con-

troller with Near Minimum Deviation Transient

Response

A practical single-mode quasi constant-frequency controller which provides near mini-

mum deviation transient-response has been presented. The introduced controller provides

recovery of the inductor current to its new steady state value within one-switching ac-

tion while eliminating problems related to mode transition existing in previous solutions.

The key new element is the load-tracking modulator, which replaces the conventional

PWM used in normal voltage mode controllers. This modulator forces the inductor cur-

rent to match the load current and then reconstructs the desired ripple waveform. An

experimental prototype was constructed demonstrating this control scheme in a single-

phase buck converter operating at 600 kHz. Its response to single and sequential load

steps was shown. Extensions to both multi-phase and indirect energy transfer converters

were proposed. Simulation results for these extensions were presented demonstrating

near-minimum deviation

5.2.1 Future Work

A simple mathematical model for this control scheme is yet to be developed. One chal-

lenge in analyzing it is that the controller does not operate with a fixed period, thus

analysis techniques usually applied to linear converters do not yield useful information.

A proper s-domain model would be useful for optimizing the compensator in the feedback

loop.

Although a prototype was constructed using a single-phase buck converter, physical

prototypes for multi-phase and indirect energy transfer converters have yet to be con-

structed, and only simulation results have been gathered thus far. Furthermore the pre-

cise details about how they would be practically implemented remain to be worked out.

The construction of such prototypes based on the implementations described in chapter

4, would be good final confirmation of the controller’s validity for such converters.

Appendix A

Bootstrapping Scheme

Bootstrapping is used to power the high-side gate drivers. The scheme used is shown

in A.1, this is similar to the one originally proposed previously [11]. This is based on

the “cascaded bootstrapping” scheme initially proposed in [35]. Switches 3, 5, and 7

all use conventional bootstrapping. When there source voltages drop down to zero, the

bootstrap supply charges to 5 V. When the power device turns on, the source node rises

to the intended voltage, with the bootstrap voltage remaining 5 V above it. Switches 1

and 4 cannot use a scheme this simple as for both switches, there exist modes of operation

where the source node never drops to zero. Hence as opposed to using a 5 V supply to

charge the bootstrapping node, the bootstrap node of switch 5 is used. This can be

explained by example. In the interleaved buck mode of operation, the source voltage of

switches 1 and 4 is always the input voltage. When switch 1 turns on, its source voltage

goes from zero to the input voltage. Its bootstrap voltage then rises to the input voltage

plus 5 V. This charges the bootstrap voltages of switches 1 and 4 to be equal to the input

voltage plus 5 V.

68

Appendix A. Bootstrapping Scheme 69

Figure A.1: The bootstrapping scheme used for power the gate drive circuits in thedesigned power stage of the 7SFC

Appendix B

Additional waveforms for IC

In this section gate drive waveforms are shown for the developed IC operating as an HSD

Buck for an input voltage of 12 V. This is to demonstrate the correct functionality of the

chip. The switching node is also shown for the HSD mode of operation when the input

is 42 V.

Figure B.1: Showing gate waveforms for Q1 and Q2 as well as the two main switchingnodes

70

Appendix B. Additional waveforms for IC 71

Fig B.1 shows waveforms for the gates of Q1 and Q2. When Q1G is low, its voltage is

6 V, equal to Vg/2. When it turns on, it rises to about 17 V, which is equal to the input

voltage plus the drive voltage. When it goes up, vsw1(t) goes up to 6 V, which is equal

to half the input voltage. When Q2 is on, its gate goes to 5 V, and vsw1(t) goes to zero.

Figure B.2: Switching waveforms for HSD mode of operation, showing gate of switch 4and 6, as well as switching node 2

Fig. B.2 shows waveforms for the gates of Q4 and Q6. When Q4 is low, its voltage is

6 V during state 1. This is because Q1 being on, causes the source of Q4 to be equal to

Vg - Vcfly. For states 4 and 2, it is off, causing gate voltage to be zero. During state 3 it

turns on, and gate voltage rises to 11 V, as this increases its source and vfly2 to be 6 V.

When Q6 is on, its gate goes to 5 V, and vsw2(t) goes to zero.


Figure B.3: Switching waveforms for HSD, showing gate of switch 3, 1, and vsw1(t)

Fig. B.3 shows waveforms for the gates of Q3 and Q1. As Q3 is always on during

HSD mode operation. As a result, Q3g is 5 V when Q1 is off. When Q1 turns on, the

source of Q3 rises to be equal to Vg - Vcfly. This pushes the gate of Q3 up to 11 V.


Figure B.4: Switching waveforms for HSD, showing gates of switches 7 and 1 as well asvsw1(t)

Fig. B.4 shows the waveforms of the gates of Q7 and Q1. When Q7g goes high, during

state 4, the voltage goes up to 5 V. Once Q1 turns on during state 1, the source and thus

gate node of Q7 rise by 6 V (to be 11 V). When Q1g turns back off, the gate drops down

again to 5 V.


Figure B.5: Switching waveforms for HSD, showing gate of switch 5, 4, and vsw2(t)

Fig. B.6 shows waveforms for the gates of Q4 and Q5. Q5 has its gate turn to 5 V

during state 2. When state 3 occurs, its source is raised up to 6 V, causing the gate to

rise to 11 V. When Q4 turns off again in state 4, the Q5g drops back down to 5 V. Q5

turns off again for state 1.


Figure B.6: Switching nodes and low-side gating signals when operating in HSD modefor 42 V input voltage.

Appendix C

Efficiency Curves

Figure C.1: Additional efficiency curves using the inductors in the 0806 LR package

76

Appendix C. Efficiency Curves 77

Figure C.2: Additional efficiency curves using using the inductors in the 1210 size package

Appendix D

Alternate Level Shifter Topologies

One option for the level shifter is the simple pulsed SR latch depicted in Fig. D.1. When

the input goes high, a brief pulse is generated which turns the device Q1 high. This draws

current through the resistor R1, pulling the node labelled Vout low. This passes through

an inverter and sets the SR latch. For a reset the same thing happens with the second

branch. As this topology only draws current during a switching action, it can consume

a relatively low amount of power, as it consists of a small number of devices it will also

consume a relatively small amount of area. This topology is problematic however as it is

extremely susceptible to process, temperature, and voltage variations. Across a full set

of corners the swing can vary enormously. This can easily expose stages downstream of

the level shifter to overvoltage, or conversely create too small a swing to be registered

by the consecutive stage. The output swing for a variety of process corners is shown in

Fig. D.2. Nominally it is about 5 V, however, it can be as 7.5 V, and as low as 2.5 V,

depending on the value of VB and the process and temperature conditions.

78

Appendix D. Alternate Level Shifter Topologies 79

Figure D.1: Pulsed SR Latch based level-shifting topology

Figure D.2: Simulation showing output swing of pulsed SR latch across process andtemperature corners

This shifter can be modified to the one of Fig. D.3 where a PMOS whose gate is

biased to VS is placed in each branch, to prevent the output voltage from being pulled

below VS. Thus, instead of sizing the current and resistance value to generate the desired

swing, the pull-down devices are sized to achieve maximum voltage swing in the PVT

corner where the swing is smallest. The added PMOS devices prevent the voltage from

being pulled lower in corners where the swing is larger. A drawback of this is that it

does not have full voltage swing, as it can only pull the output as low as VS + Vthp,


where Vthp is the threshold voltage of the PMOS device. This problem is exacerbated

by the fact that the threshold voltage also varies with PVT corners, leading to slightly

variable swing. This reduces the noise margin for the following stage as it must be able

to detect the smallest generated swing voltage as a low voltage. This topology also

has some other severe drawbacks. There is a significant tradeoff between the speed of

the shifter and its power consumption. As larger load resistors require less current to

generate the desired swing than smaller ones do, they consume less power. However, this

increases the RC time constant formed by the load resistor and parasitic capacitance at

the output nodes. If this time constant is too large, the circuit can becomes too slow to

respond to changes in VS and VB. This can cause a false triggering of the SR latch or

expose stages downstream of the level shifter to overvoltage as shown in Fig. D.4. In

addition to this, this design is relatively power hungry, consuming 3.5 mW in its worst

process corner. This is comparable to the gate drive losses of the stage that it is driving.

This topology is better suited when very high voltages are required as it can achieve

better ramp immunity (when combined with additional circuitry) then the level shifter

ultimately used, this was not necessary for the IC being developed, as the large relatively

large Coss values coupled with the modest switching node voltages limited the slew rate

of the switching node.

Figure D.3: Modified level shifter to limit swing to less than 5 V


Figure D.4: Simulation showing level shifter perforamance across several corners

Also considered was the “bootstrapped” topology shown in Fig D.5. This topology

applies the concept of bootstrapping, usually used to power high-side gate drivers, to

the level-shifting itself. It consumes very little power. However it suffers from several

drawbacks. First, it may only be used if the source voltage is 0 at the moment of turn-on,

which makes it unsuitable for several of the switches in the 7SFC. Additionally, it will

not have full-swing, facing similar challenges to the protected latched topology. Hence it

was not an attractive design.


Figure D.5: Schematic of bootstrapped level shifter

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