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Predicting Performance Impact of DVFS for Realistic Memory Systems Rustam Miftakhutdinov Eiman Ebrahimi Yale N. Patt
Predicting Performance Impact of DVFSfor Realistic Memory Systems
Rustam MiftakhutdinovEiman Ebrahimi
Yale N. Patt
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V
f
Dynamic Voltage/Frequency Scaling
Image source: intel.com
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fopt
Impact of Frequency Scaling
frequency
time
power
energy
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fo
Impact of Frequency Scaling
power
time
frequency
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fopt
Prediction Overview
instructions
frequency
energy perinstruction
100K 200K 300K0
fo freq.
time
fo freq.
powerfo
fo freq.fopt
energy
our work
×
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Outline
Intro to performance prediction
Why realistic memory systems?
Variable memory latency
Prefetching
✓
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V
f
Why Realistic Memory System?
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Prior Work
• Stall time
• Leading loads (2010) S. Eyerman et al. G. Keramidas et al. B. Rountree
Evaluated withconstant access latency memory system
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Energy Savings
Constant Access Latency
Realistic DRAM Realistic DRAM + Streaming Prefetcher
0123456789 Oracle
Stall timeLeading loadsOur predictor
Norm
. Ene
rgy
Savi
ngs
(%)
< 0.1
Gmean of relative savings for 13 memory-intensive SPEC 2006 benchmarks.Baseline: most energy-efficient static frequency for SPEC 2006
*
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Energy Savings
Constant Access Latency
Realistic DRAM Realistic DRAM + Streaming Prefetcher
0123456789 Oracle
Stall timeLeading loadsOur predictor
Norm
. Ene
rgy
Savi
ngs
(%)
< 0.1
Gmean of relative savings for 13 memory-intensive SPEC 2006 benchmarks.Baseline: most energy-efficient static frequency for SPEC 2006
*
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Outline
Intro to performance prediction
Why realistic memory systems?
Variable memory latency
Prefetching
✓✓
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Execution Example
chipactivity
memoryrequests A
BC
DE
1 2 3 4time
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T = Tmemory + Tcomputeindependent offrequency
proportional tocycle time
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to
Linear Modelexecution time T
cycle time t
Tmemory
Tcompute
0
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Measuring Tmemory
chipactivity
memoryrequests
time
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Measuring Tmemory
chipactivity
memoryrequests
time
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Causes of Request Dependences
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Pointer Chasing
instruction window
miss miss
Finite Chip Resources
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Measuring Tmemory
chipactivity
memoryrequests
time
Critical Path Algorithm
at Tstart 1. record Tstart and Tmemory
TendTstart time
Tmemory
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at Tend 2. compute path = Tmemory(Tstart) + (Tend - Tstart)old critical path request latency
3. set Tmemory = max(Tmemory, path)
new Tmemory
(length of critical path)
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to
Linear Modelexecution time T
cycle time t
Tmemory
Tcompute
0
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Linear Model
to
execution time T
cycle time t
Tmemory
Tcompute
0
to cycletime
Tm
time
fo freq.
time
fo freq.
power
fo freq.fopt
energy
×
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Critical Path: Variable Access Latency
chipactivity
memoryrequests
time
Leading Loads: Constant Access Latency
timechipactivity
memoryrequests
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to
Leading Loadsexecution time T
cycle time t
Tmemory
Tcompute
0
leading loads
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Leading Loads
to
execution time T
cycle time t
Tmemory
Tcompute
0
leading loads
to cycletime
Tm
time
fo freq.
time
fo freq.
power
fo freq.fopt
energy
×
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Energy Savings
Constant Access Latency
Realistic DRAM0
1
2
3
4
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8 OracleStall timeLeading loadsOur predictor
Norm
. Ene
rgy
Savi
ngs (
%)
Gmean of relative savings for 13 memory-intensive SPEC 2006 benchmarks.Baseline: most energy-efficient static frequency for SPEC 2006
*
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Outline
Intro to performance prediction
Why realistic memory systems?
Variable memory latency
Prefetching
✓✓✓
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chipactivity
memoryrequests
time
Prefetcher OFF
Prefetcher ON
chipactivity
memoryrequests
Streaming Workload
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Limited Bandwidth Modelexecution time T
cycle time t
Tdemand
TcomputeTmemorymin
tcrossover0
Energy Savings
29Gmean of relative savings for 13 memory-intensive SPEC 2006 benchmarks.Baseline: most energy-efficient static frequency for SPEC 2006
*
Constant Access Latency
Realistic DRAM Realistic DRAM + Streaming Prefetcher
0123456789 Oracle
Stall timeLeading loadsOur predictor
Norm
. Ene
rgy
Savi
ngs
(%)
< 0.1
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Recap
Intro to performance prediction
Why realistic memory systems?
Variable memory latency
Prefetching
✓✓✓✓
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Final Thought
Performance predictors need realistic evaluation
