Presentation on Dissertation Phase-1_PLL

8/7/2019 Presentation on Dissertation Phase-1_PLL

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Prepared by: Guided By:

Nagpara Bharat H. Prof. R. S. GajareME EC Sem.-III.Enrolment No.:90440704012

C. U. SHAH COLLEGE OF ENGINEERING & TECHNOLOGY,WADHWAN CITY- 363 030


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` Area of Interest & its Justification.` Work-plan for Dissertation Phase I.` Raw Title of the Dissertation.` Final Title of the Dissertation.` Scope of the Thesis.` Supplementary Work Carried Out.` Work to be carried out in Semester-IV


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` With the advances in CMOS technology, digital signalprocessing is penetrating into more and moreapplications.

` CMOS technology scaling has been a primary driver of the electronics industry.

` Minimum channel length of MOS transistors droppedfrom 25 m in 1960s to 65 nm in the year 2004.` Advantages of CMOS

has High speedrequires Less areadissipates Less power low fabrication cost

` Large scope to improve existing technology or to inventnew technology.


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`

CMOS technologies become mainstream technologiesfor mixed-signal integration due to the advantages of high speed, low power and high integration density.

` CMOS technologies are used in various applicationsCellular phones and Wireless local area networks,Optical communications,Disk drive read/write electronics,Microprocessors and memories,Circuits for Sensors,

Filters and oscillators,PLLs and A/D and D/A convertersetc.


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` Counseling` Literature Collection` Literature Review` Finalizing the Topic` Finalizing Software` Reporting` Dissertation I Final Reporting.


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` In most modern communication systems timinginformation, in the form of clock or oscillator signals, plays a critical role in systemperformance.

` Timing information is precious in everycommunication systems.

`

Timing information is provided through a localoscillator.


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` Minimizing the timing errors in system isimportant.

` PLL is a circuit that reduces timing errors &

synchronizes the signal.` Phase Locked Loops are used in most of

applications such asoptical communication systems,

disk drive systems,local area networks,radio transmitters and receivers,


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microprocessors,network routers, anddigital signal processorsetc.


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` Why PLL?For high speed application, jitter is a problem tocommunication system, as it reduces the performanceof overall circuitry.

As jitter is a type of corruption that cannot beeliminated, reducing jitter is one way to help toimprove the system performance.


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` Phase-locked loops (PLLs) are widely used incommunication systems. With the continuouslyexpanding of market for high speed, portablecommunication devices, and low power-low noiseCMOS submicron integrated circuit, designs of PLL for different applications are in large demand.

` The increased application of PLLs has led to thedesire to reduce the Jitter and extend the Capturerange of the PLLs.


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` Phase-Locked Loop Basics.A phase-locked loop is a feedback control circuit.

` A basic form of a PLL consists of threefundamental blocks, namely,

Phase detector (PD),Loop filter,Voltage controlled oscillator (VCO),

Divide by N.` The basic block diagram is shown in Figure1.


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Figure 1: A Basic Phase Locked Loop


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` Terminology of PLLLock range:x The range of input signal frequencies over which the loop

can maintain the lock is called as Lock Range or TrackingRange of PLL.

Capture range:x The range of input signal frequencies over which PLL can

acquire a lock is called as Capture Range or AcquisitionRange of PLL.

Pull in time:x The total time taken by the PLL to capture the signal (or

to establish the lock) is called as Pull in Time of PLL. It isalso called as Acquisition Time of PLL.


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` Non Ideal Effects in PLLJitter in PLL:x A jitter is the short term-term variations of a signal with

respect to its ideal position in time.

Phase Noise:x Phase noise is random variation of phase of the signal. It

is the frequency domain representation of rapid, shortterm fluctuations in the phase of the wave, caused by

time domain instabilities (jitter).


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` This dissertation is aimed at design andimplementation of a circuit for a digital phase lockedloops, characterizing the components anddiscussing a method of estimating the capture

range, jitter, and phase noise.

` The dissertation will attempts to design andimplementation of PLL in sub-nanometer CMOS

technology in LT spice software which is a graphicaltool for design capture and analysis.


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` Prepared a paper on Phase Frequency Detector with ChargePump for Digital Phase Locked Loop and this paper has beenselected in International Conference on Computer Engineering and Technology (ICCET10) at Jodhpur, and

same paper will be published in International Journal byorganizing committee.` Prepared a paper on Design and Analysis of 100 MHz

Voltage Controlled Oscillator (VCO) for DPLL using DeepSubmicron CMOS Technology and this paper has been

selected in ICSSA-2011 at Vallabh-Vidyanagar, and samepaper will be published in International Journal by organizingcommittee.


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` Counseling with the guide regarding the design andimplementation of PLL.

` Literature Collection for design and implementation of PLL.` Detailed study of literature material.` Defining various Components for design and implementation of

PLL.` After defining various Components, design and implementation

of the each Components will be created.` Implementation of the different architectures of PLL in LTspice

and its simulation.` Estimation of Capture Range and Jitter for the different

architectures of PLL.


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` Troubleshooting and comparison of the results for differentarchitectures of PLL.

` Drafting of Dissertation thesis.` Final reporting after counseling with guide.` Submission.


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Thank You

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Presentation on Dissertation Phase-1_PLL

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