TechnologyAdvantages for Analog/RF & Mixed-Signal Designs

Andreia Cathelin

STMicroelectronics, Crolles, France

SOI Consortium Forum, Tokyo, January 21st , 2016

Agenda

• At a glance

• ST 28nm UTBB FD-SOI CMOS: Simpler Analog Integration

• Advantages for analog design

• Advantages for RF/mmW design

• Advantages for Mixed-Signal design

• Conclusion and takeaways

2

Nota: all measurement data from ST 28nm FD-SOI CMOS, unless otherwise specified

Transistor

Typical Transistor in today

CMOS System on Chip

Change of Substrate adding

the thin Buried oxide

Bulk

Substrate

Gate

Source Drain

Substrate

Gate

Ultra-Thin Buried oxide

Source Drain

PunchThrough !

Improving power Efficiency – Bringing high flexibility in SoC integration

While keep very similar manufacturing flow

3

FinFET

Fully Depleted Transistors

FinFET & FD-SOI : Just a rotation ultimately converging when scaling BOX to TOX

Addressing Digital Markets 5

FinFet

High end servers

Laptops & tablet-PC

Networking

Infrastructure

Consumer

Multimedia

Internet of Things,

Wearable

Automotive

Smartphone

Ultimate Digital Integration Ultimate Digital + AMS + RF + … Integration

Available from

28nm node

RF Analytics

CPU & Memories

Power Management

Example: Ultra Low Power in IoT 6

Power

Supply Loss

RF

Analytics

CPU &

Memories

Other

SoC Architecture

SoC Power Consumption34 mW*

ST 28nm FD-SOI Transistor Flavors 7

BOX BOX

VBBPVBBN

GSD

GSD

P-WellN-Well

P-Sub

PMOSNMOS

BOX BOX

VBBNVBBP

GSD

GSD

P-WellN-Well

P-Sub

NMOSPMOS

-3 3-0.3

-3 3VBBN+0.3

-3 3-0.3

-3 3VBBP+0.3

Nominal VBB

GND

GND

VDD

GND

LVT NMOS

LVT PMOS

RVT PMOS

RVT NMOS

Biasing mode

FBB

FBB

RBB

RBB

-3 -2 -1 0 1 2 3-0.6

-0.4

-0.2

0.0

0.2

0.4

0.6

FBB

RBB

RBB

FBBVth

(V

)

VB (V)

NLVT

NRVT

PLVT

PRVT

Bulk type CMOS

Regular VT (RVT) CMOS in FD-SOI

Low VT (LVT) CMOS in FD-SOI; flipped-well

VDD

for Simpler Analog Integration 8ST 28nm FD- SOI makes analog/RF/HS designer’s life easier

Efficient Short Devices

Improved Analog Performance

Improved Noise

Speed increase in all analog blocks

Higher gain for a given current density

Higher bandwidth

Lower power

Smaller designs

Improved design margins

wrt PVT variations

Novel flexible design

architectures

Lower gate and parasitic capacitance

Lower noise variability

Better matching for short devices and

efficient design with L>Lmin

Very large VT tuning rangeAnalog parameters wide range tuning via a

new independent “tuning knob” (back-gate)

High performance frequency

behavior

fT/ fmax >300GHz for LVTNMOS and high

performance passives enabling RF/mmW/HS

integration with technology margin

Advantages in Analog Design 9

• Efficient use of short devices : • High analogue gain @ Low L• Low Vt mismatch (Avt ~ 2mv/µm)

• Performance example:• A 10µm/100nm device has a

DC gain of 100, & a sVt of only 2mV !

• Higher Gm for a given current density

• Lower gate capacitance

Higher achievable bandwidth or

lower power for a given

bandwidth

1,E-11

1,E-10

1,E-09

1,E-08

1,E-07

1,E-06

1,E-08 1,E-07 1,E-06 1,E-05 1,E-04 1,E-03 1,E-02

SI d

/Id²(

/Hz)

Idrain(A)

NMOS_SOI_W=9(µm)model

L=0,903(µm)

L=0,03(µm)

1,E-11

1,E-10

1,E-09

1,E-08

1,E-07

1,E-06

1,E-08 1,E-07 1,E-06 1,E-05 1,E-04 1,E-03 1,E-02

SI d

/Id²(

/Hz)

Idrain(A)

NRVT_Bulk_W=9(µm) modelL=0,903(µm)

L=0,03(µm)

L=9,903(µm)

L=0,273(µm)

0

0,05

0,1

0,15

0,2

0,25

0,3

0,35

0,4

0,45

0 5 10 15 20 25

σ(l

og

(W*L

*SI d

/Id²)

)

1/sqrt(W*L)(µm-2)

NMOS C028_SOI

C045

C028_LVT

• Same normalized drain current

noise between BULK and FD-SOI

• Lower noise variability for FD-SOI

• Improved noise in FD-SOI

Efficient Short Devices

Courtesy, L. Vogt, F. Paillardet, C. Charbuillet, P. Scheer, STMicroelectronics

Improved Analog Perf. Improved Noise

Advantages in Analog Design-II 10

• Flip-well devices:

• Large Forward Body Bias (FBB) range

• Negligible control current

• Use back-gate as « VT tuning knob »:

• Unprecendented ~250mV of tuningrange for FD-SOI vs.

• ~ 10’s mV in any bulk

Very large VT tuning

range by FBB

Courtesy, A. Cathelin, STMicroelectronics

FD-SOI(flip-well flavor/LVT devices)

P-Sub

FBB

VBBP

VBBN

0V

+3V

-3VP-sub

Bulk

FD-SOI

Forward body bias [V]

VT

[mV

]

ST 28nm LVT NMOS

(typical)

Analog Filter Design Example

• Filters with several 100’s MHz

bandwidth- PVT + ageing affect system operation

- Need to tune/trim independently several

parameters impacting overall system:

• cut-off frequency,

• linearity,

• noise,

• all for an optimal power consumption

11

Regular CMOS Tuning/trimming solution: Voltage

regulator impacting directly the signal path behavior

FD-SOI revolutionary solution: individual transistors body

biasing oxide-isolated from the signal path behavior

Filter

supply

Global

supply

VDD

VFilterTuning

margin

Regulator

drop

(>20%)

Typical example of Analog Filter

• Inverter-based analog functions:

• attractive implementations: simple and

compact

• scale nicely with technology nodes

• Here: analog low-pass Gm-C filter

• Typical implementation:

• Fixed capacitors

• Tune the filter cut-off frequency by

tuning Gm

12

Bulk

specific solution:

Tune local Vdd

Local VDD

FD-SOI

specific solution:

Tune all VBB’s

Tuning Gm with VDDOK: gm variation; NOK: linearity

13

gm

Vinput

high

nominal

low

VDD

0

• Tune Gm value with local VDD

• Major issue: it changes also

linearity and noise behavior

Local VDD

FD-SOI: Tuning gm with VbodyOK: gm variation; OK: linearity

• New tuning knob (and off the signal path): VBBP and VBBN

• Compensate VDD variations

• Tune gm back to nominal

• Ensure constant linearity operation

14

Vinput

gm

Vinput

gm

Without back-gate bias With back-gate bias

high

nominal

low

VDD

00

Inverter-based Analog Filter 15• RF low-pass Gm-C filter using CMOS

inverters

‒ Tuned by back-gate instead of supply (no signal path interference)

‒ Supply regulator-free operation

• Energy efficient

• Low voltage operation (VDD = 0.7V)

‒ Competitive linearity

• Compared to similar circuit in 65nm bulk

[2], at same noise level, get X2 linearity for

/4 power level

• Compared to best-in-class filters [7], at

same noise level and Fc, get competitive

linearity for /14 power level

• Best in class in terms of the compromise

noise-linearity-power

• Integrated in ST 28nm FD-SOI CMOS

[2] Houfaf, et al., ISSCC 2012

[5] Saari, et al., TCAS-I 2009

[6] Mobarak, et al., JSSC 2010

[7] Kwon, et al., TMTT 2009

[J. Lechevalier at al, ISSCC2015]

Advantages in RF/mmW Design 16

• For RF operation

frequency :

• Work with L = 100nm• MAG = 12dB @10GHz• NFmin ~ 0.5dB @ 10GHz• Work @ current density: 125

µA/µm

• Operation frequency range :

2 GHz - 50 GHz

• Inductance range: 0.1 nH -

28 nH

• Q factor range: 20 - 35

• Size: 60x60 µm² – 600x600

µm²

Active devices high frequency performance

Courtesy, L. Vogt, F. Paillardet, C. Charbuillet, P. Scheer, C. Durand STMicroelectronics

Performant passive

devices

• For mmW operation

frequency (intrinsic models):

• Work @ Lmin• MAG = 12dB @60GHz• NFmin ~ 1.3dB @ 60GHz• Work @ current density: 200

µA/µm 33% less power thanin 28LP bulk

• For ST 28nm FD-SOI LVTNFET: fT/ fmax >300GHz

Nbt = 1

Nbt = 2 to 6

JSSC, 2010

ISSCC, 2014

JSSC, 2013

JSSC, 2012

RFIC, 2014

ESSCIRC, 2014

RFIC, 2014

MWCL, 2015

0

1

2

3

4

5

6

7

8

9

10

12 13 14 15 16 17 18 19 20

Avera

ge P

AE

(at

8-d

B b

ack-o

ff)

[%]

1-dB compression point [dBm]

CMOS 40nm

CMOS 65nm

PA

E a

t 8

-dB

ba

ck

-off

[%

]

Average

power

High dc consumptionLow average PAE

Output

power [dBm]

Dis

sip

ate

d p

ow

er

[mW

]

High PAPR

Output power

at 8-dB back-off

60GHz PA

0

200

400

600

800

1000

1200

JSSC 2011 ISSCC 2011

JSSC 2013 ISSCC 2014

ISSCC 2014

dc c

onsu

mpt

ion

[mW

] PA

Other TX blocks

60-GHz transceivers (RF TX part)

65nm

90nm

40nm

65nm65nm

50% power in mmW TRx spent in PA

WiGiG with max.

operation probability @

8dB back-off high

linearity with optimized

power

Solve the general trade-off linearity and

power consumption

17

Novel mmW Power Amplifier thanks to FD-SOI and wide-range body biasing

18

• Revisit classical Doherty power

amplifier architecture

• Two different class power amplifier

in parallel• Ability of gradualy change the overall

class of the PA (mix of class AB and class C) thanks to wide range FBB optimise in the same time power efficiency and linearity

• Remove signal path power splitter

as in classical implementations reduced signal path losses

Class C

VG_DC, RFIn-

VB1 VB1VB2

RFIn+, VG_DC

VDD, RFOut+ RFOut-, VDD

Class AB Class AB Class C

Classical Doherty

Power Amplifier

FD-SOI-specific

Doherty

Power Amplifier

60GHz Configurable PA 19• Fully WiGiG compliant (linearity and

frequency range)

• New PA architecture: continuously

reconfigurable power cells

• Continuous operation class tuning

thanks to body bias with 2 extreme

modes:

• High gain mode: Highest ITRS FOM

• 10X better than previous SoA

• High linearity mode: Break the linearity /

consumption tradeoff

• ULV high efficiency operation

(Vdd_min = 0.8V)

• Integrated in ST 28nm FD-SOI CMOS

This work S. Kulkarni

ISSCC 2014 D. Zhao

JSSC 2013 D. Zhao

JSSC 2012 E. Kaymaksut

RFIC 2014 A. Siligaris JSSC 2010

Technology 28nm UTBB FD-SOI 40nm 40nm 40nm 40nm 65nm PD-SOI

Operating mode High gain High linearity NA Low/High power NA NA NA

Supply voltage [V] 1.0 1.0 0.8 0.9 1.0 1.0 0.9 1.8

Freq. [GHz] 61 60 60 63 61 60 77 60

Gain [dB] 35 15.4 15.1 22.4 16.8 / 17 26 9 16

PSAT [dBm] 18.9 18.8 16.9 16.4 12.1 / 17 15.6 16.2 14.5

P1dB [dBm] 15 18.2 16.2 13.9 9.1 / 13.8 15.6 15.2 12.7

PAEmax [%] 17.7 21 21 23 22.2 / 30.3 25 12 25.7

PAE1dB [%] 9 21 21 18.9 14.1 / 21.6 25 11.1 22.6

PAE8dB_backoff [%] 1.5 8 7.5 3 - / 4.7 5.8 3.5 2.7

PDC [mW] 331 74 58 88 56 / 75# 117 126 77.4

PDC_8dB_backoff [mW] 332 124 84 94 56 / 78# 120 140 79

100xP1dB/PDC 9.6 89 72 28 14.5 / 32# 31 26 24

Active area [mm²] 0.162 0.081 0.074 0.33 0.1 0.573*

ITRS FOM [W.GHz²] 161,671 1,988 1,198 6,925 641 / 2,832 13,009 236 1,038

ITRS FOM = PSAT.PAEmax.Gain.Freq² * : with pads # : estimated

[A. Larie et al., ISSCC2015]

Advantages in MS Design 20

• Tighter process corners and less

random mismatch than

competing processes

• Benefits:

• Simpler design process, shorter design cycle

• Improved yield or improved performance at given yield

Variability

Courtesy, S. Le Tual, STMicroelectronics; B. Murmann, Stanford Univ.

Switch performance Lower capacitance

• Improved gate control allows smaller

VTH

• Backgate bias allows for VTH

reduction by tuning

• Results is an unprecedented quality

of analog switches

• Compounding benefits: smaller R ->

smaller switch -> compact layout ->

lower parastics -> even smaller

switch

• Key for high performance data

converters and other Switched-

Cap. Circuits

• Lower juction capacitance

makes a substantial difference in

high-speed circuits

• Drastic reduction of self-loading in gain stages

• Drastic reduction of switch self-loading

• Two-fold benefit:

• Leads to incremental improvements

• Allows the designer to use circuit architectures that would be infeasible/inefficient in bulk technologies

High-Speed Time Interleaved-ADC example 21

• Lower Vth, less variability

• Better switch: RON & linearity

• Faster logic

• Reduced S/D capacitances

• Increased comparator BW

• Reduced switch parasitics

Verma

ISSCC 2013

Tabasy

VLSI 2013

Kull

VLSI 2013This Work

Technology 40nm CMOS 65nm CMOS 32nm SOI 28nm FD-SOI

Architecture TI-FLASH TI-SAR TI-SAR TI-SAR

Power Supply (V) 0.9 1.1 / 0.9 1 1

Sampling Rate (GS/s) 10.3 10 8.8 10

Resolution (bits) 6 6 8 6

Power Consumption (mW) 240 79.1 35 32

SNDR @ Nyquist (dB) 33 26 38.5 33.8

Active Area (mm2) 0.27 0.33 0.025 0.009

FOM @ Nyquist (fJ/conv) 700 480 58 81

Max Input Frequency (GHz) 6 4.5 4.2 20

Gain/Skew Calibration Yes Yes Yes No

[S. Le Tual et al., ISSCC2014] • Energy efficient operation

• Integrated in ST 28nm FD-SOI

CMOS

O : 28FD-SOI or 32nm SOI

Courtesy, B. Murmann, Stanford Univ.

Takeaways for Analog/RF/mixed-signal

• ST 28nm FD-SOI CMOS arguments:

• For Analog/RF design:

• FBB as VT tuning knob ultra large tuning range for VT

• Very good analog performance lower power consumption

and operate at L>Lmin for design margin

• For RF/mmW design, operate at Lmin and add:

• Deep submicron technology features:

• Front-end: performant fT, fmax

• Back-end + FD-SOI features: performant passive devices

• For mixed-signal/high-speed design:

• Improved variability

• Switch performance

• Reduced parasitic capacitance

22

Efficient Flexible Simple

Take-aways charts per field

Analog/RF design in FD-SOI

• FD-SOI arguments:

• FBB as VT tuning knob ultra large tuning range for VT

• Very good analog performance lower power consumption and operate at L>Lmin for

design margin

• Consequences on analog/RF design:

• Operate amplifiers at constant Gm

• Employ new tuning strategies

• Competitive noise and linearity behavior

• Obtain strong design independence with respect to PVT variations

• New robust design oportunities

24

RF/mmW design in FD-SOI

• FD-SOI arguments:

• FBB as VT tuning knob ultra large tuning range for VT

• Very good analog performance lower power consumption

• Deep submicron technology:

• Front-end: performant fT, fmax

• Back-end + FD-SOI features: performant passive devices

• Consequences on RF/mmW design:

• New family of reconfigurable topologies; new design architectures

• Power efficient solutions

• State of the art implementations with concomitent optimisation for each system-level parameter

• New robust design oportunities

25

Mixed-signal / High-speed design in FD-SOI

• FD-SOI arguments:

• Improved variability

• Switch performance

• Reduced parasitic capacitance

• Consequences on MS design:

• State of the art HS Data Converters

• Drastic improvement of the Nyquist FOM (FOM=P/(fs*2ENOB) )

• New robust design oportunities and new design architectures enabled

26