Presented by: Andrey Panchenko

• A number one goal in building an IC is to get millions and even billions of

transistors to all function, not just once but for billions of consecutive cycles.

• Over the coarse of a life time, an IC Chip may be subjected to variations in

temperature, intense electric fields, unrelenting currents, cosmic rays and many

more potentially hazardous encounters

• Despite these challenges, engineers still manage to build robust integrated

circuits with lifetimes exceeding ten years of continuous operations.

Standard Minimum Maximum

Commercial 0° C 70° C

Industrial -40° C 85° C

Military -55° C 125° C

• Variations in

temperature effect

performance of the IC

•Device Variation

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�Vt Variations

•Interconnect Variations

IC must function properly in all

four process corners

Hard errors that cause integrated circuits to fail permanently:

• Oxide wearout

• Interconnect wearout

• Overvoltage failure

• Latchup

Soft Error

• Alpha particle collisions

Stress on the gates causes an oxide wearout which then shifts threshold voltage

and increases gate leakage.

Eventually circuits fail due to:

• transistors become too slow

• leakage current becomes too great

• mismatches become too large

Electromigration

• Electomigration is also highly

sensitive to temperature

• Constant brief pulses of high peak

currents may even melt the

interconnect

•Tiny transistors can be easily damaged by relatively low voltages

•Overvoltage can be triggered by excessive power supply transients or

by electrostatic discharge from static electricity

•Overvoltage at the gate node accelerates oxide wearout

•DC oxide breakdown voltage scales with oxide thickness and absolute

temperature and can be modeled as:

Vbd = atox + b/T + Vo

Typical values of a = 1.5 V/nm b = 533 V*K and Vo close to 0.

• Parasitic npn transistor formed between n-diffusion, p-type substrate and

n-well

• Parasitic pnp transistor formed between p-diffusion, n-well and

p-body

• Resistors are due to resistance through the substrate or well

• The only constant in VLSI design is

constant change

• Dennard’s Scaling Law

All dimensions (x, y and z)

Device Voltage

Doping Concentration densities

•Wires get scaled equally in width and

thickness to maintain an aspect ratio

close to 2.

•Uniform Random Variable

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•Normal Random Variable

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•Channel Length

•Threshold Voltage

•Oxide Thickness

•Layout Effects