Paper Report

Presenter: Jyun-Yan Li

Specification-based Compaction of Directed Tests for Functional

Validation of Pipelined Processors

Heon-Mo Koo Intel Corporation, 1900 Prairie City Road Folsom, CA 95630, USAPrabhat Mishra Computer & Information Science & Engineering ,University of Florida, Gainesville, FL 32611, USACODES+ISSS '08 Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis

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Functional validation is a major bottleneck in microprocessor design methodology. Simulation is the widely used method for functional validation using billions of random and biased-random test programs. Although directed tests require a smaller test set compared to random tests to achieve the same functional coverage goal, there is a lack of automated techniques for directed test generation. Furthermore, the number of directed tests can still be prohibitively large.

This paper presents a methodology for specification-based coverage analysis and test generation. The primary contribution of this paper is a compaction technique that can drastically reduce the required number of directed test programs to achieve a coverage goal. Our experimental results using a MIPS processor and an industrial processor (e500) demonstrate more than 90% reduction in number of directed tests without sacrificing the functional coverage goal.

Abstract

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Random and biased-random test program generation is widely used

Simulation-based validation in the design cycle Directed test generation has shorter tests in the same coverage

Directed test still large Multiple pipeline interactions reaches the target functional Test generation after compact This paper present FSM directed test generation

What is the Problem

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Related workFSM model

[2, 20]

Abstraction FSM model[3, 8, 13,15,

17]

Model checker[10, 11]

Produce test program

Static Test compaction

Architecture Description Language

(ADL)[12]

Specification-based Compaction of Directed Tests for Functional Validation of Pipelined ProcessorsThis

paper:

Remove unreachable &

redundant state

Complex FSM models, state explosion problem

Generated from the abstract FSM

Define processor’s

functionalities

Reduce unnecessary

state

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FSM modeling of pipelined processor Remove unreachable states Remove illegal transitions Remove redundancy state Test generation

Proposal method outline

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Modeling of FSM state Total number of state =

Modeling of FSM transition

Pipeline processor FSM model

Processor’s state Sk :

SS1 SS2 SSU

N bits

stall

stall

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Identifying unreachable states Pass instruction to either EX1 or EX2

State: xx0100xx or xx0001xx ,not xx0101xx

Compaction of FSM model

ID

EX1

EX2

EX1

EX2

Idle 00

Normal op. 01

Stall 10

Exception 11

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Table 1 State: xx0001xx -> xx0101xx , not xx0001xx

Table 2 State: xx01xx -> xx00xx or xx01xx or xx11xx , not xx10xx

Table 3 State: xx11xxxx -> xx0000xx

Identifying illegal stage transitions

IDEXE

ID EXE

normal

normal

ID

normal

normal

ID EXE

exceptionidleIDEX

Eidle

Idle 00

Normal op. 01

Stall 10

Exception 11

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Inevitable state Only one state in the next state list

Example。State: xx11xx -> xx00xx 。No need state : xx01xx, xx10xx

Identify redundancy

MEM

exception

idle

Idle 00

Normal op. 01

Stall 10

Exception 11

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Coverage-driven test selection StateCovered flag

。Initial = 0 TransitionCovered flag

。Initial = 0

Test generation

ID

idle

oper

stall

IF

IALU

SC

SC

SC

ns

TC

TC

ps

…

…

…

=0

=0

=0

=0

=0

=1

=1SC StateCovered flag

TC TransitionCovered flag

ps Previous state

ns Next state

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Multi-exception at clock cycle 7 overflow exception in IALU divide by zero exception in DIV memory exception in the MEM

Directed test generation [10]

Original property

Negated property

Decomposed into 3 sub-properties

Input source

Test program

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17 function units WB: 2 states IALU, DIV: 4 states Else: 3 states Total possible states =

Test compaction results for MIPS processor

Experimental result of MIPS

Remove unreachable state

Remove illegal state & redundancy

(87.2+376.3−16.9)/(87.2+376.3)

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Functional test compaction technique to reduce test program and achieve functional coverage

3 methods for compaction Identifying unreachable states Identifying illegal stage transitions Identifying inevitable state

My comment A idea for functional verification by the state FSM How to select test program to achieve 100% state and

transition coverage

Conclusion

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State coverage Visit every state m units, r states, total states

Transition coverage Visit every transition N states, maximum state transitions

Function coverage