Presto training course_1999

PRESTO 3.2 Training Course

Version 1.0 HDT proprietary

PRESTO 3.2 T

A I

N

G

I N

Version 1.0

May 1999

The contents of this training course are proprietary data of High Design Technology. Use or

disclosure of the information contained in this document is allowed only under written

authorization of High Design Technology.

High

Design

Technology

Copyright 1998 High Design Technology.

All rights reserved.



PRESTO History 1988 Development starting

1990 SPRINT & SIGHTS High perfomance simulation & modeling

1992 PRESTO Rel 1.1 Compliance analysis

1993 PRESTO Rel 1.2 + Crosstalk analysis

1994 PRESTO Rel 2.0 + SSN analysis + new GUI

1995 PRESTO Rel 2.1 + EmiR + THRIS integration

1996 PRESTO Rel 2.2 + EmiR-Cable + What-If Analysis

1997 PRESTO Rel 3.0 + ModEnv modeling+ IBIS interface

1998 PRESTO Rel 3.1 + Lossy lines and Modal method

1999 PRESTO Rel 3.2 + Net class propagation + New

error management

Introduction

i



PRESTO flow

Extract data

Setup libraries

Set simulation par.

Run simulation

View results

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Introduction

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PRESTO

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FILE_TYPE=HDT_PLIB;

TIME=Thu Dec 10 10:45:33 1992

COMPONENT=AC04, 74AC04;

FAMILY=FACT;

PACKAGE=DEFAULT, DIP14, SOIC14;

FACTORY=DEFAULT;

TYPE=IC;

NPINS=14;

BEGIN_PIN

FACT_DR24_P=2,4,6,8,10,12;

FACT_RC_P=1,3,5,9,11,13;

FACT_GND_P=7;

FACT_VCC_P=14;

END_PIN;

BEGIN_FUNCTION

DRIVER=2,4,6,8,10,12;

RECEIVER=1,3,5,9,11,13;

POWER_FACT=14;

GROUND_FACT=7;

END_FUNCTION;

END.

Driver

Receiver

SSN report

Compliance

analysis

report Overshoots

undershoots

rise and fall

time

report

Electrical models Physical models

Board layout data

Introduction

iii

398.00 399.00 400.00 401.00 402.00 403.00 404.00404.40

TIME[nS]

-2.00 V

-1.75 V

-1.50 V

-1.25 V

-1.00 V

-0.75 V

-0.50 VV(116)

70.00 80.00 90.00 100.00 110.00 120.00 130.00 140.00 150.00 160.00 170.00 180.00

-5.00V

-4.00V

-3.00V

-2.00V

-1.00V

0.00V

1.00V

2.00V

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4.00V

5.00V

6.00V

7.00V

8.00V

EMC

reports:Con

ducted and

radiated

emissions

What-If



Training course outline • PRESTO important concepts • CAD data extraction • PRESTO input format • Library Setup • Special Nets • Aliases setup • Signal stimuli creation • Signal mask creation • Net class definition • Simulation setup • Running simulation • Looking at simulation results • Output waveform postprocessor • Simulating crosstalk • Simulating Simultaneous Switching Noise (SSN) • Physical library • Electrical library • Performing What-If analysis (layout optimisation) • Performing EMI analysis

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PRESTO important concepts

• Design components

• Design nets

• Crossection

• Signal parameters

• Striplines

• Microstrips

• Reflections due to impedance mismatch

• Crosstalk noise

• Simultaneous Switching Noise (SSN)

• Physical models

• Electrical models


1-2



Design Components

Design components are physical devices of your design (resistors, capacitors, integrated circuits, connectors, etc). A component is characterized by:

– part name: specifies the type of device. This is the identifier used to search components in libraries

– instance name: more than one component having the same part name can be present in your design. The instance name identifies univocally the component.

– value: specifies the value of the component (if any). It is used for resistors, inductors and capacitors.

– pins: a component has one or more pins where design nets are connected

– package: it is the name of the component package. Different packages can have different electrical behaviors even if the part name is the same


1-3



Design nets

Design nets are physical interconnections (usually showing low DC resistance) between two or more pins of components implemented by metal traces.

– Net name is a name that identifies the entire net

– Special nets are power and ground nets

– Net segments are linear sections of the trace

– Vias are metalized through-holes used to connect net segments belonging to different layers of the crossection

– Bend a junction between two net segments defining a corner

– T-junction a junction between three net segments

– Sub-net a subsection of a net composed by one or more segments connecting two T-junctions or a T-junction with a pin or two pins.

A net can also be implemented by a metal plane


1-4



Crossection

is the geometrical/physical description of the transverse section of the board or MCM

y-direction traces

x-direction traces

metal plane

dielectric


1-5



Signal parameters

20%

80%

Overshoot

Undershoot

Rise edge Fall edge

Overshoot

Undershoot

0%

100%

Rise time Fall time


1-6



Stripline and microstrip

dielectric1

metal plane metal plane

conductor conductor conductor conductor

dielectric2

metal plane

metal plane

dielectric3

conductor

dielectric1

dielectric2

dielectric1

metal plane metal plane

conductor conductor conductor conductor

dielectric2

air

conductor

dielectric1

air

microstrips

striplines


1-7

Examples of:



Signal reflections due to impedance mismatch

Wave reflection occurs when the impedance at receiver or driver ends is not matched to the characteristic impedance of the line.

In this case, a percentage of the incident wave is reflected back and the same phenomenon happens at the other end of the line.

Reflections also occur when geometrical /physical discontinuities affect the interconnection (vias, bends, changing of layer).

Due to the complexity of the interconnection topologies and the non-linearities of drivers and receivers (V/I curve, clamping diodes), the effects of reflections on signals can be pratically analysed only through simulation.


1-8



Crosstalk Crosstalk is a phenomenon that occurs when two or more traces

(usually belonging to different nets) follow parallel paths. In this case, an edge travelling on one of the traces couples some of its energy to the others, causing noise (far-end and near-end crosstalk).

Crosstalk depends on both electrical (signal edge shape) and geometrical (coupling length and crossection) parameters.

The crossection of coupled structures is usually analyzed by means of a 2-D electromagnetic field solver.


1-9

propagating edge

disturbing line

victim line

near-end crosstalk far-end crosstalk



Simultaneous Switching Noise (SSN) This phenomenon is due to current pulses caused by switching drivers.

The current pulses, flowing through lines or parasitic inductances, causes an impulsive drop of voltage on the power supply rails. If several drivers switch simultaneously, this voltage drop can exceed the noise margins of nets at quiet state, causing undesired switching.

It is possible to distinguish two levels of SSN:

- Inside the component package: it is caused by the parasitic effects of the power supply pins of the package. It is difficult to control.

- Outside the component package: it is caused by the non-ideal power supply distribution on the board or MCM. It can be reduced by means of decoupling capacitors.


1-10

PRESTO allows the simulation of both causes of SSN noise

allowing the verification of decoupling capacitors

effectiveness .



Physical Model Describes:

– the pinout of the component package

– the function of the pin (driver, receiver, power supply, etc)

– the name of the electrical model to be utilized during the simulation

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FILE_TYPE=HDT_PLIB;

TIME=Thu Dec 10 10:45:33 1992


FAMILY=FACT;


FACTORY=DEFAULT;

TYPE=IC;

NPINS=14;

BEGIN_PIN

FACT_DR24_P=2,4,6,8,10,12;

FACT_RC_P=1,3,5,9,11,13;

FACT_GND_P=7;

FACT_VCC_P=14;

END_PIN;

BEGIN_FUNCTION

DRIVER=2,4,6,8,10,12;

RECEIVER=1,3,5,9,11,13;

POWER_FACT=14;

GROUND_FACT=7;

END_FUNCTION;

END.


1-11



Electrical Model – models the electrical behavior of driver/receivers

– uses the Spice-like syntax of SPRINT simulator

– model parameters can be extracted from datasheets, Spice simulations or measures (V/I curves or TDR)

Driver

Receiver

S_MODEL = RECEIVER;

DESCRIPTION = FACT receiver;

BEGIN_SUBCKT

*************** FACT RECEIVER MODEL ***********

* creation date: 19 Jan 1993

*

* maximum simulation time step: 100ps

* recommended simulation time step <= 50ps

* ideal logic output signal (0 1)

*********************************************

.SUBCKT FACT_RC 1 2 10 20

* in out VCC GND

E1 2 0 1 20 THR(2.5V 0 1)

RO 2 0 10MEG

CIN 1 0 4.5PF

PVCC 1 10 0V 0MA 0.55V 0MA 0.62V 0.1MA 0.74V 1MA 0.83V 5MA 0.87V 10MA

+ 0.9V 15MA 1V 40MA C=1P

PGND 1 20 -0.9V -50MA -.89V -20MA -.83V -10MA -.792V -5MA -.763V -2.5MA

+ -.731V -1MA -.69V -.3MA -.647V -.1MA -.6V -.02MA -.5V -.01MA 0 0 C=1P

.ENDS FACT_RC

*********************

END_SUBCKT


1-12



Training course outline

CAD data extraction

2-1

• PRESTO important concepts • CAD data extraction • PRESTO input format • Library Setup • Special Nets • Aliases setup • Signal stimuli creation • Signal mask creation • Net class definition • Simulation setup • Running simulation • Looking at simulation results • Output waveform postprocessor • Simulating crosstalk • Simulating Simultaneous Switching Noise (SSN) • Physical library • Electrical library • Performing What-If analysis (layout optimisation) • Performing EMI analysis

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CAD data extraction (1)

1. Execute extract command from the PRESTO user interface: Run->CAD Extractor

2. Locate the CAD files that have to be processed: the extractor will store the PRESTO files in the current working directory

CAD data extraction

2-2

.pnf file

.pgf file

.pxf file

.psf file



CAD data extraction (2)

• Supported CAD format are: – ALLEGRO (Cadence)

– BOARDSTATION (Mentor)

– SPECCTRA (CCT)

– VISULA (Zuken)

– THEDA (Incases)

– PADS (Pads Software)

– P-CAD (ACCEL Technologies)

• For further details please refer to the PRESTO User Manual

CAD data extraction

2-3




PRESTO input format

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PRESTO input format

• PRESTO input format is composed by four files:

– PRESTO Netlist File (design.pnf)

– PRESTO Geometric File (design.pgf)

– PRESTO Crossection File (design.pxf)

– PRESTO Copper Areas (design.psf)

PRESTO input format

3-2



PRESTO Netlist File (.PNF)

• Describes the component list and attributes

• Describes the net list and attributes

DEFAULTS

UNITS_PER_INCH = 1000;

END_DEFAULTS

SUMMARY

NUM_NETS = 22;

NUM_COMPONENTS = 17;

NUM_CONDUCTORS = 6;

END_SUMMARY

COMPONENTS

IC23 = 74AC04-2, PKG = SOIC14, XCMP = 6300, YCMP = 5400;

U4 = L20-1, PKG = DIP24_4, XCMP = 3200, YCMP = 6600;

.............

NET_DESCRIPTION

RESETN = IC24 1, U4 5;

RESET = IC24 2, U7 5;

............

END_NET_DESCRIPTION

END_BOARD

user unit declaration

design summary

component description

net connectivity description

PRESTO input format

3-3



PRESTO Netlist File (2)

Some attributes of the component list can be modified by the user:

• Choose Part Editor from Run

menu

• You can assign an alternate name

for both the part name and

package name to be utilized

during the search procedure in

library

• You can assign/modify the value

property of passive components

(R,L,C). Usually this parameter is

automatically extracted from the

CAD interface.

PRESTO input format

3-4

Note: To address names in library, it is suggested to use the ALIAS definition (see later) instead of

Alt.name and Alt.pack. Infact ALIAS definitions doesn’t change if a new CAD extraction is done.



PRESTO Geometric File (.PGF)

• Describes the physical topology of the nets

P_D: 37, 75, 80, 95;

V_D: 75;

WDH: 12, 50, 100;

NET: RESETN;

SEG: 0, 0, 5225, 5550, 5600, 5550;

VIA: 0, 5225, 5550;

CMP: IC24, 1, 0, 100000, 5600, 5550;

SEG: 0, 3, 5225, 5550, 3750, 5550;

SEG: 0, 3, 3750, 5550, 3675, 5625;

SEG: 0, 3, 3675, 5625, 3675, 6150;

SEG: 0, 3, 3675, 6150, 3575, 6150;

SEG: 0, 3, 3575, 6150, 3525, 6200;

SEG: 0, 3, 3525, 6200, 3200, 6200;

CMP: U4, 5, 1, 111111, 3200, 6200;

NET: RESET;

SEG: 0, 0, 5600, 5500, 5675, 5500;

SEG: 0, 0, 5675, 5500, 5700, 5525;

SEG: 0, 0, 5700, 5525, 5700, 6150;

types of pads

via diameters

trace widths

net name

net description in term of

vias, pads and segments

PRESTO input format

3-5



PRESTO Crossection File (.PXF)

• Describes the transverse section of the board or MCM substrate

INS: AIR,0,,1,0,0;

CND: COPPER,1.44,TOP,595900,1,0;

INS: FR-4,9.84252,,4.7,2,1;

SHL: COPPER,1.44,VEE,595900,3,1;

INS: FR-4,12,,4.7,4,2;

CND: COPPER,1.44,S1,595900,5,2;

INS: FR-4,12,,4.7,6,3;

CND: COPPER,1.44,S2,595900,7,3;

INS: FR-4,12,,4.7,8,4;

SHL: COPPER,1.44,GND,595900,9,4;

INS: FR-4,9.84252,,4.7,10,5;

CND: COPPER,1.44,BOTTOM,595900,11,5;

INS: AIR,0,,1,12,6;

conductor layer declaration

insulator layer declaration

shield layer declaration

(filled or grid metal plane)

Note: Some parameters of the crossection

(dielectric constant, layer thickness, etc) can be

modified. In this way it is possible to perform

WHAT IF analysis, running multiple simulations

with different parameters

PRESTO input format

3-6



PRESTO Copper Areas File (.PSF)

• Describes the copper areas of the board like power planes, partial or splitted metallization and so on.

3-7

Note:

Metal planes will be managed as a grid of lossy

transmission lines in Q2/99

PRESTO input format




Library Setup

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Library setup • Libraries (both physical and electrical) are organized in a database to insure a

fast search of models

• System libraries are shipped with the software and cannot be modified

• More than one electrical/physical library can be open at the same time

• Two additional levels (other than System library level) can be used to define libraries: User level or Group level.

system libraries paths

user/group physical libraries list

user/group electrical libraries list

Library Setup

4-2



Library priority

• During the model link phase, PRESTO begins the search of model

description starting from the user libraries sorted in the same

order they are listed in the window and then in the group and

system libraries respectively, if models are not found in lower level libraries.

• The Library Setup window (available within the Setup menu) allows the user to add library paths, delete them or change the priority.

Note: It is suggested to use group level libraries to define models or library

aliases that have general meaning inside a group of designers. For example,

the Group level library could contain the standard components available in

warehouse, while the user level libraries could be used to define aliases

or/and to contain models of semicustom ICs (design specific components).

Library Setup

4-3




Special nets

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Special Nets

• Special nets are power and ground nets

• Special nets can be: – distributed: wired power supply nets (implemented by metal

traces) are translated into transmission line equivalents as well as other nets.

– collapsed: the power supply net distribution is collapsed in one single electrical node. Metal planes of power supply are automatically collapsed.

• Special nets require a voltage value assigned

Special nets

5-2



Special net identification

• A net can be specified as Special in two ways:

– if the power supply net name is already known, you can setup directly this property by means of the commands available in the Net Editor window (available within the Test Control menu)

– The command Search Special Net is available in the Net Editor window: it uses the information stored in the physical libraries to identify nets that connect power and ground pins of components

Note: The voltage value associated to the special net must always be

specified by the user before running the simulation

Special nets

5-3



Special net management

During the simulation, the special nets are connected to electrical models of power supply:

• If the special net is collapsed in a single electrical node, the power supply model is connected to the node

• If the special net is distributed, the power supply model(s) is(are) connected in the network in correspondence of component pins with the property TYPE=GENPOWER (see physical models properties). If no pins have attribute GENPOWER, the special net is automatically turned to collapsed type

Note: The power supply model is a two pin electrical model (the second pin is

ground) and must be available in the electrical library . It can be described as an

ideal power supply (ideal independent voltage generator) or can include

parasitic effects as noise (ripple, burst, non-linear output resistance)

Special nets

5-4




Aliases setup

6-1


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Aliases

Aliases define equivalencies between two names of components or packages

• Different CAD environments can utilize different names for the same component (for example: DIP14, DIP14_4, DIP14CA)

• Different manufacturers can identify their components with a specific prefix/suffix (for example: 74AC08, SN74AC08)

• Designers sometimes utilize internal codes to identify component or package names (for example warehouse codes)

Aliases are used by PRESTO to identify a component of the library having a part

name that is not equal to the part name specified in the design netlist (.pnf file).

The same applies for package names.

Aliases setup

6-2



Aliases type

• Library aliases – can be defined for component names only. The alias definition

(netlist part name pointing to a library part name) is inserted in the same physical library where the pointed part name is stored

• Design aliases – can be defined for component or package names. The alias

definition is stored in a specific file (.ali) within the current directory and its validity is limited to the current design.

Aliases setup

6-3



Library aliases • Library aliases are stored in the same library of the pointed

physical model.

• From a user point of view, it is equivalent to create a new physical description of the component with a different name.

• Library aliases cannot point to another alias definition.

• Library aliases can be used from many designers at the same time (it is only necessary to link the physical library).

Part or package name of the

component in netlist


component in library

Design aliases menu is activated

through the command Alias

Manager-> Library Aliases available

within the Model menu

Aliases setup

6-4



Design aliases

• Design aliases can have only local meaning (current design)

• PRESTO first replaces the names specified in the netlist with the names pointed by the design aliases (creating a new key to access the physical library) and then starts the search in library


component in netlist


component in library

Design aliases menu is activated

through the command Alias

Manager-> Design Aliases from the

Model menu

Aliases setup

6-5




7-1

Signal stimuli creation


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Used to specify the switching time features of drivers during the simulation. A stimulus is characterized by:

– stimulus name (for example: stim1)

– binary bit sequence (for example: 10010110111)

– working bit rate expressed in Mbit/s (for example: 150)

The time of the single bit is

calculated as:

tbit (ns) =

1000

bit-rate (in Mbit/s) tbit


7-2



Stimuli Setup

Stimulus bit-sequence can be specified

directly or can be contained in an ASCII

file

it is possible to delete, modify or

create a new stimulus declaration

using the commands of the Stimulus

menu

Note: If the simulation time window is

longer than the stimulus duration, the bit-

sequence will be automatically repeated.


7-3



Stimuli LAB

• create the following stimuli declarations:

– a 50 MHz clock with 50% duty-cycle

– a 10 Mbit/s stimulus with bit-sequence 1011011

– a 20 Mbit/s stimulus with bit-sequence 110110101 specified in a file called filestim

– a 100 MHz clock with 20% duty cycle


7-4




Signal mask creation

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• Compliance analysis of signal is performed with respect to user-defined masks.

Possible shapes:

– Uniform masks

– PWL masks (Piece-Wise Linear)

• Masks are defined with respect to a reference signal

• Signals violating the masks during the simulation are reported in the .rep file


8-2



Uniform masks

• These masks are well suited to check noise amplitude on signals at fixed voltage values (power supply nets or victim nets during a SSN or crosstalk analysis)

• The signal voltage used as reference is specified in the net class definition.

• Only two noise margins (lower and upper) have to be defined

Upper Margin

Lower MarginReference value


8-3

added noise



PWL masks

• PWL masks are suitable to check integrity of switching signals

• PWL masks behaviors can be defined graphically by 4 shapes:

– Rising Upper edge (RU)

– Rising Lower edge (RL)

– Falling Upper edge (FU)

– Falling Lower edge (FL)

• PWL masks are defined: – by %

– by value

• It is always necessary to specify a maximum operating frequency

RL mask

RU mask

FU mask

FL mask

A

B

C

D

E

F

G

H

reference

y

t

bit-time bit-time


8-4



PWL mask defined by %

• The maximum working frequency specification is necessary to draw the mask shapes

• The reference signal ranges always between 0 and 1 (0-100%)

• In the net class definition (where the mask will be used) the user has to set the actual reference signal swing: the mask amplitude will be automatically scaled

These masks can be utilized for more than one net class declaration, because

their shape applies to whatever signal swing.

reference

y

t0%

100%

y

t

V2

V1

net class definition:

High_value = V1

Low_value = V2

as you define it as PRESTO actually simulates it


8-5



PWL mask defined by value • The maximum working frequency specification is necessary to

draw the mask shapes

• The reference signal swing is user-defined

• The net class definition utilizing a PWL mask defined by value will set the actual reference signal swing to the value specified in the mask: the mask amplitude will not be scaled in this case

These masks can be utilized to check signals with well specified noise

tolerances.

y

t

V2

V1

net class definition:

swing value are

defined by the mask

as you define it as PRESTO actually simulates it

y

t

V2

V1


8-6



Mask shape definition (1)

Mask name

maximum working frequency: a

mask can be used to check signals

switching at a bit rate lower or equal

to the maximum working frequency

click here to start the shapes creation of a

new mask

click on these buttons to modify a

specific mask shape

By % or By value selection


8-7



Mask shape definition (2)

As example, the procedure to create a RU shape is shown:

0.00 1.00 2.00 3.00 4.00 5.00 6.00 7.00 8.00 9.00 10.00

TIME[nS]

-1.00 V

-0.50 V

0.00 V

0.50 V

1.00 V

1.50 V

2.00 V

0.00 1.00 2.00 3.00 4.00 5.00 6.00 7.00 8.00 9.00 10.00

TIME[nS]

-1.00 V

-0.50 V

0.00 V

0.50 V

1.00 V

1.50 V

2.00 V

0.00 1.00 2.00 3.00 4.00 5.00 6.00 7.00 8.00 9.00 10.00

TIME[nS]

-1.00 V

-0.50 V

0.00 V

0.50 V

1.00 V

1.50 V

2.00 V

1) The reference rising

waveform will be displayed:

the marker of the starting point

is forced to move only on the Y

axis.

2) A mask segment is defined by

positioning the marker on the

chosen point and by pressing the

left button of the mouse; now the

marker can only move at the right

of the selected point and a

hairline will connect the marker

with this point.

3) This procedure is repeated

during the selection of the

other breakpoints. The total

number of breakpoints can

range between 3 and 20. After

choosing the last point, click

on the right button of the

mouse to exit.


8-8



Masks LAB

create the following Mask definitions:

– a uniform mask to check 5V power supply signals with 5%

tolerances

– a PWL mask by percentage with:

» max working frequency = 10Mbit/s

» noise tolerances on steady state values = 10% swing

» noise tolerances for overshoots = 20% swing

» other parameters are free

– a PWL mask by value for CMOS signals with:

» max working frequency = 20Mbit/s

» noise tolerances = 1.25V (reference signal= 0-5V)

» max delay allowed = 3ns


8-9




Net class definition

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Net Class definition A Net Class defines a set of parameters that will be utilized to

check signals during the simulation:

– the stimulus assigned to the driver

– the mask used to check the signal

– the reference values used to scale and shift uniform or PWL signal masks

– the delay time of the stimulus before starting the signal checks (to allow the setup of the start-up transient)

t

stimulus td

t

mask generator

net driver

net under analysis

rec. 1

rec. 2

rec. n

mask violation

t

V2

V1

10

10

RESULTS

checker

td

WARNING:

The working frequency of the

used stimulus within a net

class definition cannot

exceed the maximum working

frequency of the signal mask.


9-2



Net Classes application

• to check quiet nets (like power supply nets, victim nets during a xtalk or SSN analysis)

– the mask type is Uniform

– the first bit of the stimulus assigned to the class specifies the steady state level for victim nets (it has no meaning for power supply nets)

»01101101 “0” logic state

»11101100 “1” logic state

• to check switching nets – the mask type is PWL (by % or by value)

– the bit sequence is applied to the driver as specified by the stimulus definition


9-3



Net Class reference values

• for Uniform masks, the two values have to be identical and specify the absolute voltage value to be applied to check noise amplitude on quiet nets .

• for PWL by % masks, the two values are used to scale the mask parameters (amplitude only) during the simulation.

• for PWL by value masks, the two values are automatically set to the masks reference signal values.

reference values


9-4




Simulation setup

10-1


1

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13

14

15

16

17

18

19



Simulation setup

1) set library paths and aliases

2) Identify power supply nets and set their voltage values

3) assign class to nets

4) set simulation parameters

Before running a simulation follow these steps:

Simulation setup

10-2



Set library paths and aliases

• System libraries are automatically set by means of the environment variable HDTTOOLS

• Physical and electrical libraries must be selected by the user through the Library Setup window.

• Aliases (both library and design) must be specified. If all components already have the right name in library, the alias setup is not required.

If one or more components are not identified during the

simulation, an error occurs:

“Error: physical models missing in library”

Simulation setup

10-3



Identifying missing components

If some components are missing in library, the .log file will report their names:

part-name, package name

and factory as specified

in the netlist

part-name, package name and factory

name used to search in library (design

aliases are applied before the search

starts)

component that has been found in library:

component that has not been identified:

“Component 100125-1 PDIL24_4 Default found as 100125 DIP24 Default in library mylib.plb”

“Warning: Component 100124-1 PDIL24_4 Default searched as 100124-1 DIP24 Default not Found!”

library name

Possible actions:

• create a physical description of the component or

• define an alias or

• utilize the default model facility.

Simulation setup

10-4



Default model facility

If some components are not described in library,a list of their pins is created. You can assign default I/O driver or receiver models (TTL, CMOS, ECL, Low voltage) to each pin of the missing component list using the Default Model Editor window without the definition of a new specific physical model.

Note: Remember to set the

“Default Models”button in the

Simulation Setup window before

running the simulation again

Simulation setup

10-5



Special nets

Special nets can be identified by the user or by means of the “Search Special Nets” command available on the Net Selector window.

This command utilizes the information contained in the physical

library to identify the nets connected to power and ground pins of

components. In order to work properly, it is required to set the

libraries paths before running the Search Special Nets command.

In any case, you must specify the voltage

value and the collapsed/distributed property

for each special net.

Simulation setup

10-6



Net Class assignment

• A Net Class specifies the type of analysis to perform on the net.

• Any net must have a net class assigned before running the simulation.

• A default class is automatically set for the nets without a specific class assigned by the user.

• A class can be assigned:

– by the user using the Net Editor window;

– automatically using the command “Automatic Net Class Assignment” available under the Nets Attributes menu of the Net Selector window. In this case, the default net classes associated to the drivers in the physical libraries will be assigned to the nets. In order to work properly, it is required to set the libraries paths before running the Automatic Net Class Assignment command.

Simulation setup

10-7



Basic simulation parameters setup Specify the use of default models for

components not available in library

Xtalk, SSN switches: enable these two

types of analysis

Resolution of the graphical output waveforms: 300-1000 samples give a good

resolution in normal situations. This number must be increased to maintain a

good resolution in case of zoom or eye-diagram plots. In this case the output

file can be very large.

Simulation time step: a value between 10 and 100

(ps) is suggested for normal situations

The simulation time window can be automatically

evaluated on the basis of the lengths of the bit-

sequences assigned as stimuli to the drivers or can

be selected by the user

Simulation setup

10-8

Enable the simulation of

the modifications made

with the What-If tool




Running simulation

11-1


1

2

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5

6

7

8

9

10

11

12

13

14

15

16

17

18

19



Running the simulation To start the simulation choose the command Run Simulation from

the Run menu.

– phase 1:

» translates the physical data of layout traces into transmission lines,

» checks that all physical models are included in library,

» calls the EM field solver if crosstalk analysis is activated

– phase 2:

» imports in the netlist the electrical models (with its right package model),

» sets simulation parameters

– phase 3:

» SPRINT executes the transient simulation of the design,

» produces the output file

Errors are stored in the prerr.err file (simulation phase) and

uierr.err (user interface). Messages and warnings are stored in the .log file.

Running simulation

11-2




Looking at simulation results

12-1


1

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3

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5

6

7

8

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13

14

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19




• Compliance analysis ASCII report file

• Graphical analysis with SIGHTS – plot, mplot, plot_by_net, etc

– eye diagram (for Unix-based workstations only)


12-2



Compliance analysis report file

** COMPLIANCE ANALYSIS REPORT **

Design name: tutorial

Net name Upper mask Lower mask I ntegrated Violation

Violation Violation Error

------------------------------------------------------------------------------------------------

VCC * 10.972890

RESET * 1.485747

DATA * 1.484746

RESETN * 1.483746

------------------------------------------------------------------------------------------------

DATA1 * 1.483746

PULLUP * 1.060050

PULLDOWN * 0.705617

FANIN * 0.390969

------------------------------------------------------------------------------------------------

VEE

OUTECLP1

GND

OUTECLM1

• Lists the nets not passing the

compliance analysis test (masks

violations).

• The check is performed on

receiver pins only.

• The file reports the mask that has

been violated (upper or lower) and

prints a number representing the

total integrated violation error


12-3



Graphical analysis

• Waveforms can be displayed with SIGHTS

• Activated by the command: View->results->Graphical it allows the plotting of waveforms

• The following description refers only to particular functions of SIGHTS suitable for S.I. Analysis

• For Unix based workstation there is an other old (no XVT based) version of Sights (Run->Sights) that allows a larger number of functionality. For a general description please refers to “SIGHTS User Manual


12-4



Waveforms can be referred by component/pin_name or by the

net_name they belonging. The related netclass masks can be

added to the display. Background can be white or black. An

“EVAL” function that allows you to display waveform values is

available.

70.00 80.00 90.00 100.00 110.00 120.00 130.00 140.00 150.00 160.00 170.00 180.00

TIME[nS]

-5.00V

-4.00V

-3.00V

-2.00V

-1.00V

0.00V

1.00V

2.00V

3.00V

4.00V

5.00V

6.00V

7.00V

8.00V#U4_1

#MASKdefaultcmos_L

#MASKdefaultcmos_U

#IC23_4

Plot and Plot by net (new Sights)

12-5



Plot and Plot by net (old Sights)

Single waveforms can be plotted with the command:

“Plot <testpoint list>“.

The command Plot by net (“Plot -n <netname list>“) plots all the

testpoints of a net with the related masks

70.00 80.00 90.00 100.00 110.00 120.00 130.00 140.00 150.00 160.00 170.00 180.00

TIME[nS]

-5.00V

-4.00V

-3.00V

-2.00V

-1.00V

0.00V

1.00V

2.00V

3.00V

4.00V

5.00V

6.00V

7.00V

8.00V#U4_1

#MASKdefaultcmos_L

#MASKdefaultcmos_U

#IC23_4


12-5bis



Eye diagrams (old Sights only)

Eye diagrams are obtained by superimposing all the time frames

of a bit sequence. This function is very useful to check jitter and

intersymbol interference. Usually, this function requires the

definition of stimulus signals with long bit-sequences.

398.00 399.00 400.00 401.00 402.00 403.00 404.00404.40

TIME[nS]

-2.00 V

-1.75 V

-1.50 V

-1.25 V

-1.00 V

-0.75 V

-0.50 VV(116)


12-6



Other useful functionalities of SIGHTS (Old Unix version only) • Multiplot

Plots each waveform in a dedicated section of the graphic window

• Scanplot

Plots sequentially all the waveforms of the graphic file net by net

• XY Plot

Can use the samples of a waveform as X-axis

• Waveform cursors

Displays the numeric values of the waveform through a couple of cursors

• Zoom Enlarges sections of the graphic window

• Piece-Wise Linear (PWL) extraction A set of selected samples can be extracted from a waveform and saved on a PWL file

• Measurement instrument interfaces

Allows the acquisition of measured waveforms (DSO, TDR) to be compared with simulations or used to build up behavioral models through PWL extraction.

• Mathematical functions

All typical mathematical operations can be performed on waveform samples


12-7




Output waveform postprocessor

13-1


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16

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19



Output waveform postprocessor (1)

Overshoots, undershoots, rise and fall times can be extracted from the graphical output file

Design: xxxxxxxx

Number of samples: 1000

Time Step: 2.6e-10

--------------------------------------------------------------------------------

Net: /A(1) Class: defaultcmos

Part Pin Rise Fall Rising Rising Falling Falling

Time Time Edge Edge Edge Edge

Ovsh Udsh Ovsh Udsh

(ns) (ns) (V) (V) (V) (V)

IC6 5 8.190 5.704 5.396 4.904 -0.459 0.402

IC9 9 8.219 5.675 5.417 4.850 -0.447 0.410

IC3 9 10.042 7.299 5.510 4.743 -0.436 0.452

IC6 9 8.141 5.637 5.407 4.897 -0.463 0.408

IC2 1 8.561 5.976 5.353 4.861 -0.431 0.419

--------------------------------------------------------------------------------

All the testpoints parameters can be

displayed or filtered in order to store

only the testpoints that violate the user-

defined value.


13-2



1) Run the simulation with graphic output as option

2) Set the parameters in the Wave postprocessor window

3) Click on Run

4) View result

Output waveform postprocessor (2)


13-3



Pin-to-Pin delay

• Activated by View->Delay Report

• Evaluates the propagation delay between the driver and the receivers.

• Four values are given: two for the rise edge and two for fall edge.

• For each edge the maximum/minimum delay are evaluated (related to Vil and Vih threshold crossing)

13-4

Vil

Vih

VOmin

VOmax

Threshold

unloaded driverloaded driver

receiver

tdd

tdmin

tdmax

tdm

driver stimulus




Simulating crosstalk

14-1


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14

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16

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18

19




• Check for noise between two or more parallel traces (coupled lines)

• Coupled lines can belong to different layers

• Crosstalk simulation can be added to SSN analysis

• Compliance checks can be performed on signals affected by crosstalk noise

• Losses can be taken into account


14-2



Crosstalk analysis flow

1 2 3

10 20 30

1 2

3

10 20

30

1

2

3

10

20

30

unbalanced TL

balanced TL

1

2

20

t

t

t

• Coupled structures are identified

scanning the design using geometrical

filters specified by the user

• Coupled structures are composed by

parallel traces with any orientation.

• Up to 32 parallel traces can be simulated

for each layer. Up to 4 layers (between

two metal planes) can be taken into

account simultaneously.

• The EM field solver (PREFIS) evaluates

the coupling parameters.

• A transmission line model based on Marx

method (striplines) or modal method

(microstrips) is created and included in

the netlist.

• The victim net is selected.

• The simulation is performed


14-3



Extracting coupled structures

• Coupled structures are extracted by means of an exhaustive geometrical analysis of the routing. Three parameters can be specified:

– mininum length: specifies the minimum length of a coupled segment to consider during the search

– maximum distance: specifies the maximum distance between two parallel segments to consider during the search

– resolution: is the minimum length of a coupled section to be considered significant during a crosstalk simulation


14-4



Crosstalk structures

Min Length = 50 mm Max Distance = 2 mm Resolution = 5 mm

PARAMETERS SETUP:

8015

20

4 4

Net 5

Net 1Net 2

Net 3

Net 4

xtk 1xtk 2

xtk3

Primary structure

(length > Min Length) Secondary structure

(length < Min Length

length > Resolution)

Discarded structure

(lenght < Resolution)

• A primary structure is a coupled section of length > Min Length.

• A secondary structure is a coupled section of length < Min Length that is the

continuation of a primary structure or other secondary structures.

• All secondary structures of length < Resolution are discarded.

• A structure can be neglected be the user (Action->Delete Xtalk)


14-5



Victim nets • Optionally, during the analysis, a selected net (victim net) is held at

quiet state while the others (disturbing nets) switches. This can be specified for each structure of the list in two ways:

– one by one manually

– automatically by the program (the selected net is in the middle of the structure)

• The quiet state can be a logic “0” or “1” depending on the net class assigned to the victim net.

victim net

selection. NONE

selection means

no victim net (to

be used for

differential

pairs)

net class

assigned to the

victim net

(NONE for

differential

pairs


14-6



Electromagnetic Field Solver

• The PRESTO electromagnetic field solver (PREFIS) utilizes the method of moments and returns the LC matrices of the coupled structures.

• Each Stripline structure (with homogeneous dielectric) is then converted in a transmission line equivalent subcircuit by means of the Marx method.

• Each Microstrip structure is then converted in an equivalent subcircuit by means of the multimodal decomposition.

• The structures analyzed are stored in a special database (one for each design) and are available for further simulations to skip further calculations.


14-7



Running crosstalk analysis

• Run the Crosstalk Preprocessor with the specified geometrical filters

• Choose the victim nets and assign net classes to them (optional)

• Set Xtalk analysis button in Setup Simulation menu

• Run the simulation


14-8

Note: the user is allowed to not assign the victims during the crosstalk analysis. In

this case the models of the interconnections will take in to account the crosstalk, but

all the signals will be switching. This can be useful, for example, when a couple of

balanced differential lines are analyzed.



Crosstalk analysis results

• Results can be obtained in ASCII or graphical way, according to the setup of the simulation setup menu

– if the setup is ASCII: the results are available in the .rep file as masks violation reports

– if the setup is graphical: the results can be displayed with SIGHTS as waveforms

t


14-9




Simulating SSN

15-1


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19



SSN analysis

• Check for noise caused by drivers switching simultaneously.

• Noise affects both drivers held at quiet state and receivers thresholds.

• SSN macromodels are automatically built up by means of the physical model descriptions.

• SSN analysis is fully compatible with crosstalk checks.

Simulating Simulating SSN

15-2



SSN analysis flow

t

t

t

• SSN macromodels of ICs are built up

automatically starting from library model

description.

• A common package model is

automatically inserted into the IC model.

(RLC, Transmission Line or S-parameters

models are allowed)

• Switching drivers are connected to their

actual interconnection topologies.

• Quiet drivers are set to “0” or “1” logic

level.

• The noise caused by the switching outputs

affects also the behavior of the clamping

diodes of receivers belonging to the same

package.

• Clamping diode currents of receivers

affect the behavior of other

drivers/receivers belonging to the same

package.

1 2 3 4 5 6

7 8 9

FILE_TYPE=HDT_PLIB;

TIME=Thu Dec 10 10:45:33 1992


FAMILY=FACT;


FACTORY=DEFAULT;

TYPE=IC;

NPINS=14;

BEGIN_PIN

FACT_DR24_P=2,4,6,8,10,12;

FACT_RC_P=1,3,5,9,11,13;

FACT_GND_P=7;

FACT_VCC_P=14;

END_PIN; BEGIN_FUNCTION

DRIVER=2,4,6,8,10,12;

RECEIVER=1,3,5,9,11,13;

POWER_FACT=14;

GROUND_FACT=7;

END_FUNCTION;

END.

gnd1 package pins

power1 package pins power2 package pins

input output

on-chippower1 net

on-chip gnd1 net

on-chippower2 net

on-chip gnd2 net

gnd2 package pins

... ...

......

supply pin models

supply pin models

modelsmodels

Simulating SSN

15-3



Percentage of switching drivers (1)

How many drivers switch simultaneously for each component?

This number is usually very difficult to set in case of large

components: • for simple components (e.g. AC244) the assumption is very easy: the worst case is

obtained with all drivers switching except one that is set at quiet state.

• for complex components having, for example, more than one output bus, the actual

timing of the design becomes very important and the percentage of switching drivers

is different for each component. Normally, the previous rule (all drivers are switching

except one) cannot be applied, because the number of power pins of large

components is usually not designed on the basis of all driver switching assumption:

This hypothesis can be too pessimistic.

Simulating SSN

15-4



Percentage of switching drivers (2)

PRESTO allows two approaches: a) rough simulation:

a fixed percentage of switching drivers is assigned to component packages

b) accurate simulation:

1) select a time window on a logic simulation already performed on the design.

2) utilize the bit sequences obtained as output of the logic simulation to set PRESTO signal stimuli and related net classes.

3) assign the classes to the nets

4) simulate a Real Timing Simulation: the percentage of switching drivers will be the real one.

Note: automatic interfaces between your logic simulator and

PRESTO can be easily implemented.

Contact HDT for more information about Real Timing Simulation

Simulating SSN

15-5



Running SSN analysis

• Set SSN button in the Simulation Setup window

• Set the SSN parameters: percentage of switching drivers (100% in case of Real Timing Simulation) and quiet state net class

• Run the simulation

Simulating SSN

15-6



SSN report

• The drivers to be set quiet are automatically chosen by the system in a random way. The report file (.brep) reports the configuration utilized for the simulation.

*** Simultaneous Switching Noise Report ***

Design name: xxxxxxx

--------------------------------------------------------------------------------

Pin name Net name Status Class

--------------------------------------------------------------------------------

Instance IC21 Component 74AC04 package DIP14 factory DEFAULT

2 /A(1) ACTIVE defaultcmos





12 /A(6) VICTIM defaultgnd

--------------------------------------------------------------------------------

...

...

Switching nets: net classes are

set by means of the Net Editor

window .

Quiet net: net class is a parameter of

the SSN setup and overrides the net

class assigned by means of the Net

Editor window during the SSN analysis.

Simulating SSN

15-7



SSN results

• Results can be obtained in ASCII or graphical way, according to the setup of the simulation setup menu

– if the setup is ASCII: the results are available in the .rep file as masks violation reports

– if the setup is graphical: the results can be displayed with SIGHTS as waveforms

t

Simulating SSN

15-8




Physical library

16-1


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10

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13

14

15

16

17

18

19



Physical library

• Contains the physical model descriptions.

• Data base organized.

• Component creation and library management fully supported by the PRESTO graphical interface.

• Support different component pinout description associated to different package pinouts

Note: a component can be available in different packages. The pinout

of these can be different, so that more than one physical model can be

required for the same component. PRESTO searches the component in

the library data base using a key composed by the component and the

package name, so that the model can be correctly identified.

Physical library

16-2



Physical Model Describes:

– the pinout of the component package

– the function of the pin (driver, receiver, power supply, etc)

– the name of the electrical model to utilize during the simulation

1 2

3 4

5 6

7 8

9

FILE_TYPE=HDT_PLIB;

TIME=Thu Dec 10 10:45:33 1992


FAMILY=FACT;

PACKAGE SOIC14;

FACTORY=DEFAULT;

TYPE=IC;

NPINS=14;

BEGIN_PIN

FACT_DR24=2,4,6,8,10,12;

FACT_RC=1,3,5,9,11,13;

FACT_GND=7;

FACT_VCC=14;

END_PIN;

BEGIN_FUNCTION

DRIVER=2,4,6,8,10,12;

RECEIVER=1,3,5,9,11,13;

POWER_FACT=14;

GROUND_FACT=7;

END_FUNCTION;

END.

Physical library

16-3



Physical model types

• Resistors, capacitors, inductors, diodes

• Integrated circuits

• Programmable logic devices

• Connectors

• Special components

Physical library

16-4



Physical model definition

The model description is done by means of the Physical Model Editor window. The resulting description can be saved directly in the physical library or exported in a file having the Physical Model Description format (ASCII file with .pmd extension)

Model parameters (library,

component name, pin number

and packages list)

Model description

Physical library

16-5



Physical Model Description format (PMD) FILE_TYPE=HDT_PLIB;

TIME= xxxxxxxxxx

COMPONENT=component_name;

FAMILY=xxxxxxxx;

PACKAGE=xxx;

FACTORY=DEFAULT;

TYPE=xxxxx;

NPINS=nn;

BEGIN_PIN

model_name=pin_list;

END_PIN;

BEGIN_FUNCTION

function_name=pin_list;

END_FUNCTION;

BEGIN_POWER

power_name=pin_list;

END_POWER

BEGIN_CLASS

net_class_name=pin_list;

END_CLASS;

BEGIN_DR_LIST

driver_list;

END_DR_LIST;

BEGIN_VSET

voltage_value=pin_list;

END_VSET;

END.

Header

pin to electrical_model assignment

pin function (Driver, Receiver, Bidirectional, etc)

pin to power pin association: describes which

power/ground pin powers the other functions (driver,

receiver, etc) pins

default net class to pin assignment (not mandatory)

driver list (only if bidirectional, 3-state or open collector

functions are present in the model)

power supply voltage assignment (connectors only)

Physical library

16-6



R,L,C, Diodes

• These are two-pin models

• Only one electrical model can be associated to the physical models

1 RECEIVER myresistor

2 RECEIVER myresistor

RES

DEFAULT

R 2

RES is the name of the

physical component

Default is the package

type for which

the model applies

“R” is the TYPE that applies

for resistors

The description requires the

pin name, the function

(always RECEIVER for these

components) and the name of

the electrical model (myresistor

in this case).

Physical library

16-7



Integrated circuits

• One electrical model has to be assigned to each pin of the component functioning as DRIVER or RECEIVER.

• Two electrical models have to be assigned to each pin functioning as BIDIR, 3STATE, OPCOL (one driver and one receiver models).

• An electrical model must be assigned to each pin functioning as POWER. This model is utilized during the analysis of the special nets (power and ground nets) behavior.

Physical library

16-8



Example of IC description

1 RECEIVER ac_rc vcc gnd

2 RECEIVER ac_rct vcc gnd

3 DRIVER ac_dr8 vcc gnd

4 BIDIR ac_bd8 ac_rc vcc gnd

5 POWER vcc_mod vcc

6 POWER gnd_mod gnd

7 POWER gnd_mod gnd

8 ...

9 ...

MYIC

DIP14

IC 14

pin 1 has function RECEIVER, the electrical model to utilize is

“ac_rc” and the power pins of the electrical model must be

powered through the pins 5 and 6 (the package model will be

automatically connected).

pin 3 has function DRIVER and the electrical model to utilize is

“ac_dr8” (8mA driver in this case).

pin 4 is bidirectional, so two electrical models must be

specified: one will be used when pin 4 acts as DRIVER and the

other one when the pin acts as RECEIVER.

pins 5 and 6 are power and ground pins. They have a power

electrical model associated and a power name (vcc for pin 5

and gnd for pin 6 in this case)

1

2

3

4

5

6

7 8

9

1 0

1 1

1 2

1 3

1 4

v c c

g n d

(the package model is

not shown)

Physical library

16-9



Programmable Logic Devices (PLD)

• Their I/O description is not fixed but design dependent (driver and receiver configuration is programmable).

• The same design can contain more than one PLD device having identical part name but different pin configuration (a different instance name of course)

• The description is similar to IC description but the component name must contain the design and the instance name with a special syntax.

part_name@instance_name@design_name

ex: IDTxxx@IC21@MYDES

Only the first 5 characters of the design name are necessary.

Physical library

16-10



Connectors (CON)

• Like PLD, the connector configuration is design dependent

• While the previous models describe the drivers and receivers inside the design, connector models allow the description of drivers and receivers outside the design and their interconnection to the circuitry inside the design under test.

• If the external connections are known, connector models allow you to accurately simulate also the behavior of the interface interconnections.

• If the external connections are unknown, the description of this model can be avoided using the Default Models

Physical library

16-11



Connectors (2)

• Specific electrical models can be utilized to take into account the actual external interconnections of driver/receiver.

design under test

connector

physical

model

standard driver or

receiver

Special driver or receiver

with its actual

interconnection description

(RLC, TLM, behavioral, ...)

Physical library

16-12



Connectors (3)

• The component name of connectors is specified like that of PLD devices (design-dependent components)

part_name@instance_name@design_name

e.g.: CONN5PIN@IP21@MYDES

Only the first 5 characters of the design name are required.

• One additional section of the description is utilized to specify the power and ground supply of driver/receivers models. In this way, it is also possible to simulate ground voltage shift between the design under test and the external circuitry and its effects on signal integrity.

Physical library

16-13



Example of connector model

1 RECEIVER ac_rc 5 0

2 RECEIVER ac_rct 5 0

3 DRIVER ac_dr8 5 0.2

4 BIDIR ac_bd8 ac_rc 5.2 0

5 GENPOWER vee -4.5

6 GENPOWER gnd 0.0

7 ...

8 ...

9 ...

CON15@J1@TUTOR

CONN15PIN

CON 15

pin 1 is connected to a RECEIVER, the electrical model to

utilize is “ac_rc” and its power pins are connected to a 5/0V

power supply.

pin 3 is connected to a DRIVER and the electrical model to

utilize is “ac_dr8” (8mA driver in this case). The power pins

are connected to a 5/0.2 power supply

pin 4 is bidirectional, so two electrical models have to be

specified: one will be used when pin 4 acts as DRIVER and the

other one when the pin acts as a RECEIVER.

pins 5 and 6 are power and ground supply pins (GENPOWER

function). They have a power supply electrical model

associated and a supply voltage.

1

2

3

4

5

1 5

- 4 . 5 V

p o w e r n e t

d e s i g n

u n d e r

t e s t

e x t e r n a l

w o r l d

c o n n e c t o r

g r o u n d n e t0 V

6

5 V

0 V5 V

5 V

5 . 2 V

0 V

0 V

0 . 2 V

Vset+ Vset-

Physical library

16-14



Special components

• These models describe the component as a black box, and their internal structure is described by a SPRINT netlist without explicit driver/receiver declaration. The number of pins of the physical description must match that of the related electrical model.

• SC modeling allows wide flexibility in modeling of the internal functionality of the device. For example, it is possible to build up models taking into account logic and timing behavior of the core of the device (see Electrical library section).

Physical library

16-15



Library management

• To insert a model in library: – Create a model description.

– Choose Save in Library specifying:

» the target library

» the component name

» the package name

– If the library doesn’t already exist, a new one will be created.

• To extract a model from library: – Choose Load Component Data specifying:

» the target library

» the component name

» the package name

– The model will be then displayed in the Model Editor window.

Physical library

16-16



Importing and exporting models

• To import a model from an ASCII file (PMD syntax): – Select the Import command and specify the file to load.

– The model description will be loaded in the Component Editor window.

• To write a model on an ASCII file (PMD syntax): – Select the Export command and specify the output file name.

– The model description will be saved on the specified file.

16-17

Physical library




Electrical library

17-1


1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19



Electrical library

• Contains the electrical model descriptions

(driver, receiver, passive components, etc).

• It is organized as a data base.

• Library management is fully supported by the PRESTO graphical interface.

• Model architecture is fully user-definable

• Models are MODENV compatible

Electrical library

17-2



Modeling capabilities

• The models are described as .SUBCKT circuits in SPRINT syntax.

• The model architecture is user-definable.

• A set of default architectures is available for typical situations.

• All SPRINT primitives can be utilized within the model and in particular:

– resistors, inductors, capacitors;

– non linear resistors

– time/voltage/current controlled resistors (switches)

– independent or voltage/current dependent sources

– dynamic or static transfer functions

– transmission lines

– time domain scattering parameters (including measure-based data).

• PRESTO allows the definition of hierarchical modeling (max. two nesting levels).

Electrical library

17-3



Model types

• Driver/Receiver – 4-pin models

– Suitable for ICs/PLDs/CONNECTORS I/O descriptions

– Selectable package

• R,L,C,Diodes, nonlinear resistors, voltage generators – 2-pin models

– Suitable to model 2-pin passive components, IC power pins (to simulate the behavior of supply nets, voltage power supply, etc)

• Special Components (SC) – n-pin (n >= 1) models.

– utilized to model the behavior of a whole device, for example a resistive array or an operational amplifier.

– allows the creation of complete electrical/logic/timing descriptions of simple components.

Electrical library

17-4



Receiver Model

sources,passive elem.,measures,

power node

ground node

input node at "analog"

"logic" levels"0" and "1"

0

1

output node atelectrical levels"V1" "V2"

V2

V1

etc

Input pin is automatically

connected to its external net

and acts as an electrical

load

Output pin provides a

digital signal (0 1)

obtained by an internal

threshold

Power and ground pins are

automatically connected to

the power and ground nets

supplying the device. component

power rail

ground rail

Electrical library

17-5

package



Example of simple CMOS receiver model

in

out

vcc

gnd

Cin

STF

Pvcc

Pgnd

1

210

20

E1

.SUBCKT name 1 2 10 20

CIN 1 0 value

PVCC 1 10 vcc_static_char C=1P

PGND 1 20 gnd_static_char C=1P

E1 2 0 1 20 THR( 2.5 0 1 )

.ENDS name

name is the name identifying the electrical model in the Sprint netlist,

value is the value of the input capacitance,

vcc_static_char is the static characteristic of the vcc clamping diode and

gnd_static_char is the static characteristic of the gnd clamping diode.

Usually, the static characteristic of the diode is expressed as a Piece Wise Linear fitting of its

actual V,I characteristic.

Electrical library

17-6



Driver model

sources,passive elem.,measures,

power node

ground node

input node at"logic" levels"0" and "1"

0

1

output node at "analog"electrical levels"V1" "V2"

V2

V1etc.

component

power rail

ground rail

Output pin is

connected to its net

and acts as a

generator

Power and ground pins are

automatically connected to

the power and ground nets

supplying the device.

Input pin is used by

Presto to connect the

driver to a digital

stimulus (0-1 levels) that

defines the switching

sequence

Electrical library

17-7

package



Example of CMOS driver model

out

vcc

gnd

Cout

2

10

20

Pvcc

Vcomp

E1

RSWvcc

+

+

Pgnd

RSWgnd

+E0

Td

STF

STF DTF

DTF

1

in

SUBCKT name 1 2 10 20

COUT 2 0 value RSWVCC 7 2 1 0 PWL(0V 1E6 1V 0 2V 0) C=2P

PVCC 7 8 1_static_char C=2P

E1 8 9 1 0 dtf stf 0.1NS

VCOMP 10 9 DC(5)

RSWGND 17 2 1 0 PWL(-1V 0 0V 0 1V 1E6) C=2P

PGND 17 18 0_static_char C=2P

E0 18 19 1 0 dtf stf 0.1NS

TD 19 20 C=6P

.ENDS name

name is the name of the electrical model within the Sprint netlist,

value is the value of the output capacitance,

1_static_char is the static characteristic of the output at "1" logic level,

0_static_char is the static characteristic of the output at "0" logic level,

stf is the static transfer function of the output and

dtf is the dynamic transfer function of the output.

Electrical library

17-8



Special components

component

power rail

ground rail

core

Any Sprint

netlist using

any Sprint

primitive

1

3

5

7

n -1

2

4

6

8

n

• PRESTO doesn’t provide automatic driver/receiver management for SC

• The internal description has to be complete and the output signals (to the external

nets) depend only by the input signals (coming from the external nets) or by signal

generated internally by means of user-defined voltage/current sources

• Allows the modeling of crosstalk between pins belonging the same package

Electrical library

17-9

package



Example of special component model

AC02 (four NOR):

1 2 3 4 5 6 7

gnd

vcc

standard

receiver model 8 9 10 11 12 13 14

R

1V

0V

Delay

Delay

Delay

2

3

1

Single NOR model

Four NOR models

A B OUT

0 0 1

1 0 0

0 1 0

1 1 0 standard driver model pin crosstalk

model

Electrical library

17-10

. . .

timing/logic core



Importing and exporting models

• To import a model from an ASCII file (SPRINT syntax): – Select a target library.

– Select the Import command and specify the file to load.

– The model description will be loaded in the target library.

• To write a model on an ASCII file (SPRINT syntax): – Select a source library

– Select a model from the list displayed in the window

– Select the Export command and specify the output file name.

– The model description will be saved on the file.

Electrical library

17-11





1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

18-1

Layout optimisation



Performing a “What-If?” analysis

• Check the effects of small modifications of the design: “What happens if I try to … ?”

• Action at component level: – deleting or changing the values of existing components

– inserting new components (e.g. decoupling capacitors, matching resistors, noise sources)

• Action at layout level: – deleting existing segments

– adding “physical” segments (with electrical properties defined by their geometry)

– adding “electrical” segments (with electrical properties set up by the user)

Layout optimisation

18-2



Friendly Graphic User Interface

Layout optimisation

18-3

Click with the center

button of the mouse on a

layout object (net, pin,

via) to identify it

Select What-If analysis to open the

optimisation window: it’s necessary to

choose if dealing with Components or

with Segments



Component optimisation

Layout optimisation

18-4

Currently deleted/ insereted/ modified

components. They are identified by:

• Component name (it’s the name of the

physical component as found in the library)

• Package name and Factory name

• Instance name

• Value (for passive component only)

• Type

Modification token “Enable/Disable”: this

allows to perform multiple simulation with or

without some modifications in order to point

out the best solution

Component

properties and pin

connection

window



Segment Optimisation

Electrical Segment

insertion window

Currently deleted/ insereted/

modified segments. Their related

net is displayed

Physical Segment

insertion window

18-5

Layout optimisation





1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

19-1

EMI analysis



EmiR analysis flow

EMI analysis

A Signal Integrity

simulation with suitable

stimuli is performed

A Fast Fourier Transform

of the currents flowing

through the traces allows

the simulator to work

in the frequency domain

An analytical method based

on the Green dyadic is used

to evaluate the field

radiated by the traces

19-2



Time domain parameters setup

The simulation time window is completely

defined by the frequency parameters of EmiR:

• Tstart is 100ns, because the analysis in the time domain

must be “transient-free”

• Minimum working frequency: this affects the Tstop

parameter, because the FFT must be performed on a

complete period of the signal

• Maximum working frequency: this affects the

resolution parameter, because the FFT algorithm must

have enough sampled data to provide high frequency

results

• Simulation Time Step: the user can modify this

parameter, but a check is performed and an error

message is displayed if it’s too large compared to the

selected frequency domain

19-3

EMI analysis



EMI simulation characteristic

• The Cross Talk analysis is not compatible with the EMI one

• Defined stimuli and delay are neglected (all the nets are driven with a 50% duty cycle waveform selected according to the minimum EMI frequency), then:

– the analysis is made at only one digital frequency

– all the nets have signals “in phase”

– the even harmonics of the spectrum are very lower then the odd ones (this depends on the 50% duty cycle)

19-4

EMI analysis



EmiR setup

Anechoic

chamber

analysis

Run EmiR

analysis

Semi-anechoic

chamber analysis

Near Field

analysis Far Field

analysis

H-Field

spectrum

EMI Maps

Radiation

Diagram

E-Field

Spectrum

Far Field from

the board

Far Field from the

board with an

attached cable

EMI

Profiles E-Field

Spectrum

19-5

EMI analysis



Anechoic chamber analysis

Select low frequency

algorithm

Provide all field

components:

(Ex, Ey, Ez)

Select results in Root Mean

Square dBuV/m

Select frequency

for radiation

diagram

19-6

EMI analysis



Semi-anechoic chamber analysis

Use a fixed height for the

antenna or perform a scan,

taking as results the

maximum field calculated at

each step

Define cable parameters.

NOTE: it is supposed to be

solded at the ground plane

of the board

19-7

EMI analysis

Date post:	16-Jul-2015
Category:	Technology
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