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Module Introduction• Purpose:

– This module considers the SC140’s Address Generation Unit. In this module we discuss the components and structure of the Address Generation Unit. We consider register modes and Program Control relative addressing.

• Objectives:– Describe the structure of the SC140’s Address Generation Unit– Identify the components of the SC140’s Address Generation Unit– Describe the operation of the SC140’s address modes– Describe the operation of the SC140’s address modify modes

• Contents: 21 pages• Questions 5 Test questions• Learning Time: 25 minutes

Welcome to TechOnline’s course covering the StarCore SC140 DSP Core. The SC140 Address Generation Unit module is the second in a series of four StarCore SC140 course modules. This module considers the SC140’s Address Generation Unit. In this module, we discuss the components and structure of the Address Generation Unit and review the AGU programming model. We’ll also consider SC140 address modes and address modify modes.

Let’s begin by discussing the architecture of the Address Generation Unit.

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Address Generation Unit

• The Address Generation Unit (AGU) performs address calculation using four types integer arithmetic

– Linear– Modulo– Multiple Wrap-Around Modulo– Reverse-Carry

• Contains two Address Arithmetic Units (AAU) and a Bit Masking Unit (BMU)

• Generates two addresses for data accesses to the memory space and updates the address registers according to the specified address in each cycle

• Supports data access widths of 8/16/32/64 bits• The AGU also generates change of flow addresses (jump and call)• AAU’s can also be used as a general purpose integer arithmetic unit• The BMU is used to perform bit mask operations

The Address Generation Unit, or AGU, is used primarily to perform address calculations, and it uses four types of integer arithmetic's in these calculations. There is linear addressing, where it can view the memory as being one contiguous block and it can either sequentially or randomly access memory. Modulo arithmetic, which is an integer arithmetic where the post modification or address arithmetic effecting one of the address registers, wraps around, in a similar manner as a circular buffer. There is multiple wrap-around modulo, which is useful in waveform generation or decimation. It’s similar to Modulo arithmetic, as there is a wrap-around that occurs. But, if the increment is substantial enough, it will wrap around multiple times. And finally, there is Reverse-carry addressing. This is useful in FFT type algorithms.

The AGU contains two address arithmetic units, or AAUs, and a single bit masking unit, or BMU. The AAUs generate addresses for data access to the memory space. They have the capability of updating the address registers according to the specified address in each cycle. The addressing within the SC140 supports data access widths of 8 bits, or one byte, 16 bit words, 32 bit long words and 64 bit double long words.

The AAU is also used to generate change of flow addresses for instructions like jumps, calls, etc. The AAUs can also be used as general purpose integer arithmetic units. The BMU is used for bit mask operations.

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AGU Block Diagram

M0M1M2M3

N0N1N2N3

B0/R8B1/R9B2/R10B3/R11B4/R12B5/R13B6/R14B7/R15

R0R1R2R3R4R5R6R7

SP (NSP,ESP)

AddressArithmetic

Unit(AAU)

BitMaskUnit

(BMU)Program Counter (PC)

Memory data bus 1 (XDBA)Memory data bus 2 (XDBB)

XABA XABB PAB

MCTL

Here, we see a block diagram of the AGU. The major components included in the AGU are, of course, the two AAUs. As you can see, there are also 8 address registers labeled R0 through R7, and eight alternative address registers labeled R8 through R15. These alternative registers are in a shared register bank with the base registers, B0 through B7. The base address registers are used in modulo addressing.

As we discussed in our last module, there are two stack pointers, the NSP and the ESP. There are four offset registers, N0 through N3 and four modifier registers, M0 through M3. The offset registers are used for post incrementing during register indirect operations. The modifier registers are used in the modulo buffer and multiple wrap modulo buffer operations. There is also a modifier control register, the MCTL register, that controls the behavior of various types of buffers.

The AAUs contain a 32-bit full adder, and are capable of adding or subtracting two AGU registers. It can also add an immediate value to an AGU register, increment or decrement an AGU register, or do somearithmetic operations with the program counter and an AGU register. In one clock cycle, each of the AAUs can update one address register and generate a 32-bit address that can get placed on the program address bus, or one of the X address buses.

Next, we’ll consider the bit mask unit.

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Bit Mask Unit

• The BMU performs bit mask operations according to immediate mask operand:– Setting– Clearing– Changing– Testing

• Bit Mask instructions are executed in two cycles, and work on 16-bit data in memory or a portion of a register

• A subset of the Bit Mask instructions (BMTSET) allow for hardware support of semaphoring:

1. Test the destination and set T-bit if all bits set in mask are set in destination.

2. Set (write) every bit in the destination that is set in the mask3. Set the T-bit if the set (write) failed.

The BMU performs bit mask operations. It has the ability to set, clear, change, or test a particular set of bits specified by an immediate mask. All of the bit mask instructions execute in two cycles and only work on 16-bit data in memory or the 16-bit upper or lower section of a register.

There is a subset of the bit mask instructions, called bit mask test and set, which are useful in support of hardware semaphoring. This works in essentially three steps. First, the destination is tested, to see if the bits to be set are already set. If this is the case, the T-bit in the status register will be set. Second, it attempts to write every bit in the destination, based upon the mask, if they were not already written. Third, it will test to see if the write failed. If the write did fail, the T-bit will be set. Therefore, if the T-bit is set during this operation, somewhere in the execution of these steps, access was not available to that shared resource.

Next, we’ll consider the SC140’s AGU programming mode.

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AGU Programming Model

Address/Base Address Registers

B0/R8B1/R9

B2/R10B3/R11B4/R12B5/R13B6/R14B7/R15

N0N1N2N3

Offset Registers031

31 0

M0M1M2M3

Modifier Registers031

Address Registers

R0R1R2R3R4R5R6R7

SP (NSP,ESP)

31 0

MCTL031

Here, we see an overview of the AGU programming model. There aresixteen 32-bit address registers, eight of which are shared with the base address registers in a shared register bank. R8 and R15 can only be used in the linear addressing mode. This is because the modulo addressing, multiple wrap-around modulo addressing, and reverse-carry addressing modes, all utilize or specify the use of the base address registers. Address registers can be post updated, according the address mode selected, using the modifier register or the offset register. We’ll show examples of this later.

There are two stack pointers implicitly used in all PUSH and POPinstructions. They are post-incremented on PUSH operations and pre-decremented on POP operations. Finally, there are four offset registers which are used to increment and decrement registers in address register calculations.

Now, let’s take a moment to review by considering the following question.

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Question

The SC140 AGU is supported by how many general purpose address registers?

A4B 8C 12D16

The SC140 AGU is supported by how many general purpose address registers?

Answer: The SC140 AGU is supported by 16 general purpose address registers.

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Addressing Modes

• Four different addressing modes:– Register Direct Modes– Address Register Indirect Modes– PC Relative Modes– Special Address Modes

There are four different addressing modes supported by the SC140. The register direct mode, in which case the operand is already in a register and the instruction, by specifying that register, can use this data directly. The address register indirect mode, where the operand is located in memory and the register itself acts as a pointer of where to go get the data that will be used in the instruction.

PC relative modes, where the operand address is a mathematical operation of the program counter and a displacement that is added to it. And, the special address modes that use an immediate value to determine the data or address of interest.

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Register Direct Modes

Data or Control Register Direct Address Register DirectExample: Example:move.l d0,d1 move.l d0,r0;direct move

nopmove.l (r0),d1

;indirect move

$00001ef9 $c001

$0000d00dR0

$00001ef9D0

Before

$00001ef9 $c001

R0

D0

After

$0000d00d

$00001ef9

$0000abeD1 D1 $00001ef9

$00001ef9 $c001

$0000d00dR0

$00001ef9D0

Before

$00001ef9 $c001

R0

D0

After

$00001ef9

$00001ef9

$0000abeD1 D1 $0000c001

Here are some examples of register direct modes. In the example on the left, we see that the instruction that will be executed is a move of the contents of D0 to D1. Before this instruction is executed, the content of D0 is 1EF9 and D1 contains the value of ABE. After the instruction executes, D1 contains the value of 1EF9 as well. This is an example of data or control register direct.

In the address register direct example on the right, there is a sequence of three instructions. The first instruction exhibits the direct move. The contents of D0, 1EF9, are being moved to R0. The third instruction utilizes the contents of R0 in an indirect fashion. What this shows is that if an AGU register is changed with a move, POP, or bit mask instruction, the contents are not available for use as a pointer in the immediately following instruction. This is because of the pipeline flow.

The execution stage is the fifth stage of the pipeline, or when the contents of R0 would be updated in our example. To use R0 in an indirect move, the new content would be needed in the address generation stage of the pipeline, which is the fourth stage, before R0 would have been updated. Therefore, the nop instruction is required in this example.

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Register Indirect Mode Examples

$00001000 $0abe

$00001000R0

Address Register Indirect ModeNo Update

Example: move.w (r0),d0

$0000faceD0

Before

$00001000 $0abe

R0

D0

After

$00001002 $f00d

R0

Address Register Indirect ModePost-Increment

Example: move.l d0,(r0)+

D0

Before

$00001002 $0000

R0

D0

After

$00001000 $feed $00001000 $face

$00001000

$00000abe

$00001000

$0000face

$00001004

$0000face

The register indirect modes are used to compute the address of an operand. The operand that is desired is in memory, and the address register is used as a pointer to the operand in fetching it from or writing it back to memory. Post modifications can be specified, including post incrementing, post decrementing, incrementing by an offset, indexing by an offset, indexing by address registers, as well as both short and word displacements.

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Register Update CalculationsAddressing Mode Calculation Memory Access Width

Byte Word Long Two LongPost-increment (Rn)+ Rn register post-increment 1 2 4 8Post-decrement (Rn)- or post-decrementPost increment by Rn register post-increment Ni*1 Ni*2 Ni*4 Ni*8Offset (Rn)+NiIndexed by offset N0 Address calculation Rn+N0 Rn+2*N0 Rn+4*N0 Rn+8*N0(Rn+N0)Indexed by Address Address calculation Rn+Rm Rn+2*Rm Rn+4*Rm Rn+8*RmRegister Rm (Rn+Rm)Short Displacement Address calculation Rn+Disp Rn+2*Disp Rn+4*Disp Rn+8*DispWord Displacement Address calculation Rn+Disp Rn+Disp Rn+Disp Rn+DispSP update in Push/Pop SP post-increment or 8 8 8 8

pre-decrement

The SC140 core supports byte, word, long word or double long word accesses. The access width is determined by the type of instruction used. When you post an increment by a particular value, either by an offset, by post incrementing, or by decrementing by one memory access width, the value gets shifted to the correct value based on the access width.

For example, if you access in a byte-wise fashion, the post increment will be one, but if you access by a word, it will post increment by 2, since a word is 16 bits. Essentially, it addresses as byte-wise, and shifts accordingly based on the access width.

Next, we’ll consider PC relative addressing.

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PC Relative Addressing• PC relative addressing is used for program change of flow

– Conditional branch instruction– Unconditional branch instruction – Two-word Branch instruction – DOSETUP instruction

• Examples:bt TRUE_PATHbra LABELbsr SUBROUTINE

DOSETUP0 LPSTARTADDR

PC relative addressing is used for program change of flow. PC relative addressing is used for instructions such as conditional and unconditional branch instructions, as well as two-word branch instructions. Your setups should be built as shown in these examples.

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Special Address Modes• Special Address Modes use immediate values to determine data or address

– Immediate Short Data – Immediate Word Data – Immediate Long Data – Absolute Word Address– Absolute Long Address – Absolute Jump Address – Implicit Reference

• Examplesadd #3,d0 ; immediate short data

move.l (table_start),d1 ; absolute long address

Special address modes use immediate values to determine the data or address that will be used. In our first example, the immediate value of 3 is added to the contents of D0. In our second example, table_start is an immediate long address that is used in the calculation. The contents that are addressed by the immediate address table_start are stored in the data register D1.

Now that we’ve discussed the SC140 address modes, let’s review by considering the following question.

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QuestionWhich of these describe all the addressing modes offered by the SC140?

A Register Offset, Address Register Indirect, PC Relative, and Special Address

B Register Direct, Address Register Direct, PC Relative, and Direct Address

C Register Direct, Address Register Indirect, PC Relative, and Special Address

D Register Direct, Address Register Indirect, PC Relative, and Direct Address

Which of these describe all the addressing modes offered by the SC140?

Answer: Register Direct, Address Register Indirect, PC Relative, and Special Address are the addressing modes offered by the SC140.

Next, we’ll consider the address modify modes.

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Address Modify Modes

• Four types of integer arithmetic are support for address calculation and modification

– Linear addressing – Reverse-carry addressing – Modulo addressing – Multiple wrap-around modulo addressing

There are four types of address modify modes that are supported by the SC140 core. Linear addressing is used for general purpose addressing. Reverse-carry addressing is useful for FFT type addressing. Modulo addressing is used for circular buffers and FIFO's. And, Multiple wrap-around modulo addressing is used for decimation, interpolation, waveform generation, and other similar types of functions. The type of arithmetic that gets used when utilizing the address registers is determined by a value that is programmed into the MCTL register.

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Reverse-Carry Addressing Mode

-

+

+x

A

B

A’=A+Bw**k

W**k

B’=A-Bw**k

Radix 2, decimation in time, complex DFT

W

W

W

WW

W

W

W

W

W

W

W

000 0

001 1

010 2

011 3

100 4

101 5

110 6

111 7

0 000 0

4 100 1

2 010 2

6 110 3

1 001 4

5 101 5

3 011 6

7 111 7

Flow diagram for 8-point decimation in time FFTTime DomainInput

Frequency DomainOutput

Example:

N2MCTL

$00000200$00010000

R4 $00000C00

move.l (r4)+n2,d0R4 $00000200

move.l (r4)+n2,d0R4 $00000A00

move.l (r4)+n2,d0R4 $00000600

Here, we see a flow diagram for an eight point decimation in time FFT. This FFT is a mathematical approximation of a discrete Fourier transform. The discrete Fourier transform allows representation of a signal in the time and frequency domains. The order of complexity for a discrete Fourier transform is on the order of N2, for example, when computing an eight input sample, it requires 64 computations. The FFT reduces the computational complexity to logN.

Looking at our example, you can see the time domain on the left as the input, and the frequency domain on the right as the output. It appears as if the output has no order to it, but in reality, it does. Look at the input and you will recognize it as a binary numerical sequence. On the output side, read the binary number from right to left, and you will see that the output is ordered as well. This indicates that the FFT output data is in a bit reversed format. Using the reverse carry addressing mode, bit reversing is performed automatically.

In our example, the MCTL register is set such that the R4 register is used for bit reverse addressing. We are using n2 as the post incrementing value, and R4 is initially set to C00. We move a long word pointed to by R4 into D0, and then once we are done with the move, we update the contents of R4, incrementing it by n2.

There are two things to note here. First, since this is reverse carry mode, the carry when updating it by n2 propagates from left to right, instead of right to left as one would normally expect. And second, since this is a long word access, the value of n2 actually gets shifted by 2 before it gets added. This is due to a long word access being 32 bits. Therefore, we have the shifting by two before doing the add, and then the propagation of the carry from left to right.

At the completion of the first move instruction, the value changes from C00 to 200, based on the propagation of the carry reverse as well as the addition of the value of n2, shifted by 2. After the second instruction, the value will be A00. At the conclusion of the third instruction, the value will be 600.

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Modulo Addressing ModeExample:

10a7

1007

B2MCTL

$00001007$00000800

R2 $000010a5

move.b (r2)+,d0

R2 $000010a6

move.b (r2)+,d0

R2 $00001007

inca r2

R2 $00001008

M0 $000000a0

The Modulo addressing mode is useful in circular buffers. In this example, we see the MCTL register initialized to a value that indicates the use of the B2 and R2 register pair as a circular buffer. B2 acts as the base. The value of the MCTL register specifies that the contents of M0 should be used as the length of this particular buffer. Then, R2 is the paired value with B2 and acts as the current pointer. So, instructions that modify the contents of R2 are subject to this modulo addressing mode.

In our example, the first instruction is a move of byte addressing, using R2 as a pointer in memory. This moves the contents of that memory location R2 into D0. At the conclusion, it post increments R2. In this particular case, it increments R2 by the exact value of 1, since we are accessing a byte. R2, heading into this instruction, is at the value 10A5. At the conclusion of the instruction, it will be at the value 10A6. Another move of a byte, using the same instruction, does not result in a value of 10A7. Instead, since modulo addressing mode is being used, it has the value of 1007.

Also, note that our example includes an instruction that increments the value of R2. This is also subject to modulo addressing mode behavior. For example, if this instruction is used with the previous value, rather than the move.b instruction, it too would have wrapped around from 10A6 to 1007. So, it is any instruction that modifies an address register that is subject to a particular addressing mode based upon the MCTL register setting.

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Multiple Wrap-Around Modulo Addressing Mode

Example:

abc8

abc0

B2MCTL

xxxxxxxx$00000c00

R2 $0000abc4

move.w (r2)+n3,d0R2 $0000abc6

move.w (r2)+n3,d0R2 $0000abc0

adda #$12,r2R2 $0000abc2

M0 $00000007N3 $00000011

In Multiple wrap-around modulo addressing, the address modification is performed via modulo M. But, in this particular case, this modulo M must be a power of two, setting the base address to certain limited values. The MCTL register, in this example, is set up such that the R2 register is subject to multiple wrap-around modulo addressing. In addition, we have specified that M0 determines the length of the multiple wrap-around modulo buffer.

R2 is initially set at the value ABC4, and the length of the modulo buffer is 7. The first instruction does a move of a word value, with R2 acting as a pointer to memory, and moves the content of that location to D0, with a post modification of n3. Since this is a move of a 16-bit word, the n3 value is shifted by 1 when the modulo addressing occurs. This equates to an R2 value at the conclusion of the instruction of ABC6. Executing the same instruction again, we see it wraps around multiple times, settling on a value of ABC0.

This again demonstrates that not only are move instructions with post modification affected by the addressing mode, but any modification to an address register is affected by the addressing mode.

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Question

Which of the following address modify modes are supported by the SC140 core?

A Linear addressing, reverse carry addressing, modulo addressing, and multiple wrap around modulo addressing

B Linear addressing, Offset addressing, modulo addressing, and multiple wrap around modulo addressing

C Direct addressing, reverse carry addressing, modulo addressing, and multiple wrap around modulo addressing

D Linear addressing, reverse carry addressing, indirect addressing, and multiple wrap around modulo addressing

Which of the following address modify modes are supported by the SC140 core?

Answer: Linear addressing, reverse carry addressing, modulo addressing, and multiple wrap around modulo addressing are supported by the SC140 core.

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Question

How many functional units are contained in the SC140 Address Generation Unit?

a. 1 b. 2 c. 3 (correct. Two Address Arithmetic Units and one Bit Masking unit) d. 4 e. 5

How many functional units are contained in the SC140 Address Generation Unit?

Answer: There are 3 functional units contained in the SC140 Address Generation Unit.

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Question

The SC140 AGU supports what data access widths?

a. 8 bits, or one byte b. 16 bit words c. 32 bit long words d. 64 bit double long words e. all of the above (correct) f. a, b & c

The SC140 AGU supports what data access widths?

Answer: The SC140 AGU supports access widths of 8 bits, or one byte, 16 bit words, 32 bit long words, and 64 bit double long words.

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Module Completion

• SC140 Address Generation Unit– Block diagram– Bit mask unit– Programming model– Addressing modes

> Direct mode> Indirect mode> PC relative addressing> Special addressing modes

– Address modify modes> Linear addressing mode> Reverse carry addressing mode> Modulo addressing mode> Multiple wrap around modulo addressing mode

In this module, we’ve discussed the components and structure of the SC140 Address Generation Unit. We reviewed the AGU programming model and covered the capabilities of the Address Arithmetic Units and Bit Mask Unit within the AGU.We considered the AGU addressing modes including the register direct and indirect modes, as well as PC relative addressing and the special addressing modes.

We concluded this module with a look at the SC140’s addressing modify modes. We saw that there are four types of integer arithmetic supported for address calculation and modification: linear addressing, reverse-carry addressing, modulo addressing and multiple wrap-around modulo addressing.