Prob : 1 Design a NAND Gate using CMOS using Pull up And ... spice 3rd SEM_MOD.pdf · 3rd Semester,...

3rd Semester, M-Tech in VLSI & Microelectronics Tanner Spice Lab Report

PPaaggee 11 ooff 1133

Prob : 1 Design a NAND Gate using CMOS using Pull up And Pull Down network logic.

Circuit Diagram:

NETLIST for the Circuit

* Waveform probing commands .probe .options probefilename="Nand.dat" + probesdbfile="C:\Documents and Settings\Administrator\Desktop\Batch-2_Vivita\Nand.sdb" + probetopmodule="Module0" * Main circuit: Module0 C1 Y Gnd 1pF M2 Y A N15 N5 NH L=0.2u W=2u AD=66p PD=24u AS=66p PS=24u M3 N15 B Gnd Gnd NH L=0.2u W=0.2u AD=66p PD=24u AS=66p PS=24u M4 Y A Vdd Vdd PH L=0.2u W=5u AD=66p PD=24u AS=66p PS=24u M5 Y B Vdd Vdd PH L=0.2u W=5u AD=66p PD=24u AS=66p PS=24u v6 A Gnd bit({0100} pw=100n on=5.0 off=0.0 rt=1n ft=1n delay=0 lt=100n ht=100n) v7 B Gnd bit({0111} pw=100n on=5.0 off=0.0 rt=1n ft=1n delay=0 lt=100n ht=100n) vdd vdd gnd 1v .tran 1n 400n .include dual.md .print v(A) v(B) v(Y) .End of main circuit: Module0



OUTPUT for the Circuit



Prob : 2 Design a NOR Gate using CMOS using Pull up And Pull Down network logic.

Circuit Diagram:

NETLIST for the Circuit .probe .options probefilename="Nor.dat" + probesdbfile="C:\Documents and Settings\Administrator\Desktop\Batch-2_Vivita\Nor.sdb" + probetopmodule="Module0" * Main circuit: Module0 C1 Y Gnd 1pF M2 Y A Gnd Gnd Nh L=0.2u W=2u AD=66p PD=24u AS=66p PS=24u M3 Y B Gnd Gnd Nh L=0.2u W=2u AD=66p PD=24u AS=66p PS=24u M4 N8 A Vdd Vdd Ph L=0.2u W=5u AD=66p PD=24u AS=66p PS=24u M5 Y B N8 Vdd Ph L=0.2u W=5u AD=66p PD=24u AS=66p PS=24u v6 A Gnd bit({0101} pw=100n on=5.0 off=0.0 rt=1n ft=1n delay=0 lt=100n ht=100n) v7 B Gnd bit({0111} pw=100n on=5.0 off=0.0 rt=1n ft=1n delay=0 lt=100n ht=100n) vdd vdd gnd 1v .tran 1n 400n .include dual.md .print v(A) v(B) v(Y) .End of main circuit: Module0






Prob : 3 Design an XOR Gate using CMOS using Pull up And Pull Down network logic.

Circuit Diagram:

NETLIST for the Circuit * Waveform probing commands .probe .options probefilename="Cmos Xor.dat" + probesdbfile="C:\Documents and Settings\Administrator\Desktop\Batch-2_Vivita\Cmos Xor.sdb" + probetopmodule="Module0" * Main circuit: Module0 M1 Vout A N4 Gnd NH L=.2u W=2u AD=66p PD=24u AS=66p PS=24u M2 Vout Ab N3 Gnd NH L=.2u W=2u AD=66p PD=24u AS=66p PS=24u M3 N4 B Gnd Gnd NH L=.2u W=2u AD=66p PD=24u AS=66p PS=24u M4 N3 Bb Gnd Gnd NH L=.2u W=2u AD=66p PD=24u AS=66p PS=24u M5 Bb B Gnd N1 NH L=.2u W=2u AD=66p PD=24u AS=66p PS=24u M6 Ab A Gnd Vdd NH L=.2u W=2u AD=66p PD=24u AS=66p PS=24u M7 Vout B N8 Vdd PH L=.2u W=5u AD=66p PD=24u AS=66p PS=24u M8 Bb B Vdd N2 PH L=.2u W=5u AD=66p PD=24u AS=66p PS=24u M9 Ab A Vdd Vdd PH L=.2u W=5u AD=66p PD=24u AS=66p PS=24u M10 Vout Bb N7 Vdd PH L=.2u W=5u AD=66p PD=24u AS=66p PS=24u M11 N7 A Vdd Vdd PH L=.2u W=5u AD=66p PD=24u AS=66p PS=24u M12 N8 Ab Vdd Vdd PH L=2u W=5u AD=66p PD=24u AS=66p PS=24u



v13 A Gnd bit({0011} pw=100n on=1.0 off=0.0 rt=1n ft=1n delay=0 lt=100n ht=100n) v14 B Gnd bit({0101} pw=100n on=1.0 off=0.0 rt=1n ft=1n delay=0 lt=100n ht=100n) v15 Vdd Gnd 1.0 .tran 1n 400n .include dual.md .print v(A) v(B) v(Vout) .measure tran delay trig v(B) val=.5 rise=1 targ v(Vout) val=.5 rise=1 .End of main circuit: Module0




Prob : 4 Design a Full adder using CMOS using Pull up And Pull Down network logic and measure the power dissipated.

Circuit Diagram:

NETLIST for the Circuit * SPICE netlist written by S-Edit Win32 6.00 * Written on Aug 29, 2006 at 20:06:58 * Waveform probing commands .probe .options probefilename="Full_Adder.dat" + probesdbfile="C:\Documents and Settings\Administrator\Desktop\Batch-2_Vivita\Full_Adder.sdb" + probetopmodule="Module0" * Main circuit: Module0 M1 N33 A Gnd Gnd NH L=.2u W=2u AD=66p PD=24u AS=66p PS=24u M2 CarryB A N2 Gnd NH L=.2u W=2u AD=66p PD=24u AS=66p PS=24u M3 N2 B Gnd Gnd NH L=.2u W=2u AD=66p PD=24u AS=66p PS=24u M4 CarryB C N33 Gnd NH L=.2u W=2u AD=66p PD=24u AS=66p PS=24u M5 N33 B Gnd Gnd NH L=.2u W=2u AD=66p PD=24u AS=66p PS=24u M6 Carry CarryB Gnd Gnd NH L=.2u W=2u AD=66p PD=24u AS=66p PS=24u M7 N9 CarryB N55 Gnd NH L=.2u W=2u AD=66p PD=24u AS=66p PS=24u M8 N55 A Gnd Gnd NH L=.2u W=2u AD=66p PD=24u AS=66p PS=24u



M9 N55 B Gnd Gnd NH L=.2u W=2u AD=66p PD=24u AS=66p PS=24u M10 N47 C Gnd Gnd NH L=.2u W=2u AD=66p PD=24u AS=66p PS=24u M11 N51 B N47 Gnd NH L=.2u W=2u AD=66p PD=24u AS=66p PS=24u M12 N9 A N51 Gnd NH L=.2u W=2u AD=66p PD=24u AS=66p PS=24u M13 N55 C Gnd Gnd NH L=.2u W=2u AD=66p PD=24u AS=66p PS=24u M14 Sum N9 Gnd Gnd NH L=.2u W=2u AD=66p PD=24u AS=66p PS=24u M15 N11 A Vdd Vdd PH L=.2u W=5u AD=66p PD=24u AS=66p PS=24u M16 N11 B Vdd Vdd PH L=.2u W=5u AD=66p PD=24u AS=66p PS=24u M17 CarryB B N1 Vdd PH L=.2u W=5u AD=66p PD=24u AS=66p PS=24u M18 N1 A Vdd Vdd PH L=.2u W=5u AD=66p PD=24u AS=66p PS=24u M19 CarryB C N11 Vdd PH L=.2u W=5u AD=66p PD=24u AS=66p PS=24u M20 Carry CarryB Vdd Vdd PH L=.2u W=5u AD=66p PD=24u AS=66p PS=24u M21 N14 B Vdd Vdd PH L=.2u W=5u AD=66p PD=24u AS=66p PS=24u M22 N14 C Vdd Vdd PH L=.2u W=5u AD=66p PD=24u AS=66p PS=24u M23 N14 A Vdd Vdd PH L=.2u W=5u AD=66p PD=24u AS=66p PS=24u M24 N22 A Vdd Vdd PH L=.2u W=5u AD=66p PD=24u AS=66p PS=24u M25 N27 B N22 Vdd PH L=.2u W=5u AD=66p PD=24u AS=66p PS=24u M26 Sum N9 Vdd Vdd PH L=.2u W=5u AD=66p PD=24u AS=66p PS=24u M27 N9 CarryB N14 Vdd PH L=.2u W=5u AD=66p PD=24u AS=66p PS=24u M28 N9 C N27 Vdd PH L=.2u W=5u AD=66p PD=24u AS=66p PS=24u v13 B Gnd bit({01010101} pw=100n on=1.0 off=0.0 rt=1n ft=1n delay=0 lt=100n ht=100n) v14 A Gnd bit({00110011} pw=100n on=1.0 off=0.0 rt=1n ft=1n delay=0 lt=100n ht=100n) v15 C Gnd bit({00001111} pw=100n on=1.0 off=0.0 rt=1n ft=1n delay=0 lt=100n ht=100n) vdd vdd gnd 1v .include dual.md .tran 1n 800n .power vdd .print v(A) v(C) v(Carry) v(Sum) p(vdd)

.End of main circuit: Module0




Results for Power and Delay for the Circuit

FULL_ADDER CIRCUIT for HIGH THRESHOLD

Sum Carry A B C Power Delay Power Delay 0 0 0 3.07E-09 3.07E-09 0 0 1 4.98E-08 9.23E-10 4.98E-08 0 0 1 0 2.81E-09 9.60E-10 2.81E-09 0 1 1 2.95E-09 0 2.95E-09 6.90E-10 1 0 0 3.25E-08 1.00E-09 3.25E-08 0 1 0 1 3.28E-08 3.28E-08 7.32E-10 1 1 0 6.69E-08 6.69E-08 8.80E-10 1 1 1 1.81E-09 4.80E-10 1.81E-09 1.12E-09



Prob : 5 Design a XOR Gate using CMOS using Transmission Gate logic and measure the Power.

Circuit Diagram:

NETLIST for the Circuit * SPICE netlist written by S-Edit Win32 6.00 * Written on Sep 7, 2006 at 19:36:28 * Waveform probing commands .probe .options probefilename="sedit.dat" + probesdbfile="File1.sdb" + probetopmodule="Module0" * Main circuit: Module0 M1 B Ab Vout Gnd NH L=.2u W=2u AD=66p PD=24u AS=66p PS=24u M2 Bb A Vout Gnd NH L=.2u W=2u AD=66p PD=24u AS=66p PS=24u M3 Bb B Gnd N3 NH L=.2u W=2u AD=66p PD=24u AS=66p PS=24u M4 Ab A Gnd Vdd NH L=.2u W=2u AD=66p PD=24u AS=66p PS=24u M5 B A Vout Vdd PH L=.2u W=5u AD=66p PD=24u AS=66p PS=24u M6 Bb B Vdd N2 PH L=.2u W=5u AD=66p PD=24u AS=66p PS=24u M7 Ab A Vdd Vdd PH L=.2u W=5u AD=66p PD=24u AS=66p PS=24u M8 Bb Ab Vout Vdd PH L=.2u W=5u AD=66p PD=24u AS=66p PS=24u v9 A Gnd bit({0011} pw=100n on=1.0 off=0.0 rt=1n ft=1n delay=0 lt=100n ht=100n) v10 B Gnd bit({0101} pw=100n on=1.0 off=0.0 rt=1n ft=1n delay=0



lt=100n ht=100n) v11 Vdd Gnd 1.0 .tran 1n 400n .include dual.md .power v11 100n .print v(A) v(Vout) p(v11) .measure tran delay trig v(B) val=.5 rise=1 targ v(Vout) val=.5 rise=1 * End of main circuit: Module0


* BEGIN NON-GRAPHICAL DATA Power Results v11 from time 1e-007 to 1e-030 Average power consumed -> 2.479105e-006 watts Max power 4.043389e-004 at time 2.00752e-007 Min power 1.620846e-009 at time 2.13097e-007



Prob :6 Design a MUX using CMOS.

NETLIST for the Circuit * SPICE netlist written by S-Edit Win32 6.00 * Written on Sep 7, 2006 at 19:36:28 * Waveform probing commands .probe .options probefilename="sedit.dat" + probesdbfile="File1.sdb" + probetopmodule="Module0" * Main circuit: Module0 M1 Ab A Vdd Gnd NH L=0.2u W=2u AD=66p PD=24u AS=66p PS=24u M2 Bb B Vdd Gnd NH L=0.2u W=2u AD=66p PD=24u AS=66p PS=24u M3 I0 Ab Y1 Gnd NH L=0.2u W=2u AD=66p PD=24u AS=66p PS=24u M4 I1 Ab Y2 Gnd NH L=0.2u W=2u AD=66p PD=24u AS=66p PS=24u M5 I2 A Y1 Gnd NH L=0.2u W=2u AD=66p PD=24u AS=66p PS=24u M6 I3 A Y2 Gnd NH L=0.2u W=2u AD=66p PD=24u AS=66p PS=24u M7 Y1 Bb Y Gnd NH L=0.2u W=2u AD=66p PD=24u AS=66p PS=24u M8 Y2 B Y Gnd NH L=0.2u W=2u AD=66p PD=24u AS=66p PS=24u M9 Ab A Vdd Vdd PH L=0.2u W=5u AD=66p PD=24u AS=66p PS=24u M10 Bb B Vdd Vdd PH L=0.2u W=5u AD=66p PD=24u AS=66p PS=24u M11 I0 A Y1 Vdd PH L=0.2u W=5u AD=66p PD=24u AS=66p PS=24u M12 I1 A Y2 Vdd PH L=0.2u W=5u AD=66p PD=24u AS=66p PS=24u M13 I2 Ab Y1 Vdd PH L=0.2u W=5u AD=66p PD=24u AS=66p PS=24u M14 I3 Ab Y2 Vdd PH L=0.2u W=5u AD=66p PD=24u AS=66p PS=24u M15 Y1 B Y Vdd PH L=0.2u W=5u AD=66p PD=24u AS=66p PS=24u M16 Y2 Bb Y Vdd PH L=0.2u W=5u AD=66p PD=24u AS=66p PS=24u * End of main circuit: Module0 v1 I0 Gnd bit({11} pw=100n on=1.0 off=0.0 rt=1n ft=1n delay=0 lt=100n ht=100n) v2 I1 Gnd bit({01} pw=100n on=1.0 off=0.0 rt=1n ft=1n delay=0 lt=100n ht=100n) v3 I2 Gnd bit({00} pw=100n on=1.0 off=0.0 rt=1n ft=1n delay=0 lt=100n ht=100n) v4 I3 Gnd bit({01} pw=100n on=1.0 off=0.0 rt=1n ft=1n delay=0 lt=100n ht=100n) v5 A Gnd bit({01} pw=100n on=1.0 off=0.0 rt=1n ft=1n delay=0 lt=100n ht=100n) v6 B Gnd bit({00} pw=100n on=1.0 off=0.0 rt=1n ft=1n delay=0 lt=100n ht=100n) v15 Vdd Gnd 1.0 .include "C:\Documents and Settings\Administrator\Desktop\Batch-2_Vivita\dual.md" .tran 1n 200n .print v(I0) v(I1) v(I2) v(I3) v(Y) .END




Date post:	30-Apr-2018
Category:	Documents
Upload:	phunganh
View:	216 times
Download:	2 times