PROBABILITY AND STOCHASTIC PROCESSES (PSP) VLSI.doc · Web viewWeste Kamran Eshraghian, Principles...

G. PULLA REDDY ENGINEERING COLLEGE (Autonomous): KURNOOL Accredited by NBA of AICTE and NAAC of UGC

An ISO 9001:2008 Certified InstitutionAffiliated to JNTUA, Anantapur

M.Tech Syllabus- Scheme 2013(VLSI and Embedded Systems)

1

TWO YEAR M.TECH DEGREE COURSE (SCHEME-2013)Scheme of I nstruction and Examination

(Effective from 2013-2014)

M.Tech - I Semester VLSI and Embedded Systems Scheme: 2013

S. No Course

No.Course Title

Credits

Scheme of Instruction

periods/week

Scheme of Examination

Maximum Marks

L T P End Exam

Internal Assessment

Total

1. EC851 Advanced Problem Solving(APS) 3 3 - – 70 30 100

2. EC852 CMOS VLSI Design(CMOS) 3 3 – 70 30 100

3. EC853Modeling of Advanced Digital System design using HDL (MAD-HDL)

3 3 - – 70 30 100

4. EC854 Advanced Embedded Systems –I(AES-1) 3 3 – 70 30 100

5 Elective - I 3 3 – 70 30 100

6. EC855Advanced VLSI and Embedded Systems Lab (AVESP)

2 – 3 50 50 100

7. EC856 Seminar 1 - - - - 100 100

Total 18 15 - 3 400 300 700

2

Scheme : 2013Internal Assessment : 30End Exam : 70End Exam Duration: 3 Hrs

Course Objectives:1. To make students familiar with graphs and their properties in advanced level.2. To make students familiar with spanning tree and Shortest path algorithms.3. To make students familiar with critical path concepts used in VLSI Signal

Processing.Course outcomes:

1. Students will be able to know the concepts of DFG used in VLSI Signal Processing.

2. Students will be able to solve problems arise in complex graphs like travelling Salesman, Mohammad’s scimitar, Star of David etc…

Introduction: Basic definitions, Results and examples relating to Graph theory, Self–complementing graphs and properties of graphs, Trees, Spanning tree & directed graphs.

Classification of Graphs: Definitions of strongly, Weakly, Unilaterally connected graphs and deadlocks, Metric representation of graphs. Classes of graphs, Standard results relating to characterization of Hamiltonian graphs, Standard theorems

Self–Centered graphs and related theorems: Chromatic number vertex and edge , Application to coloring, Linear graphs, Euler’s formula.

Graph algorithms: DFS, BFS algorithms, Minimum spanning tree and maximum spanning tree algorithm. Directed graphs algorithms for matching, Properties flow in graph and algorithms for max flow. PERT-CPM, Complexity of algorithms, P–NP, NPC, NP hard problems and examples.

Linear integer and dynamic programming: Conversions of TSP, Maximum flow, Shortest path problems. Branch bound methods, Critical path and linear programming conversion. Flow shop scheduling problem, Personal assignment problem, Dynamic programming - TSP, Best investment problems.

Reference Books: 1. C. Papadimitriou & K. Steiglitz, Combinational Optimization, Prentice Hall, 1982.2. H. Gerej, Algorithms for VLSI Design Automation, John Wiley, 1992.Reference Books: 3. B. Korte & J. Vygen, Combinational Optimization, Springer Verilog, 2000.4. G.L. Nemhauser & AL Wolsey, Integer & Combinatorial Optimization, John Wiley, 1999.5. W.J. Cook et al, Combinational optimization, John Wiley,2000.

Note : The question paper shall consist of Eight questions out of which the student shall answer any Five questions

L T/D P C

3 0 0 3

EC851: ADVANCED PROBLEM SOLVING (APS)(For M. Tech ECE (VLSI&ES) – I Semester)

3

Scheme : 2013Internal Assessment : 30End Exam : 70End Exam Duratio : 3 Hrs

Course Objectives:1. To make students aware of Semi conductor Device Physics.2.To make students understand various inverter topologies in

PMOS, NMOS, CMOS, BICMOS.3. To make students understand fabrication of IC in different technologies.

Course Outcomes:1.Students will be able to grasp semi conductor physics.2.Students will be able to know VLSI processing technology.3.Students will be able to construct various circuits ,Stick diagrams,Layoutsusing CMOS.

Device Physics: Review of MOS Transistor Theory, MOS Device Equations I/V Basic DC Equations, Concept of Threshold voltage, Second Order Effects, Small Signal ac Characteristics.

Inverter Analysis: Complementary CMOS Inverter DC Characteristics, βn/βp Ratio, Noise Margin, CMOS Inverter as an Amplifier, Static Load CMOS Inverters I/V Pseudo NMOS Inverter, Saturated Load Inverters, Cascode Inverter, TTL Interface Inverter, Differential Inverter, Transmission Gate, Tri-state Inverter, BiCMOS Inverters.

Fabrication Process: Basic MOS Technology, NMOS and CMOS Process Flow, Stick Diagrams Design Rules, Layout Design and Tools, Latch-up in CMOS.

Circuit Characterization and Performance Estimation: Resistances and Capacitances Estimation, SPICE Modeling, Switching Characteristics, Delay Models, Rise and Fall times, Propagation Delays, Body Effect. CMOS Gate Transistor Sizing, Power Dissipation, Design Margining, Scaling Principles.

CMOS Circuit and Logic Design: CMOS Logic Gate Design, Basic Physical Design of Simple Logic Gates, CMOS Logic Structures, Clocking Strategies, Low Power CMOS Logic Structures, Chip Input and Output (I/O) Structures.

VLSI Design Methodologies: VLSI Design Flow, Structured Design Strategies, VLSI Design Styles, Chip Design Options.

Subsystem Structures: Arithmetic Logic Unit (ALU), Shifters, Memory Elements, High Density Memory Structures, Finite State Machines (FSM) and Programmable Logic Arrays (PLA).

Text Books:1. Weste Kamran Eshraghian, Principles of CMOS VLSI design , a Systems Perspective by NEILHE, Pearson Education Series, Asia, 2002.2. Wolf, Modern VLSI Design, Pearson Education Series, 2002.Reference Books:3. Jean M. Rabey, Digital Integrated Circuits, Prentice Hall India, 20034. M. Shoji, CMOS Digital Circuit Technology, Prentice Hall, 1987.


L T/D P C

3 0 0 3

EC852: CMOS VLSI DESIGN (CMOS)(For M. Tech ECE (VLSI&ES) – I Semester)

4

Scheme : 2013Internal Assessment : 30End Exam : 70End Exam Duration : 3 Hrs

Course Objectives:1. To make familiar with architecture of PLD’s & industry standard FPGA 2. To give understanding of various placement and routing algorithms.3. To give understanding of HDLs(Hardware Description Languages) like VHDL & Verilog

Course Outcomes:1. Students will be able to design systems with standard FPGAs2. students will be able to know various styles of modeling like

Dataflow,Behavioural,Structural modeling. 3. Students will be able to design (coding)digital systems in both VHDL&Verilog.

Introduction to PLDs & FPGAs: ROMs, Logic array (PLA), Programmable array logic, GAL, bipolar PLA, NMOS PLA, PAL 14L4, Xilinx logic cell array (LCA) – I/ O Block, Programmable interconnect, Xilinx , 3000 series and 4000 series FPGAs. Altera CPLDs, Altera FLEX 10K series PLDs.

Placement and routing: Mincut based placement, Iterative improvement placement, Routing, Segmented channel routing , Maze routing , Routability and routing resources , Net delays.

Introduction to VHDL : Digital system design process, Hardware simulation, Levels of abstraction, VHDL requirements, Elements of VHDL, Top down design VHDL operators, Timing, Concurrency, Objects and classes, Signal assignments, Concurrent and sequential assignments.

Structural, Data flow & Behavioral description of hardware in VHDL : Parts library, Wiring of primitives, Wiring of iterative networks, Modeling a test bench, Top down wiring components, Subprograms. Multiplexing and data selection, State machine descriptions, Open collector gates, Three state bussing, Process statement, Assertion statement, Sequential wait statements, Formatted ASCII I/O operations MSI based design.

Introduction to Verilog HDL : Lexical conventions, Data types, System tasks and Compiler Directives−Modules and Ports−Gate Level Modeling with Examples, Design options of Digital Systems, Hierarchical system design, ASIC designs, PLD modeling, CPLD and FPGA devices, Synthesis, Design flow of ASICs and FPGA based system, design environment and constraints logic synthesizers, Language structure synthesis, Coding guidelines for clocks and reset.

Text Books: 1. P.K. Chan & S. Mourad, Digital Design sing Field Programmable Gate Array, 1st Edition, Prentice Hall, 1994.2. J. V. Old Field & R.C. Dorf, Field Programmable Gate Array, John Wiley, 1995.3. M. Bolton, Digital System Design with Programmable Logic, Addison Wesley, 1990.Reference Books:4. Thomas E. Dillinger, VLSI Engineering, Prentice Hall, 1st Edition, 1998.5. Douglas Perry, VHDL, 3rd Edition, McGraw Hill 2001.6. J. Bhasker, VHDL, 3rd Edition, Addison Wesley, 1999.7. Ming-Bo Lin., Digital System Designs and Practices Using Verilog HDL and FPGAs, Wiley, 2008.8. Samir Palnitkar, Verilog HDL: A Guide to Digital Design and Synthesis, Pearson Education, 2005.


L T/D P C

3 0 0 3

EC853: MODELING OF ADVANCED DIGITAL SYSTEM DESIGN USING HDL (MAD-HDL)

(For M. Tech ECE (VLSI&ES) – I Semester)

5


Course objectives:1. To make students familiar with basic embedded systems and SOCs2. To make students familiar with processor organizations and memory overview.3. To make students understand Microcontrollers, RISC machines and ARM processors.4. To make students write programs in ALP.

Course Outcomes:1. Students will be able to understand embedded systems and SOCs2. Students will be able to write various programs in Assembly Language Programm3. Students will be able to use ARM processors in their projects and industry.

Introduction to embedded systems: Background and History of Embedded Systems, Definition and Classification, Programming languages for embedded systems, Desirable characteristics of programming languages for embedded systems, Low-level versus high-level languages, Main language implementation issues, Control, typing, Major programming languages for embedded systems, Embedded System on a Chip (SoC) and the use of VLSI designed Circuits.Processor and Memory Organization: Structural units in processor, Processor selection for an embedded system, Memory devices, Memory selection, Allocation for memory to program segments and blocks and memory map of a system, DMA, Interfacing processor, I/O Devices - Device I/O Types and Examples I/V Synchronous – ISO synchronous and Asynchronous Communications from Serial Devices, Examples of Internal Serial–Communication Devices – UART and HDLC, Parallel Port Devices, Sophisticated interfacing features in Devices/Ports- Timer and Counting Device

Microcontroller: Introduction to Microcontrollers, Microprocessors Vs Microcontrollers, PSoC and MCS – 5x Family Overview, Important Features, Architecture, Pin Functions, Architecture, Addressing Modes, Instruction Set, Instruction Types.

ARM Processor as System-on-Chip: Acorn RISC Machine, Architecture inheritance, ARM programming model, ARM development tools, 3 and 5 stage pipeline, ARM organization, ARM instruction execution and implementation, ARM Coprocessor Interface. ARM Assembly Language Programming: ARM instruction types, Data transfer, Data processing and control flow instructions, ARM instruction set, Coprocessor instructions. Architectural Support for High Level Language: Data types, Abstraction in Software design, Expressions, Loops, Functions and Procedures, Conditional Statements, Use of Memory.

Text Books: 1. Steve Furber, ARM System on Chip Architecture, 2nd Edition, Addison Wesley Professional, 2000.2. Ricardo Reis, Design of System on a Chip: Devices and Components, 1st Edition, Springer, 2004.3. Raj Kamal, Embedded Systems Architecture, Programming and Design, 2nd Edition, TMH, 2006.4. Jonathan W Valvano, Embedded Micro Computer Systems, Real Time Interfacing,1st Edition, Books / Cole,Thomson learning 2006.

Reference Books:5. Arnold S Burger, Embedded System Design An Introduction to Processes, Tools and Techniques, 1st Edition, CMP Books, 2007.6. David.E. Simon, An Embedded Software Primer,2nd Edition, Pearson Edition, 2009.7. Andrew N.sloss, Dominic Symes, Chris Wright, ARM System Developer’s guide,1st Edition, Elsevier Publications 2005.Note : The question paper shall consist of Eight questions out of which the student shall answer any Five questions

L T/D P C

3 0 0 3

EC854 ADVANCED EMBEDDED SYSTEMS -I ( AES – I )(For M. Tech ECE(VLSI&ES) – I Semester)

6

Scheme : 2013Internal Assessment : 50External : 50Exam Duration : 3 Hrs

1. Digital Circuits Description using Verilog and VHDL

2. Verification of the Functionality of Designed circuits using function Simulator.

3. Timing simulation for critical path time calculation.

4. Synthesis of Digital circuits

5. Place and Route techniques for major FPGA vendors such as Xilinx, Altera and Actel etc.

6. Implementation of Designed Digital Circuits using FPGA and CPLD devices.

7. Microcontroller programming using PSoC and MC- 5x seriesa) Toggling the LEDs,b) serial data transmission,c) LCD and Key pad interface

L T/D P C

3 0 0 3

EC855: ADVANCED VLSI AND EMBEDDED SYSTEMS LAB ( AVES(P) – I ) (For M. Tech ECE(VLSI&ES) – I Semester)

7

TWO YEAR M.TECH. DEGREE COURSEScheme of I nstruction and Examination


M.Tech - II Semester VLSI and Embedded Systems Scheme: 2013

S. NoCourse No. Course Title Credits


periods/week

Scheme of Examination

Maximum Marks

L T P End Exam

Internal Assessment Total

1 EC857 Algorithms for VLSI(AFV) 3 3 - – 70 30 100

2 EC858 Analog VLSI Design(AVLSI) 3 3 - – 70 30 100

3. EC859 Low Power VLSI Design(LVD) 3 3 - – 70 30 100

4 EC860 Advanced Embedded Systems – II(AES-II) 3 3 - – 70 30 100

5. Elective - II 3 3 - - 70 30 100

6. EC861 Advanced EDA Lab(EDAP) 2 – - 3 50 50 100

7. EC862 Seminar 1 - - - - 100 100

Total 18 15 - 3 400 300 700

8


Course Objectives:1. To make students familiar with various algorithms like partitioning, Floor planning, P&R

in VLSI.2. To make students familiar with logic simulation and verification.3. To make students familiar with Synthesis algorithms.4. To make students familiar with multi chip modules

Course Outcomes:1. Students will be able to understand various algorithms commonly used in VLSI.2. Students will be able to understand optimization for synthesis.3. Students will be able to understand latest trends in physical design like MCMs.

Basic Algorithms and Data structures : Data Structures and Basic Algorithms , Algorithmic Graph Theory and Computational complexity, Tractable and Intractable problems, General Purpose Methods for Combinational Optimization.

Partitioning, Floor planning, Placement & Routing Algorithms : Partitioning, Problem formulation, Classification of partitioning algorithms, Group migration algorithms, Simulated annealing and evolution, Performance driven partitioning, Floor planning and pin assignment, Problem formulation, Classification of floor planning algorithms, Classification of pin assignment algorithms, Placement, Problem formulation, Classification of placement algorithms, Simulation based placement, Partitioning based placement, Performance driven placement, Routing, Global routing, Problem formulation, Classification of global routing algorithms, Detailed routing, Problem formulation, Classification of detailed routing algorithms.

Simulation, Logic synthesis & Verification : Simulation, Different levels of simulation, Logic synthesis & Verification, Basic issues in combinational logic synthesis, Binary decision diagrams, ROBDD principles, Implementation and construction, Manipulation, Variable ordering, Applications to verification and combinatorial optimization.

High level synthesis & Compaction : Hardware models for high level synthesis, Internal representation of the input algorithm, Allocation, Assignment and scheduling, Compaction, Problem formulation, Classification of compaction algorithms, One dimensional compaction, One and a half dimensional compaction, Two dimensional compaction, Hierarchical compaction, Recent trends in compaction.

Physical Design Automation of FPGAs & MCMS : Physical Design Automation of FPGAs, FPGA technologies, Physical design cycle for FPGAs, Partitioning, Routing, Physical design automation of MCMS, MCM technologies, MCM Physical design cycle, Partitioning, Placement, Routing , VHDL, Verilog, Implementation of simple circuits using VHDL and Verilog.

Text Books:1. N.A.Sherwani, Algorithms for VLSI Physical Design Automation, 3rd Edition, Kluwer Academic, 1999.2. S.H.Gerez, Algorithms for VLSI Design Automation, John Wiley, 1998.


L T/D P C

3 0 0 3

EC857: ALGORITHMS FOR VLSI ( AFV )(For M. Tech ECE(VLSI&ES) – II Semester)

9


Course objectives:1. To make students familiar with advanced current mirrors and their behavior at high

frequency and low frequencies.2. To make students familiar with design of OP-AMPs, comparators in BiCMOS.3. To make students familiar with S&H, ADC,DAC etc..4. To give in detail view of filters used in sampling, Analog Multipliers.

Course Outcomes:1. Students will be able to design current mirrors and high impedence current mirrors.2. Students will be able to design Differential OP-AMP,S&H Circuits3. Students will be able to design analog multipliers and able to analyze their operation.

Basic current mirrors and single stage amplifiers: Simple CMOS current mirror, common source, Common gate amplifier with current mirror active load, Source flower with current mirror to supply bias current, High output impedance current mirrors and bipolar gain stages, Frequency response.

Operational amplifier design and compensation: Two stage CMOS operational amplifier, feedback and operational amplifier compensation, advanced current mirrors, Folded-cascode operational amplifier, Current mirror operational amplifier, Fully differential operational amplifier, common mode feedback circuits, Current feedback operational amplifier. Comparator, Charge injection error, Latched comparators, BiCMOS comparators.

Sample and hold and switched capacitor circuits: MOS, CMOS and BiMOS sample and hold circuits, Switched capacitor circuits, Basic operation and analysis first order and biquad filters, Charge injection, Switched capacitor gain circuit, Correlated double sampling techniques, Other switched capacitor circuits.

Data converters: Ideal D/A and A/ D converters, Quantization noise, Performance limitations. Nyquist rate D/A converters, Decoder based converters, Binary scaled converters, Hybrid Converters, Nyquist rate A/ D converters, Integrating, Successive approximation, Cyclic flash type, Two step interpolating, Folding and pipelined, A/D converters.

Over sampling converters and filters: Over sampling with and without noise haping, Digital decimation filter, High order modulators, Band pass over sampling converters, Practical Considerations, Continuous time filters, Mixers, PLLs, Multipliers.

Text Books: 1. Paul.R. Gray & Robert G. Major, Analysis and Design of Analog Integrated Circuits, John Wiley & sons, 2004.2. David Johns, Ken Martin, Analog Integrated Circuit Design, John Wiley & sons. 2004.

Reference Books: 3. Behzad Razavi, Design of Analog CMOS Integrated Circuits, Tata Mc Grah Hill. 2002.4. Jacob Baker.R.et.al., CMOS Circuit Design, IEEE Press, Prentice Hall, India, 2000.5. Mohamed Ismail, Analog VLSI , Mc Graw hill, 1st Edition, 1994.


L T/D P C

3 0 0 3

EC858: ANALOG VLSI DESIGN (AVLSI)(For M. Tech ECE(VLSI&ES) – II Semester)

10


Course Objectives:1. Students will be able to understand various types of power dissipation in CMOS.2. Students will be able to estimate power.3. Students will be able to reduce the power for the given circuits in CMOS.

Course Outcomes:1. Students will be able to estimate different powers in CMOS2. Student will be able to minimize static, dynamic power dissipation.3. Students will be able to minimize power for software design like ARM,XILINX etc..

Introduction and need of low power design: Sources of power dissipation, MOS transistor leakage components, SOI technology, Fin FET, Back gate FET, Power and energy basics, Power dissipation in CMOS circuits, Energy–delay product as a metric, Design strategies for low power.

Power Estimation Techniques: Circuit Level, Modeling of Signals, Signal Probability Calculations, Statistical techniques, High Level Power Analysis, RTL Power Estimation, Fast Synthesis, Analytical Approaches, Architectural Power Estimation.

Power Optimization Techniques – I: Dynamic Power Reduction, Dynamic Power Component, Circuit Parallelization, Voltage Scaling Based Circuit Techniques, Circuit Technology-Independent Power Reduction, Circuit Technology Dependent Power Reduction, Leakage Power Reduction, Leakage Components, Design Time Reduction Techniques, Run-time Stand-by Reduction Techniques, Run-time Active Reduction Techniques Reduction in Cache Memories.

Power Optimization Techniques – II: Low Power Very Fast Dynamic Logic Circuits, Low Power Arithmetic Operators, Energy Recovery Circuit Design, Adiabatic, Charging Principle and its implementation issues.

Software Design for Low Power: Sources of Software Power Dissipation, Software Power Estimation, Software Power Optimizations, Automated Low-Power Code Generation, Co-design for Low Power.

Text Books: 1. Kaushik Roy and Sharat Prasad, Low-Power CMOS VLSI Circuit Design, Wiley Inter-science Publications, 2000.2. Christian Piguet, Low Power CMOS Circuits Technology, Logic Design and CAD Tools, 1st Indian Reprint, CRC Press, 2010.

Reference Books: 3. J. Rabaey, Low Power Design Essentials, 1st Edition, Springer Publications, 2010.


L T/D P C

3 0 0 3

EC859: LOW POWER VLSI DESIGN ( LVD) (For M. Tech ECE(VLSI&ES) – II Semester)

11


Course Objectives:1. Students will be exposed to UNIX,POSIX,UNIX Kernel etc….2. Students will be able to understand RTOS and their types.3. Students will be able to understand embedded OS like VX works

Course Outcomes:1. Students will be able to work with Micro vision,keil programs.

2. Students will be able to work with RTOS, and can be programmed with VX WORK

Brief Review of Unix Operating Systems: (Unix Kernel, File system, Concepts of, Process, Concurrent Execution & Interrupts. Process Management, forks & execution. Programming with system calls, Process Scheduling, Shell programming and filters), Portable Operating System Interface (POSIX), IEEE Standard 1003.13 & POSIX real time profile, POSIX versus traditional Unix signals, Overheads and timing predictability.

Hard versus Soft Real-time systems: examples, Jobs & Processors, Hard and Soft timing constraints, Hard Real-time systems, Soft Real-time systems. Classical Uniprocessor Scheduling Algorithms, RMS, Preemptive EDF, Allowing for Preemptive and Exclusion Condition.

Concept of Embedded Operating Systems: Differences between Traditional OS and RTOS. Realtime System Concepts, RTOS Kernel & Issues in Multitasking, Task Assignment, Task Priorities, Scheduling, Intertask Communication & Synchronization, Definition of Context Switching, Foreground ISRs and Background Tasks. Critical Section, Reentrant Functions, Interprocess Communication (IPC), IPC through Semaphores, Mutex, Mailboxes, Message Queues or Pipes and Event Flags.

VxWorks: POSIX Real Time Extensions, timeout features, Task Creation, Semaphores (Binary, Counting), Mutex, Mailbox, Message Queues, Memory Management, Virtual to Physical Address Mapping.

Debugging Tools and Cross Development Environment: Software Logic Analyzers, ICEs. Comparison of RTOS, VxWorks, μC/OS-II and RT Linux for Embedded Applications.

Text Books: 1. Jane W.S.Liu, Real Time Systems, Pearson Education, Asia, 2011.2. Betcnhof, D.R., Programming with POSIX threads, Addison - Wesley Longman, 1997.

Reference Books: 3. Wind River Systems, VxWorks Programmers Guide, Wind River Systems Inc.1997.4. Jean.J.Labrosse, MicroC/OS-II, 2nd Edition,Elsevier, 2012, CMP Books.5. Real Time Systems, C.M.Krishna and G.Shin, McGraw-Hill Companies Inc., McGraw Hill International Editions, 1997.


L T/D P C

3 0 0 3

EC860: Advanced Embedded Systems - II ( AES – II )(For M. Tech ECE(VLSI&ES) – II Semester)

12

Scheme : 2013Internal Assessment : 50End Exam :50Exam Duration : 3 Hrs

LIST OF EXPERIMENTS

1. Layout Extraction for Analog & Mixed Signal Circuits.

2. Analog Circuit simulation using Mentor Graphics Suit

3. Verification of layouts (DRC, LVS)

4. Back annotation

5. Parasitic Values Estimation from Layout.

6. Design Rule Checks

7. Programming using real time operating systems

a). Multi tasking using round robin scheduling

b). IPC using message queues

c). IPC using semaphore

d). IPC using mail box

L T/D P C

0 0 3 2

EC861: ADVANCED EDA LAB ( EDA(P) ) (For M. Tech ECE(VLSI&ES) – II Semester)

13



M.Tech - III Semester VLSI and Embedded Systems Scheme: 2013

S. No. Course No. Course Title Credits


periods/weekScheme of Examination

L T PEnd

Exam Marks

Internal Assessment Marks

Total Marks

1. EC951 Electronic Design Automation Tools(EDAT) 3 3 - - 70 30 100

2. Elective –III 3 3 - - 70 30 100

3. Elective-IV 3 3 - - 70 30 100

4. EC952 Dissertation Phase-1 6 - - - 50 50 100

TOTAL 15 9 - - 260 140 400

14


Course Objectives:

1. Students will be exposed to complete Frontend and Backend tools.

2. Students will be exposed to simulation of the analog circuits using spice.

3. Students will be exposed to System C constructs.

Course Outcomes:

1. Students will be able to utilize EDA tools in their projects.2. Students will be able to understand industry standard tools.

3. Students will be able to understand Mixed signal design In AMS.

An overview of OS commands: System settings and configuration. Introduction to Unix commands. Writing Shell scripts. VLSI design automation tools.An overview of the features of practical CAD tools. Modelsim, Leonardo spectrum, ISE 8.1i, Quartus II, VLSI backend tools.

Synthesis and simulation using HDLs: Logic synthesis using verilog and VHDL. Memory and FSM synthesis. Performance driven synthesis, Simulation- Types of simulation. Static timing analysis. Formal verification. Switch level and transistor level simulation.

Circuit simulation using Spice: - Circuit description. AC, DC and transient analysis. Advanced spice commands and analysis. Models for diodes, transistors and opamp. Digital building blocks. A/D, D/A and sample and hold circuits. Design and analysis of mixed signal circuits.

MSCM: Mixed signal circuit modeling and analysis using VHDL –AMS,

System design using systemC: - SystemC models of computation. Classical hardware modeling in system C. Functional modeling. Parametrized modules and channels. Test benches. Tracing and debugging.

Text books:

1. M.J.S.Smith, Application Specific Integrated Circuits,Pearson,20022. M.H.Rashid, Spice for Circuits and Electronics using Pspice. (2/e), PHI.

Reference Books:

3. T. Grdtker et al , System Design with SystemC, Kluwer, 2004.4. P.J. Ashenden et al , The System Designer’s Guide to VHDL-AMS, Elsevier, 2

Note : The question paper shall consist of Eight questions out of which the student shall

L T/D P C

3 0 0 3

EC951: ELECTRONIC DESIGN AUTOMATION TOOLS(EDAT) (For M. Tech ECE(VLSI&ES) – III Semester)

15

answer any Five questions

List of Subjects for Electives

Description Subject title Code

Elective-I

CPLD/FPGA Design (FPGA) EC863

Scripting Languages for VLSI Design Automation ( SLA ) EC864

VLSI Architectures (VLSIA ) EC865

Electromagnetic Interference/ Compatibility(EMI/C) EC866

Elective II

Advanced Digital Signal Processors(ADSP’s) EC867

Neural Networks and Fuzzy Logic (NNFL) EC868

Advanced Computer Architecture(ADCA). EC869

Analysis and Design of Digital Integrated Circuits (ADDIC) EC870

Elective III

Application Specific Integrated Circuits (ASIC) EC954

Semiconductor Physics and processing(SPP) EC955

System Modeling and Simulation(SMS) EC956

Micro Electro Mechanical Systems. (MEMS) EC957

Elective IV

VLSI Signal Processing ( VS ) EC958

VLSI System Design for Testing (VDFT) EC959

Nano Electronics ( NE ) EC960

Design Of Semiconductor Memories(DSM) EC961

16


Course Objectives:1. Students exposed to various architectures of CPLDs and FPGAs like XILINX2. Students will be able to understand Physical design of FPGAs3. Students will be able to understand Floor Planning,P&R for XILINX,ALTERA etc…

Course Outcomes:

1. Students will be able to design their projects utilizing various FPGAs and CPLDs

2. Students will get exposure to industry standard FPGAs like XILINX,ALTERA etc..

3.Students will efficiently P&R in their sub modules of project

CPLD: Programmable logic, Programmable read only memory (PROM), programmable logic array (PLA), Programmable array logic (PAL). Sequential programmable logic devices (SPLDS), Programmable gate arrays (PGAS), CPLD.FPGA: Programmable logic FPGA, Configuration logic blocks, Function Generator, ROM implementation, RAM implementation, time skew buffers, FPGA Design tools, Network-on-chip, Adaptive System-on-chip, AES ASIC Implementation, Advanced FPGA Design

FPGA logic cell for XILINX, ALTERA and ACTEL ACT: Technology trends, AC/DC IO Cells, Clock and power inputs, FPGA interconnect: Routing resources, Elmore’s constant, RC delay and parasitic capacitance FPGA design flow, Low level design entry.

FPGA physical design: CAD tools, Power dissipation, FPGA Partitioning, Partitioning methods.Floor planning: Goals and objectives, I/O, Power and clock planning, Floor Planning tools.

Placement: Goals and objectives, Placement algorithms, Min-cut based placement, Iterative Improvement and simulated annealing, Routing, introduction, Global routing, Goals and objectives, Global routing methods, Back-annotation, Detailed Routing, Goals and objectives, Channel density, Segmented channel routing, Maze routing, Clock and power routing, Circuit extraction and DRC.

Verification and Testing: Verification, Logic simulation, Design validation, Timing verification, Testing Concepts, Failures, Mechanism and faults, Fault coverage, ATPG methods, Design for testability, Scan Path Design, Boundary Scan design, BIST Design guidelines, Design of a Testing machine.

Text Books: 1. Pak and Chan, Samiha Mourad, Digital Design using Field Programmable Gate Arrays, 1st Edition Pearson Education, 2009.2. Michael John Sebastian Smith, Application specific Integrated Circuits, 3rd Edition, Pearson Education Asia, 2001.Reference Books:3. S. Trimberger, Edr, Field Programmable Gate Array Technology, 1st Edition Kluwer Academic Publications,1994.4. John V.Oldfield, Richard C Dore, Field Programmable Gate Arrays, 1st Edition,Wiley Publications, 1999.5. S. Brown, R. Francis, J. Rose, Z.Vransic, Field Programmable Gate array, 1st Edition, Kluwer Publications, 1992.Note : The question paper shall consist of Eight questions out of which the student shall answer any Five questions

L T/D P C

3 0 0 3

EC863: CPLD’S AND FPGA DESIGN (FPGA) (Elective –I for M. Tech ECE(VLSI&ES) – I Semester)

17


Course Objectives:1. Students will be able to learn concepts of scripting languages in VLSI like PERL2. Students will be able get overview of subroutines, Threads etc..3. Students will be able to get exposure to other scripting languages like SKILL,

Java ScriptCourse Outcomes:

1. Students are capable of scripting the given code in HDLs.2. Students will get benefit of using Scripting languages in their projects.3. Students will get scope for learning Java Script, SKILL etc…

Overview of scripting languages: PERL, File handles, Operators, Control structures, Regular expressions, Built in data types, Operators, Statements and declarations- simple, Compound, Loop statements, Global and scoped declarations.

Pattern matching: Regular expression, Pattern matching operators, Character classes, Positions, capturing and clustering.

Subroutines: Syntax, Semantics, Proto types, Format variables, References, Data structures, Arrays of arrays, Hashes of arrays, Hashes of functions, Inter process communication, Signals, Files, Pipes, sockets.

Threads: Process model, Thread model, Perl debugger, Using debugger commands, Customization, Internals and externals, Internal data types, Extending perl, embedding perl, Exercises for programming using perl.

Other languages: Broad features of other scripting languages SKILL, CGI, java script, VB script.

Reference Books: 1. Larry Wall, Tom Christiansen, John Orwant, Programming perl, 3rd Edition, Oreilly publications. 2. Randal L, Schwartz Tom Phoenix, Learning PERL, Oreilly publications


L T/D P C

3 0 0 3

EC864: SCRIPTING LANGUAGES FOR VLSI DESING AUTOMATION (SLA) (Elective-I for M. Tech ECE(VLSI&ES) – I Semester)

18


Course Objectives:

1. Students will be able to understand processor architectures like RISC and CISC.2. Students will be able to understand DSP processors like TMS 320 c54x,TMS 320

c6711 etc..3. Students will learn Pipelining and Super scalar processors

Course outcomes:1. Students will be in position to choose processor architecture for their projects.2. Students will be able to work with DSP processors and understand MAC

architecture.3. Students will be able learn advanced concepts in super scalar architectures.

Complex Instruction Set Computers (CISC): Instruction Set, Characteristics and Functions, Addressing Modes, Instruction Formats, Architectural Overview, Processor Organization, Register Organization, Instruction Cycle, Instruction Pipelining, Pentium Processor, PowerPC Processor.

Reduced Instruction Set Computers (RISC): Instruction execution Characteristics, Register Organization, Reduced Instruction Set, Addressing Modes, Instruction Formats, Architectural Overview, RISC Pipelining, Motorola 88510, MIPS R4650, RISC Vs. CISC.

DSP Processors: Instruction Set, Addressing Modes, Instruction Formats, Architectural Overview.

Pipeline Processing: Basic Concepts, Classification of Pipeline Processors, Instruction and Arithmetic Pipelining, Design of Pipelined Instruction Units, Pipelining Hazards and Scheduling, Principles of Designing Pipelined Processors.

Super scaler Processors: Overview, Design Issues, PowerPC, Pentium.

Text Books:1. B.Venkatramani & M.Baskar, Digital Signal Processor, McGraw Hill, 20002. Avatar Singh and S.Srinivasan, Digital signal processing, Thomson Books, 2004

Reference Books:

3. K.Hwang & F.A.Briggs, Computer Architecture and Parallel Processing, Mc Graw Hill.4. J.P.Hayes, Computer Architecture and Organization, Mc Graw Hill.5. Dezso Sima, Terence Fountain, Peter Kacsuk, Advanced Computer Architectures-A Design6. Space Approach, Addison-Wiley.


L T/D P C

3 0 0 3

EC865: VLSI ARCHITECTURES (VLSIA ) (Elective-I for M. Tech ECE(VLSI&ES) – I Semester)

19

7.


Course Objectives:1. Students will be able to get the interference of EM waves in I.C.s2. Students will be able to get concepts of standards used in I.C.s like MIL,Civilian

Standards3. Students will be able to get PCB traces and cross talk.

Course outcomes:1. Students are in a position to calculate interference effects of I.C.s2. Students will get scope to learn Military standards,Civilian standards.3. Students will get problematic approach to solve mismatching in I.C.s with environment

EMI/ EMC concepts and definitions: Sources of EMI, Conducted and radiated EMI, Transient EMI, Time domain Vs Frequency domain EMI, Units of measurement parameters, Emission and immunity concepts, ESD.

Conducted, Radiated and Transient Coupling: Common Impedance Ground Coupling, Radiated Common Mode and Ground Loop Coupling, Radiated Differential Mode Coupling, Near78 Field Cable to Cable Coupling, Power Mains and Power Supply coupling.

Civilian standards: FCC, CISPR, IEC, EN, Military standards, MIL STD 461D/462, EMI Test Instruments/ Systems, EMI Shielded Chamber, Open Area Test Site, TEM Cell, Sensors/ Injectors/ Couplers, Test beds for ESD and EFT.

Shielding, Filtering: Grounding, Bonding, Isolation Transformer, Transient Suppressors, Cable Routing, Signal Control, Component Selection and Mounting.

PCB Traces Cross Talk: Impedance Control, Power Distribution Decoupling, Zoning, Motherboard Designs and Propagation Delay Performance Models.

Text Books: 1. V.P.Kodali, Engineering EMC Principles, Measurements and Technologies, IEEE Press, 19962. Henry W.Ott, Noise Reduction Techniques in Electronic Systems, John Wiley and Sons, NewYork.

1988

Reference Books:

3. C.R.Paul, Introduction to Electromagnetic Compatibility, John Wiley and Sons, Inc, 19924. Bernhard Keiser, Principles of Electromagnetic Compatibility, Artech house, 3rd Edition, 1986


EC867: ADVANCED DIGITAL SIGNAL PROCESSORS (ADSP’s)

L T/D P C

3 0 0 3

EC866: ELECTRO MAGNETIC INTERFERENCE/ COMPATIBILITY(EMI/C)(Elective-I for M. Tech ECE(VLSI&ES) – I Semester)

20

(Elective-II for M. Tech ECE(VLSI&ES) – II Semester)


Course Objectives:1. Students will be able to learn different architectures for FIR&IIR filters.2. Students will be able to learn Radix-N DIT/DFT3. Students will be able to learn Super Scalars and DSP processors.

Course Outcomes:1. Students will learn algorithms in DSP advanced level2. Students will understand Radix-N architectures in their projects.3. Students will be able to use various DSP architectures in their designs.

Filters: Structures for FIR filters, Structures for IIR filters, Effects of coefficient quantization and round off noise, Designing techniques for IIR, Transformation from Analog filters, Computer aided design, Designing techniques for FIR filters, windowing, Frequency sampling and optimum approximation

DFT: Radix-2, Radix-4 and composite Radix DIT and DIF algorithms, Applications of DFT to real time DSP

Multirate Signal Processing: Mathematical description of change of sampling rate, Interpolation and Decimation, Continuous time model, Direct digital domain approach, Decimation by an integer factor D Interpolation by an integer factor I, Single and multistage realization, Poly phase realization, Application to sub band coding, Wavelet transform and filter bank implementation of wavelet expansion of signals.

DSP Architecture and Processors: Architectures-VanNuemann, Harward, VLIW (Very Long Instruction Word), SIMD (Single Instruction and Multiple Word), Super Scalar, Hardware-Loops, Circular Buffers.

Optimizations: Software Pipelining, Loop-unrolling, Overall mapping of DSP algorithms to architectures.

Text Books:1. John G.Proakis, Dimitris G.Manolakis, Digital Signal Processing, Prentice Hall of India.2. Monson H.Hayes, Statistical Digital Signal Processing and Modeling, John Wiley and Sons,

Inc.,3. Sopocles J. Orfanidis, Optimum Signal Processing, McGraw Hill.

Reference Books:4. Simon Haykin, Adaptive Filter Theory.5. Simon Haykin, Advanced Digital Signal Processing.6. Emmanuel C.Ifeachor, Barrie W.Jervis, Digital Signal Processing: A Practical Approach, 2nd

Edition, Printice Hall.7. Texas Instruments Technical Reference Manual.


L T/D P C

3 0 0 3

EC868: NEURAL NETWORKS AND FUZZY LOGIC (NNFL) (Elective –II for M. Tech ECE(VLSI&ES) – II Semester)

21


Course Objectives:1. Students will be able to learn neuron functionality.2. Students will be able to learn statistical methods in neural network applications.3. Students will be able to learn memory techniques in fuzzy logic.

Course Outcomes:1. Students will be able to get basic concepts of biological neurons.2. Students will be able to understand network configurations in neural networks.3. Students will be able to get theoretical approach of designing memories in neural

networks.Biological Neural Network: Organisation of human brain, Neuron functions-cell body, Dendrites, Axon, Cell membrane, Computers and human brains.

Artificial Neural Networks: Characteristics, Single layer and multi-layer Artificial Neural Networks, Training, Objective, Supervised and unsupervised training, Overview.

Perceptrons: Perceptron representation, Learning, Training algorithm, Advanced algorithms and applications.

Neural Dynamics: Counters propagation Networks, Introduction, Network structure, Normal operation, training the Kohonen and Grossberg layers, Full counter propagation network, Applications.

Statistical Methods : Training, Applications, Applications to non-linear optimisation problems, Back propagation and Cauchy training.

Hopfield Networks : Recurrent network configurations, Applications.

Bi-directional Associative Memories : BAM structure, Retrieving a stored association, Encoding the associations, Memory capability, Continuous, Adaptive and competitive BAM.

Adaptive Resonance Theory: ART architecture and implementation training example, Characteristics.

Introduction to Fuzzy Systems: Crisp sets, Notation, Basic concepts, Classical logic, Fuzzy logic, Fuzzy operations, Complement, Union and Intersection. Fuzzy Relations: Binary relations, Equivalence and Similarity relations, Compatibility relation, Orderings, Morphisms.

Fuzzy Measures: Belief and plausibility measures, Probability measures, Possibility and necessity measures.Fuzzy Associative Memories: Fuzzy and Neural function estimators, Neural vs Fuzzy representation of structured knowledge, FAMs as mappings, Fuzzy hebb FAMs, The Bi-directional FAM, Theorem, Superimposing FAM rules, FAM system Architecture.

Text Books:1. Phillip D. Wasserman , Van Nostrand Reinhold, Neural Computing, Theory and Practice.

Reference Books: 2. George I Klir and Tina A. Folger, Fuzzy sets, uncertainty and Information, PHI. 3. Bart Kosko, Neural Networks and Fuzzy Systems, PHI.

Note : The question paper shall consist of Eight questions out of which the student shall answer any Five questions The question paper shall consist of EIGHT questions out of which the student shall

L T/D P C

3 0 0 3

EC869: ADVANCED COMPUTER ARCHITECTURE (ADCA). (Elective-II for M. Tech ECE (VLSI&ES) – II Semester) 22

answer any FIVE questions


Course Objectives:1. To make students familiar with pipeline and vector processing in system design.2. To make students familiar with memory organization and optimization.

3. To make students familiar with Dennis and Arvind machinesCourse Outcomes:

1. Students will get scope to analyze architecture design related to VLSI sub system.2. Students will be able to organize memory for optimum use.3. Students will be in a position to map algorithms in VLSI arrays.

Pipeline and Vector Processor: Analogy with assembly line, Linear pipeline speed up, Efficiency and throughput, Instruction pipeline, Arithmetic pipeline, CSA tree, Nonlinear pipeline, Principles of designing pipeline processors, Job scheduling, Characteristics of vector processing, Pipelined vector processing.

Array processors: SIMD array processor organization, Masking and data routing mechanism, Interconnection network classifications, Mesh, Cube, Barrel shifter networks, Parallel algorithms, Matrix multiplication, Summation of vector elements, Polynomial evaluation, FFT, Parallel sorting.

Multiprocessor Systems: Loosely coupled and tightly coupled organizations, interconnection networks, Common-bus, Cross-bar, Banyan, Delta networks, Language features for parallel processing FORK-JOIN and other concepts, MPS operating system.

Advanced memory organization: Virtual memory concept paging, Segmentation, Paging algorithms, Cache memory organization, C.S.C/S access schemes and Multi-port memory organization.

Data-flow Computers and VLSI computing Structures: Data-driven computation, Data flow machine architectures, Data flow graphs and languages, Dennis machine and Arvind machine, VLSI computing structure attributes, Systolic array, Mapping algorithms into VLSI arrays, Re configurable processor array, VLSI matrix arithmetic processor.

Text Books :1. K.Hwang & F.A.Briggs, Computer Architecture and Parallel Processing, Mc Graw Hill.2. J.P.Hayes, Computer Architecture and Organization, Mc Graw Hill.Reference Books:3. Dezso Sima, Terence Fountain, Peter Kacsuk, Advanced Computer Architectures-A Design Space

Approach, Addison-Wesley.


EC870: ANALYSIS AND DESIGN OF DIGITAL INTEGRATED CIRCUITS (ADDIC)

L T/D P C

3 0 0 3

23

(Elective-II for M. Tech ECE (VLSI&ES) – II Semester)


Course Objectives:1. To make Students familiar with sub blocks in digital system2. To make students familiar with State machines and their coding techniques.

Course Outcomes:1. Students will be able to implement their projects in State machines 2. Students will get insight into Topdown Design methodologies.

Building blocks for digital design: multiplexer, Demultiplexer, Decoder, Encoder, Comparator, adders, Building blocks with memory, Clocked building blocks, Register-building blocks, RAM, ROM, PLA, PAL.

Hardware description languages: Hierarchical modeling concepts, Modules, Module instances, design and stimulus blocks: gate level, Data flow, Behavioral modeling techniques (vhdl & verilog), Switch level modeling, Delays.

Emitter coupled logic gates: Emitter coupled differential pairs, Terminating emitter coupled logic, temperature sensitivity, Current mode logic gates, Current mode logic latches.

Differential CMOS circuits: Static CMOS digital latches, Static random-access memory cell, D-RAM cell, Dynamic CMOS latches, Synchronous system design techniques, Gray, Code counter, BiCMOS logic gates, Pseudo, NMOS and dynamic pre-charging. Domino- CMOS logic, No race logic, Single-phase dynamic logic, Differential CMOS logic, Dynamic differential logic.

Top down design: Finite state machine (FSM), Case studies(traffic signal controller), Synchronization failure and meta stability, Algorithmic state machines (ASMs), Synthesis and test benches- using vhdl & verilog.

Text Books:1. Ken Martin, Digital Integrated Circuit Design, Oxford University Press 2000.2. John F Wakerly, Digital Design Principles & Practices, 3rd Edition, Pearson Education & Xilinx Design Series, 2002.Reference Books:3. Samir Palnitkar, Verilog HDL- A Guide to Digital Design and Synthesis, Prentice Hall India, 2000.4. Prosser and Winkel, The Art of Digital Design, Prentice Hall, 1994.


L T/D P C

3 0 0 3

24


Course Objectives:

1. To make students familiar with types of ASIC like XILINX, ALTERA etc...2. To make students familiar with different types of ASIC architecture.3. To make students familiar with system partitioning, routing and design checks.4. To make students familiar with planar subset problem.

Course Outcomes:1. Students will get scope to analyze various ASICs including their P&R2. Students will be able to design and analyze memory architectures.3. Students will be able to understand in detailed view of MCM.

Types of ASICs : Design flow, CMOS transistors CMOS Design rules, Combinational Logic Cell, Sequential logic cell, Data path logic cell, Transistors as Resistors, Transistor Parasitic Capacitance, Logical effort, Library cell design, Library architecture .

Anti fuse - Static RAM: EPROM and EEPROM technology, PREP benchmarks, Actel ACT - Xilinx LCA, Altera FLEX, Altera MAX DC & AC inputs and outputs, Clock and Power inputs, Xilinx I/O blocks.

Actel ACT -Xilinx LCA - Xilinx EPLD, Altera MAX 5000 and 7000, Altera MAX 9000, Altera FLEX, Design systems, Logic Synthesis, Half gate ASIC, Schematic entry, Low level design language, PLA tools, EDIF- CFI design representation.

ASIC Construction: Physical Design, System Partitioning, FPGA Partitioning, Partitioning Methods, Floorplanning and Placement, Physical Design Flow, Routing Global Routing , Detailed Routing, Special Routing. Design checks.

Planar subset problem(PSP): Single layer global routing, Single layer detailed routing, Wire length and bend minimization technique-Over the cell(OTC) Routing, Multichip modules(MCM), Programmable logic arrays, Transistor chaining, Weinberger Arrays, Gate Matrix Layout-1D compaction-2D compaction.

Text Books:1. M.J.S .Smith, Application Specific Integrated Circuits, 1st Edition, Addison - Wesley Longman Inc.,

19972. Farzad Nekoogar and Faranak Nekoogar, From ASICs to SOCs: A Practical Approach, 1st Edition,

Prentice Hall PTR, 2003.Reference Book:3. Sarrafzadeh & Wong, An Introduction to VLSI Physical Design, 1st Edition,McGraw Hill,1996.


L T/D P C

3 0 0 3

EC954: APPLICATION SPECIFIC INTEGRATED CIRCUITS (ASIC) (Elective-III for M. Tech ECE(VLSI&ES) – III Semester)

25


Course Objectives:1. To make students familiar with semiconductor physics.2. To make students familiar with fabrication of CMOS ,BiCMOS technologies.3. To make students familiar with IC packaging techniques

Course Outcomes:1. Students will get clear idea of device physics and their properties.2. Students will get familiar with various fabrication techniques and memory techniques.3. Students will be able get packaging techniques used in CMOS.BiCMOS

Introduction to semiconductor devices: Introduction- material conductivity, Quantum mechanics, energy bands, Crystalline structures, Density of states, Band structures, Fermi - Dirac function, Material classification, Band structure, Electrons and holes, Doping, Scattering, Mobility, Diffusion transport, Einstein relation, Carrier generation and recombination, Continuity equation.

Crystal Growth, Wafer Preparation, Epitaxy and Oxidation : Review of Semiconductor theory, Electronic Grade Silicon, Czochralski Crystal Growing, Silicon Shaping Processing consideration, Vapor Phase Epitaxy, Molecular Beam Epitaxy, Silicon on Insulators, Epitaxial Evaluation, Growth Mechanism and Kinetics, Thin Oxides, Oxidation Techniques and Systems, Oxide Properties.

Lithography and Relative Plasma Etching: Optical Lithography, Electron Lithography, X-Ray Lithography, Ion Lithography Plasma, Properties, Feature Size, Control and Anisotropic Etch Mechanism, Relative Plasma Etching Techniques and Equipments.

Deposition, Diffusion, Ion Implementation And Metallization: Deposition Processes, Polysilicon, Plasma Assisted Deposition, Models of Diffusion in Solids, Fick’s One Dimensional Diffusion Equation, Atomic Diffusion Mechanism, Measurement Techniques, Range Theory, Implantation Equipment, Annealing Shallow Junction, High Energy Implantation, Physical Vapor Deposition, Patterning.

VLSI Process Integration, Analytical, Assembly Techniques And Packaging Of VLSI Devices : NMOS IC Technology, CMOS IC Technology, MOS Memory IC Technology, Bipolar IC Technology, IC Fabrication, Analytical Beams, Beams Specimen Interaction, Chemical Methods, Package Types baking Design Considerations, VLSI Assembly Technology, Package Fabrication Technology.

Text Books:1. S.M.Sze, VLSI Technology, 2nd Edition, McGraw-Hill, 19882. Duoglas A Pucknell and Kamaran Eshragian, Basic VLSI design, 3rd Edition, PHI, 1994.

Reference Book:3. Wayne wolf, Modern VLSI Design, 2nd Edition, Prentice Hall Ptr, 1998.


L T/D P C

3 0 0 3

EC955: SEMICONDUCTOR PHYSICS AND PROCESSING (SPP) (Elective-III for M. Tech ECE (VLSI&ES) – III Semester)

26


Course Objective:1. To make students familiar with types of simulation2. To make students familiar with state machines and markov process3. to make students familiar with Alpha/beta trackers.

Course Outcome:1. Students will be able to work with different packages and simulation 2. Students will be able to work with Poisson process in real time3. Students will be able to model and simulate models.

Basic Simulation Modeling, Systems; Models and Simulation, Discrete Event Simulation, Simulation of single server queing system, Simulation of Inventory System, Alternative approach to modeling and simulation.

Simulation Software: Comparison of simulation packages with Programming languages, Classification of Software, Desirable Software features, General purpose simulation packages, Arena, Extend and others, Object Oriented Simulation, Examples of application oriented simulation packages.

Building Simulation Models: Guidelines for determining levels of model detail, Techniques for increasing model validity and credibility.

Modeling Time Driven Systems: Modeling input signals, delays, System integration, Linear Systems, Motion control models, Numerical Experimentation.

Exogenous Signals And Events: Disturbance signals, State Machines, Petri Nets and Analysis, System encapsulation.

Markov Process: Probabilistic systems, Discrete Time Markov processes, Random walks, Poisson processes, the exponential distribution, simulating a poison process, Continuous-Time Markov processes.

Event Driven Models: Simulation diagrams, Queing theory, simulating queing systems, Types of Queues, Multiple servers.

System Optimization: System Identification, Searches, Alpha/beta trackers, Multidimensional Optimization, Modeling and Simulation methodogy.

Text Books1. Frank L. Severance, System Modeling & Simulation, An Introduction, John Wiley & Sons.Reference Book:2. Averill M. Law, W. David Kelton, Simulation Modeling and Analysis, 3rd Edition, TMH.3. Geoffery Gordon, Systems Simulation, PHI.


L T/D P C

3 0 0 3

EC956: SYSTEM MODELING AND SIMULATION (SMS) (Elective-III for M. Tech ECE (VLSI&ES) – III Semester)

27


Course Objective:1. To make students familiar with cutting edge MEMS technology2. To make familiar with digital & analog circuitry in MEMS3. To make students familiar with silicon based MEMS

Course Outcome:1. Students will be able to design Basic &Complex circuits in MEMS.2. Students will be able to design 2-terminal MEMS for project works.3. Students will get industry standard Silicon based technologies in MEMS.

Introduction, Basic Structures of MEM Devices: (Canti Levers, Fixed Beams diaphragms).Broad Response of MEMS to Mechanical (force, pressure etc.) Thermal, Electrical, Optical andMagnetic stimuli, Computability of MEMS with VLSI Applications in Electronics, Broad Advantages and Disadvantages of MEMS from the point of Power Dissipation, Leakage etc.

Review of Mechanical Concepts: Stress, Strain, Bending Moment, Deflection Curve, Differential equations describing the Deflection under Concentrated Force, Distributed Force, Deflection Curves for Canti-Levers, Fixed beam, Electrostatic Excitation, Columbic Force between the Fixed and Moving Electrodes, Deflection with voltage in C.L, Deflection Vs Voltage Curve, Critical Deflection, Description of the above w.r.t Fixed Beams, Fringe Fields, Field Calculations using Laplace Equation, Discussion on the Approximate Solutions, Transient response of the MEMS.

Two Terminal MEMS : Capacitance Vs Voltage Curve, Variable Capacitor, Applications of Variable Capacitors, Two Terminal MEM Structures, Three Terminal MEM structures, Controlled Variable Capacitors, MEM as a Switch and Possible Applications.

MEM Circuits & Structures for Simple GATES : AND, OR, NAND, NOR, Exclusive OR, Simple MEM Configurations for Flip-Flops Triggering, Applications to Counters, Converters, Applications for Analog Circuits like Frequency Converters, Wave Shaping. RF Switches for Modulation, MEM Transducers for Pressure, Force Temperature, Optical MEMS.

MEM Technologies: Silicon Based MEMS : Process Flow , Brief Account of Various Processesand Layers like Fixed Layer, Moving Layers, Spacers etc., Etching Technologies, Metal BasedMEMS, Thin and Thick Film Technologies for MEMS, PROCESS flow and Description of theProcesses, Status of MEMS in the Current Electronics scenario.Text Books:1. Gabriel.M. Reviez, R.F. MEMS Theory, Design and Technology, Jhon Wiley & Sons, 2003.2. Thimo Shenko, Strength of Materials, CBS Publishers & Distributors.Reference Books:3. K. Pitt, M.R. Haskard, Thick Film Technology and Applications, 1997.4. Wise K.D. (Guest Editor), Special Issue of Proceedings of IEEE, Vol.86, No.8, Aug 1998.5. Ristic L. (Ed.), Sensor Technology and Devices, Artech House, London 1994.


L T/D P C

3 0 0 3

EC957: MICRO ELECTRO MECHANICAL SYSTEMS. (MEMS) (Elective –III for M. Tech ECE (VLSI&ES) – III Semester)

28


Course Objectives:1. To make students familiar with DFG techniques used in signal Processing.2. To map given DSP architectures into VLSI systems.3. To make students familiar with advanced DS processors.

Course outcomes:1. Students will be able to implement DSP architectures in DFG.2. Students will be able to implement filters in DF&TDF techniques.3. Students will be able to implement their DSP algorithms in DS processors.

Introduction to Digital Signal Processing Systems: Introduction, Typical DSP Algorithms, DSP Application demands and scaled CMOS technologies, Representation of DSP Algorithms.

Iteration Bound: Introduction, Data Flow Graph Representations, Loop Bound and Iteration Bound, Algorithms for computing iteration bound, Iteration bound of multirate data flow graphs.

Pipelining and Parallel Processing: Introduction, Pipelining of FIR Digital Filters, Parallel Processing, Pipelining and Parallel Processing for low power.

Retiming and Unfolding: Introduction, Definitions and properties, Solving systems of inequalities, Retiming Techniques, An algorithm for unfolding, Critical path, Unfolding and retiming, Applications of unfolding Folding: Introduction, Folding techniques, Register minimization techniques, Register minimization in folded architecture, Folding of multirate systems

Systolic Architecture Design: Introduction, System array design methodology, FIR systolic arrays, selection of scheduling vector, Matrix-matrix multiplication and 2-D systolic array design, Systolic Design for space representations containing delays. Instruction Set: Instruction types, Various types registers, Orthogonality, Assembly language and application development. Processors: Architecture and instruction set of TMS320C3X, TMS320C5X, TMS320C6X, ADSP 21XX DSP Chips, Some example programs, Fast Convolution, Introduction cook-Toom algorithm, Winograd algorithm, Iterated convolution, Cyclic convolution, Design of fast convolution algorithm by inspection Algorithmic Strength reduction in filter and transforms.

Recent Trends in DSP System Design: FPGA-Based DSP System Design, Advanced development tools for FPGA, Development tools for Programmable DSPs, I/V an introduction to Code Composer Studio.

Text Books:1. Keshab K. Parthi, VLSI Digital Signal Processing- System Design and Implementation , Wiley Inter Science. 1998,2.Kung S. Y, H. J. While House, T. Kailath, VLSI and Modern Signal processing, Prentice Hall, 1985.Reference Books:3.Jose E. France, Yannis Tsividis, Design of Analog, Digital VLSI Circuits for Telecommunications and Signal Processing, Prentice Hall,1994.4. Medisetti V. K ,VLSI Digital Signal Processing , IEEE Press (NY), USA, 1995.


L T/D P C

3 0 0 3

EC958: VLSI SIGNAL PROCESSING (VS ) (Elective-IV for M. Tech ECE (VLSI&ES) – III Semester)

29

EC959: VLSI SYSTEM DESIGN FOR TESTING (VDFT) (Elective-IV for M. Tech ECE (VLSI&ES) – III Semester)


Course Objectives:1. Students will get scope to learn DFT modeling, Fault modeling2. Students will be able to learn stuck-at-faults in VLSI designs.3. Students will learn ATPG/BIST

Course Outcomes:1. Students will be able to calculate stuck–at-faults for VLSI circuits.2. Students will employ BIST/ATPG in their projects.3. Students will be able to get overview of memory testing.

Introduction to Test and Design for Testability (DFT) Fundamentals Modeling: Modeling digital circuits at logic level, register level and structural models. Levels of modeling. Logic Simulation, Types of simulation, Delay models, Element evaluation, Hazard detection, Gate level event driven simulation.

Fault Modeling : Logic fault models, Fault detection and redundancy, Fault equivalence and fault location, Single stuck and multiple stuck, Fault models. Fault simulation applications, General techniques for Combinational circuits.

Testing for single stuck faults (SSF): Automated test pattern generation (ATPG/ATG) for SSFs in combinational and sequential circuits, Functional testing with specific fault models. Vector simulation , ATPG vectors, formats, Compaction and compression, Selecting ATPG Tool.

Design for testability: Testability trade-offs, Techniques, Scan architectures and testing, Controllability and absorbability, Generic boundary scan, Full integrated scan, Storage cells for scan design, Board level and system level DFT approaches, Boundary scan standards, Compression techniques, Different techniques, Syndrome test and signature analysis.

Built-in self-test (BIST): BIST Concepts and test pattern generation. Specific BIST Architectures, CSBL, BEST, RTS, LOCST, STUMPS, CBIST, CEBS, RTD, SST, CATS, CSTP, BILBO, Brief ideas on some advanced BIST concepts and design for self-test at board level. Memory BIST (MBIST), Memory test architectures and techniques, Introduction to memory test, Types of memories and integration, Embedded memory testing model, Memory test requirements for MBIST. Brief ideas on embedded core testing.

Text Books: 1. Miron Abramovici, Melvin A. Breur, Arthur D. Friedman, Digital Systems Testing and Testable Design, Jaico Publishing House, 2001.2. Alfred Crouch., Design for Test for Digital ICs & Embedded Core Systems, Prentice Hall.Reference Book:3. Robert J. Feugate, Jr., Steven M. Mentyn, Introduction to VLSI Testing, Prentice Hall, Englehood Cliffs, 1998


L T/D P C

3 0 0 3

30

EC960: NANO ELECTRONICS (NE ) (Elective-IV for M. Tech ECE (VLSI&ES) – III Semester)


Course Objectives:

1. To make students familiar with concepts of structure used in solid state.2. To make students familiar with Technology of nano electronics.

Course Outcomes:1. Students will be able to understand basics of nano technology and their structure.2. Students will be able to do their research in nano electronics.3. Students will be able to learn various types of sensors in real time.

Physics of solid state: Structure, Energy band, Quantum mechanics.

Technology: Film deposition methods, Lithography.

Analysis: Electron microcopies, Scanning probe microcopies.

Logic devices: Limitation of MOSFETS, Single electron devices, Quantum transport devices, Carbon Nano tubes, Molecular devices.

Spintronics: Principle, Applications, Quantum computing, Nano sensors.

Text Books:1. W. Roy VCH, Nano Electronics and Information Technology, 2nd Edition, Rainen waser 20052. Chonles P.Pook Jr., Frank. J. Owens, Introduction to Nano technology, 1 st Edition, Wiley Interscience, 2003Reference Books:3. T. Pradeep, Nano: The essentials, , 1 st Edition, Tata McGraw Hill, 20074. Mark Ratne, Danill Ratne, Nano Technology, 1 st Edition Pearson education, 2006


L T/D P C

3 0 0 3

31


Course Objectives:

1. To make students familiar with advanced memory organization techniques.2. To make students familiar with issues in memories.3. To make students familiar with current memory fabrication techniques

Course Outcomes:1. Students will get insight into basic memory techniques to advanced memory techniques.2. Students will be able to analyze faults in memories.3. Students will be able to use efficient memory techniques in their projects especially testing phase.

SRAM Cell Structures: MOS SRAM Architecture, MOS SRAM Cell and Peripheral Circuit Operation-Bipolar SRAM Technologies, Silicon On Insulator (SOl) Technology, Advanced SRAM Architectures and Technologies, Application Specific SRAMs.

DRAM Technology Development: CMOS DRAMs, DRAMs Cell Theory and Advanced Cell Structures, BiCMOS, DRAMs, Soft Error Failures in DRAMs, Advanced DRAM Designs and Architecture, Application Specific DRAMs.

Masked Read-Only Memories (ROMs): High Density ROMs, Programmable Read-Only Memories (PROMs)-Bipolar PROMs, CMOS PROMs-Erasable (UV), Programmable Road-Only Memories (EPROMs), Floating-Gate EPROM Cell-One-Time Programmable (OTP) EPROMs, Electrically Erasable PROMs (EEPROMs), EEPROM Technology And Architecture, Nonvolatile SRAM, Flash Memories (EPROMs or EEPROM), Advanced Flash Memory Architecture.

RAM Fault Modeling: Electrical Testing, Peusdo Random Testing, Megabit DRAM Testing, Non-volatile Memory Modeling and Testing, IDDQ Fault Modeling and Testing, Application Specific Memory Testing

General Reliability Issues: RAM Failure Modes and Mechanism, Non-volatile Memory Reliability, Reliability Modeling and Failure Rate Prediction, Design for Reliability, Reliability Test Structures, Reliability Screening and Qualification, RAM Fault Modeling, Electrical Testing, Pseudo Random Testing, Megabit DRAM Testing, Non-volatile Memory Modeling and Testing, IDDQ Fault Modeling and Testing, Application Specific Memory Testing.

Radiation Effects: Single Event Phenomenon (SEP), Radiation Hardening Techniques-Radiation Hardening Process and Design Issues, Radiation Hardened Memory Characteristics, Radiation Hardness Assurance and Testing, Radiation Dosimetry, Water Level Radiation Testing and Test Structures, Ferroelectric Random Access Memories (FRAMs), Gallium Arsenide (GaAs) FRAMs, Analog Memories, Magneto-resistive Random Access Memories (MRAMs), Experimental Memory Devices, Memory Hybrids and MCMs (2D) Memory Stacks and MCMs (3D) Memory MCM Testing and Reliability Issues, Memory Cards, High Density Memory Packaging Future Directions.

Text Books:1. Ashok K. Sharma, Semiconductor Memories, Two-Volume Set, Wiley-IEEE Press, 20032. Brent Keeth, R. Jacob Baker, DRAM Circuit Design A Tutorial, Wiley-IEEE Press, 2000

Reference Books:

3. Betty Prince, High Performance Memories New Architecture DRAMs and SRAMs - Evolution and Function, Wiley, 1999


L T/D P C

3 0 0 3

EC961: DESIGN OF SEMICONDUCTOR MEMORIES ( DSM ) (Elective-IV for M. Tech ECE(VLSI&ES) – III Semester)

32



M.Tech - IV Semester VLSI and Embedded Systems Scheme : 2013

S No Course No Course Title Credits


periods/weekScheme of Examination

L T PEnd

Exam Marks

Internal Assessment

Marks

Total Marks

1. EC953 Dissertation Phase-2 12 - - - 50 50 100

33

Date post:	28-Mar-2018
Category:	Documents
Upload:	tranphuc
View:	214 times
Download:	1 times

PROBABILITY AND STOCHASTIC PROCESSES (PSP) VLSI.doc · Web viewWeste Kamran Eshraghian, Principles...

Documents