Procedural Circuit Simulation with decida Richard V. H. Booth Agere Systems, Allentown, PA.

Procedural Circuit SimulationProcedural Circuit Simulationwith with decidadecida

Richard V. H. BoothRichard V. H. Booth

Agere Systems, Allentown, PAAgere Systems, Allentown, PA

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decidadecida

• Device and Circuit Data AnalysisDevice and Circuit Data Analysis• http://decida.orghttp://decida.org

• Platform for Procedural Circuit SimulationPlatform for Procedural Circuit Simulation• M.S. Toth and R.V. Booth, “A Designer-Customizable M.S. Toth and R.V. Booth, “A Designer-Customizable

Design Environment for Analog/Mixed-Signal Circuit Design Environment for Analog/Mixed-Signal Circuit Design,” presented at the 2001 O’Reilly Open-Source Design,” presented at the 2001 O’Reilly Open-Source Convention, San Diego CA, July 2001.Convention, San Diego CA, July 2001.

• http://conferences.oreillynet.com/cs/os2001/view/e_sess/1351http://conferences.oreillynet.com/cs/os2001/view/e_sess/1351

• Compact Model Compiler (AMC)Compact Model Compiler (AMC)• R.V.H. Booth, “An Extensible Compact Model Description R.V.H. Booth, “An Extensible Compact Model Description

Language and Compiler,” presented at the 2001 Language and Compiler,” presented at the 2001 International Behavioral Modeling and Simulation International Behavioral Modeling and Simulation Workshop, Santa Rosa CA, October 2001.Workshop, Santa Rosa CA, October 2001.

• http://www.bmas-conf.org/web-docs/Repository/y2001/FinalPapers/http://www.bmas-conf.org/web-docs/Repository/y2001/FinalPapers/Pdf/Booth.pdfPdf/Booth.pdf

• Device Measurements and Parameter ExtractionDevice Measurements and Parameter Extraction• Data Analysis and VisualizationData Analysis and Visualization

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decida decida procedural simulationprocedural simulation

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Procedural simulationProcedural simulation

• Design phasesDesign phases• Initial circuit module designsInitial circuit module designs• Circuit module optimizationsCircuit module optimizations• Pre-layout/post-layout characterizationsPre-layout/post-layout characterizations• Model-building for high-level verificationModel-building for high-level verification• Top-level simulations (pre-release/field)Top-level simulations (pre-release/field)

• Procedural simulationProcedural simulation• Organized simulation Organized simulation

runs/post-processing/bookkeepingruns/post-processing/bookkeeping• Can be used with Can be used with ALLALL design phases design phases

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Procedural SimulationProcedural Simulation

• Advantages of Procedural Simulation ApproachAdvantages of Procedural Simulation Approach• All variations over All variations over processingprocessing, supply , supply voltagevoltage, ,

operating operating temperaturetemperature, control register/divider , control register/divider settingssettings can be performed can be performed

• Simulation results are Simulation results are post-processedpost-processed in-line, and in-line, and can be evaluated before the entire range of can be evaluated before the entire range of variations are donevariations are done

• Simulations can be farmed out to Simulations can be farmed out to compute farmcompute farm• Script is ready for simulations with Script is ready for simulations with post-layoutpost-layout

netlists or revised process files netlists or revised process files • Simulation approach is exactly Simulation approach is exactly documenteddocumented• Scripts can be Scripts can be re-usedre-used for similar modules for similar modules• SimulatorSimulator independence independence

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PLL design component testsPLL design component tests

PFD charge-pumpREF

FBK

UP

DNVCO

loopfilter

feedback divider

OUT

bias regulatorVREF

IREF

VREG

DIV

VC

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PFD charge-pumpREF

FBK

UP

DNVCO

loopfilter

feedback divider

OUT

bias regulatorVREF

IREF

VREG

DIV

VC

dc analysis (T, Vdd)

stability

line-rejection

load-rejection

startup

dropout

compact model

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PFD charge-pumpREF

FBK

UP

DNVCO

loopfilter

feedback divider

OUT

bias regulatorVREF

IREF

VREG

DIV

VC

frequency versus VC

jitter analysis

range design

gain design

operating current

powerdown current

compact model

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PFD charge-pumpREF

FBK

UP

DNVCO

loopfilter

feedback divider

OUT

bias regulatorVREF

IREF

VREG

DIV

VC

locking time

stability analysis

phase/frequency hit

operating current

powerdown current

compact model

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Open SourceOpen Source

How do you develop a procedural circuit simulation platform How do you develop a procedural circuit simulation platform while doing real work?while doing real work?• Using the tool immediately for real work can make it Using the tool immediately for real work can make it

exactly the right solution for the problem at hand. But:exactly the right solution for the problem at hand. But:• the solutions must be generalized appropriatelythe solutions must be generalized appropriately• infrastructure specifics promote hackinginfrastructure specifics promote hacking

• Most people do it (shell scripts, etc.)Most people do it (shell scripts, etc.)• If it’s just one person using the platform, then updating If it’s just one person using the platform, then updating

it doesn’t make anyone angry. But if more than one (a it doesn’t make anyone angry. But if more than one (a few):few):

• extensibility and incremental development doesn’t require extensibility and incremental development doesn’t require major code releases, just feature-addingmajor code releases, just feature-adding

• spin-off tools can be used by othersspin-off tools can be used by others

• Open Source!Open Source!• customers can use itcustomers can use it• tool becomes more generaltool becomes more general• tool benefits from real code development expertisetool benefits from real code development expertise

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decidadecida architecture architecture

Tcl/Tk

decida BLT [incr tcl]

Application

decidalibrary

packagelibraries

userlibraries

simulators

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Tcl/Tk


Application

decidalibrary

packagelibraries

userlibraries

simulators

Tcl/Tk Core

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Tcl/Tk


Application

decidalibrary

packagelibraries

userlibraries

simulators

Extensibility

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Tcl/Tk


Application

decidalibrary

packagelibraries

userlibraries

simulators

Natural Development Flow

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decidadecida extension extension

Data objectData object

data dat1

dat1 read vco.prelayout.out

dat1 plot Time Vco

dat1 jitter Vco

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Circuit Simulator ObjectCircuit Simulator Object

celerity sim1

sim1 command “.rd vco10v3.sp”

sim1 command “.dc vcont 0 $vdd .1”

sim1 info elements

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Test Bench ObjectTest Bench Object

TestCkt tckt1

tckt1 embed vco10v3.sp

tckt1 monitor V(OUT)

set datq [tckt1 analysis_data .dc vcont 0 $vdd .1]

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Test Suite ObjectTest Suite Object

TestSuite ts1

ts1 add-test temp-sweep { . . .} {. . .}

ts1 configure –simulator hspice

ts1 go

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TestSuite Script exampleTestSuite Script example

TestSuite ts1 –mode prelayout –simulator hspice \ -modeldir /home/models/lv090g/sim \ –netlistdir /home/mgb1/work/proj1 \ -vnom 3.3 –vlow 3.0 –vhigh 3.6#-----------------------------------------------------# test definitions#-----------------------------------------------------ts1 go –guiexit 0

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TestSuite test menuTestSuite test menu

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Bandgap temperature sweep testBandgap temperature sweep test

ts1 add-test dc { prelayout {bgfra_test.sp bgfra.sp} postlayout {bgfrq_test.sp bgfra.extract.sp}} { tckt monitor {V(VBG) IBG=I(MN1) @XBGFRA: V(Q1E)} Report rpt $test.$mode.report –verbose 1 rpt header “Case Temp Vdd VBG IBG VQ1E” foreachcase {WCS WCF} { tckt setlibs $lib foreach vdd [range-sample $vlow $vhigh .1 –step] { tckt setsupply VDD $vdd set d [tckt analysis_data .dc temp -40 125 5] rpt report-data $d key TEMP vdd VBG IBG VQ1E $d delete } } delete object rpt}

Specify a Test named “dc”

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Specify list of netlists to embed

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Specify list of node voltages and element currents to monitor

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Create Report object to collect simulation results

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Perform analysis for each Case combination (process/temperature/voltage)

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Simulator-independent reference to Processing-case library

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Loop over range of supply voltages(over-ride case-combination setting)

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Simulator-independent power-supply setting

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Perform analysis and collect the resultsIn an auxiliary data object

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No post-processing required:Dump the results to the report object

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dataviewdataview of test results of test results

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Last WordsLast Words

• analysis/visualizationanalysis/visualization• dataviewdataview• X-Y/histogram/smith-chartX-Y/histogram/smith-chart• FFT/IFFTFFT/IFFT• eye/scope diagramseye/scope diagrams• jitter analysisjitter analysis• signal analysissignal analysis

• simulator-independencesimulator-independence• speed/accuracyspeed/accuracy• pre-layout/post-layoutpre-layout/post-layout• verificationverification• convergenceconvergence

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decida decida Open-Source projectOpen-Source project

http://decida.orghttp://decida.org

executables for Solaris and Linuxexecutables for Solaris and Linux

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Procedural Circuit Simulation with decida Richard V. H. Booth Agere Systems, Allentown, PA.

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