1 Block 1: ZYNQ-7000 Architecture Objectives: Describe the architecture and components that comprise the Zynq All Programmable SoC processing system (PS) Relate a user design goal to the function, benefit, and use of the Zynq All Programmable SoC Effectively select and design an interface between the Zynq PS and programmable logic (PL) that meets project goals Analyze the tradeoffs and advantages of performing a function in software versus PL Describe the AXI interconnect to the programmable logic (PL) Identify basic modes of device configuration List the input/output peripherals (IOPs) that are available in the processing system Describe the difference between multiplexed I/O (MIO) and extended MIO (EMIO) usage Describe the boot sequence of the Zynq device Describe the difference between secure and non-secure boot modes List the memory controllers that are available in the PS Discuss the decision-making process between programmable logic and software architectures Agenda: Zynq All Programmable SoC Overview o Processor with Programmable Logic o Application Processing Unit (APU) o Input/Output Peripherals (IOP) o Datapath and Memory o Programmable Logic (PL) Inside the Application Processor Unit (APU) o APU Components o Cortex-A9 Processor Overview o NEON/FPU Coprocessor o PS Memory and Cache Resources o Snoop Control Unit o System-Level Control Registers o Timers and More Timers
Transcript
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Block 1:
ZYNQ-7000 Architecture
Objectives:
Describe the architecture and components that comprise the Zynq All Programmable SoC
processing system (PS)
Relate a user design goal to the function, benefit, and use of the Zynq All Programmable SoC
Effectively select and design an interface between the Zynq PS and programmable logic (PL)
that meets project goals
Analyze the tradeoffs and advantages of performing a function in software versus PL
Describe the AXI interconnect to the programmable logic (PL)
Identify basic modes of device configuration
List the input/output peripherals (IOPs) that are available in the processing system
Describe the difference between multiplexed I/O (MIO) and extended MIO (EMIO) usage
Describe the boot sequence of the Zynq device
Describe the difference between secure and non-secure boot modes
List the memory controllers that are available in the PS
Discuss the decision-making process between programmable logic and software
architectures
Agenda:
Zynq All Programmable SoC Overview
o Processor with Programmable Logic
o Application Processing Unit (APU)
o Input/Output Peripherals (IOP)
o Datapath and Memory
o Programmable Logic (PL)
Inside the Application Processor Unit (APU)
o APU Components
o Cortex-A9 Processor Overview
o NEON/FPU Coprocessor
o PS Memory and Cache Resources
o Snoop Control Unit
o System-Level Control Registers
o Timers and More Timers
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o General Interrupt Controller (GIC)
o DMA
Processor Input-Output Peripherals
o Processor Peripheral Overview
o GPIO
o I2C
o UART
o CAN
o SPI
o SD/SDIO
o USB
o Ethernet
Introduction to AXI
o What is AXI?
o Variations of AXI
o AXI Transactions
Zynq All Programmable SoC PS-PL Interface
o PS-PL Interface Overview
o Interconnects in the PS
o AXI Master Interfaces
o AXI Slave Interfaces
o AXI ACP Interface
Zynq All Programmable SoC Booting
o Configuration Sequence Overview
o Software Boot
o PL Configuration
o Device Configuration Interface
o Typical Use Cases
Zynq All Programmable SoC Memory Resources
o Memory Resources Overview
o On-Chip Memory (OCM)
o Static Memory Controller (SMC)
o DDRx Memory Controller (DMC)
o Linear Quad SPI Flash Controller (QSPI)
o Block RAM
o Programmable Logic to Memory
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Block 2:
Embedded Design Flow
Objectives:
Describe the major sub-blocks of a Zynq All Programmable SoC processor system
Enumerate the key aspects of the Zynq All Programmable SoC processing system
List some of the peripherals available in the Vivado IP catalog Describe the embedded design
flow
Show how the hardware and software design environments are linked
Construct a simple embedded design using the IP Integrator (IPI) tool
Locate processor IP and add processors to an IPI sub-system Configure the processor IP of an
embedded design
Identify the IP available for an embedded system design
Describe how to add hardware to an existing IP integrator (IPI) block diagram
Use the IPI workspace view to construct and modify a design Explain how the various block
design's components are
configured
Discuss how memory can be constructed within the IP integrator workspace
Agenda:
Embedded Design Overview
o Embedded Processor Component
o Overview of Embedded Development
o Embedded Development Design Flow
o SDK Software Platform Management
IP Integrator and the PS Configuration Wizard
o Starting Out
o Building a System with IP Integrator
o Re-Customizing the Zynq All Programmable SoC PS
Adding Hardware to an Embedded System
o Embedded System Tools and Products
o IP Delivery in the Vivado Design Suite
o Adding Hardware with IP Integrator
o Block Memory Usage
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Hardware Aspects of the Interruptsystem in the Zynq device
o Need Your Attention
o Interrupts in the Cortex-A9 Processor
o Interrupt Controller
o Interrupt Inclusion
Labs:
1. Hardware Construction Using the Vivado IP Integrator
2. Adding and Downloading Software
3. Adding IP to a Hardware Design
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Block 3:
Embedded Software Development
Objectives:
Implement an effective software design environment for a Xilinx embedded system using
the Xilinx SDK tools
Write a basic user application (under Standalone) using the Xilinx Software Development
Kit (SDK) and run it on an embedded system platform
Examine the Xilinx libraries for required services and features
Use a board support package (BSP) to access system services from the software
application
Determine whether your embedded system application requires a standalone system or
an operating system
List the contents of a BSP
Explain the difference between level 0 and level 1 software drivers
Write and compile an error free program
Download and execute a program
Use SDK software and error navigation features
Identify the content, functionality, and use of the more popular system services in the
Standalone Software Platform
Describe the address space of the Cortex™-A9 processors
Describe the interrupt structure of the Cortex™-A9 processor
Register the interrupt handler/interrupt service routine (ISR)
Describe the Xilinx device driver implementation standard
Agenda:
Standalone Software Platform Development
o Overview
o Libraries
o Processor Services
o Device Drivers
o Standalone Board Support Package
Software Development Using SDK
o Overview
o SDK: Software Development Kit
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o Eclipse IDE
o SDK Help
o SDK Project Creation
o SDK Project Options
o SDK Run Options
o Writing Software and Compiling
Writing Code in the Xilinx Standalone Environment
o Overview
o Xilinx Data Types
o Using Device Drivers
o Using Timers
o GPIO – Detailed Example
o Tips and Tricks
Address Management
o Address Management
o Object Files and Sections
o Linking and Locating
o Linker Scripts
Software Aspects of the Interruptsystem in the Zynq device
o Overview
o Interrupts in the Cortex-A9 Processor
o Interrupt Inclusion
o Using an Interrupt Controller for Multiple Interrupts
o Create the Embedded Software Interrupt-Structure
o Considerations for Implementing Interrupts
Software Platform Download and Boot
o Overview
o Bootloader Options for the Zynq All Programmable SoC
o Bootloader Sequence of the Zynq All Programmable SoC
o Booting the Zynq All Programmable SoC from Off-Chip Flash or Another Peripheral
Writing a Custom Device Driver
o Overview
o Including the Driver in the BSP
o MDD File
o Tcl File
o MSS File
o Driver Code Structure
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Labs:
1. Basic System Implementation
2. Embedded Software Application Development
3. Software Interrupts
4. File Systems
5. Writing a Device Driver
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Block 4:
Verification for Hardware and Software
Objectives:
Generate an IP template using the Create and Package IP Wizard
Attach custom IP to the wizard-provided skeleton HDL
Manage a custom AXI IP design using the provided Vivado IDE project
Describe the Bus Functional Model (BFM) and how it helps in verification
List the BFM IP catalog components offered by Xilinx
Describe the basic tenets of the BFM Verilog API tasks
Describe the Vivado® Design Suite BFM design flow
Identify the current debugging capabilities in SDK
Describe the differences between the XMD and GDB debuggers List the features of the GDB
debugger
Use the SDK debugger perspective
List the benefits of hardware/software debugging using the Vivado Logic Analyzer
Agenda:
Designing a Custom AXI Peripheral
o Talking AXI
o AXI Backend Signaling Requirements
o Creating a Custom AXI Peripheral
Bus Functional Model Simulation
o Debugging Custom IP
o BFM Simulation
o Bus Functional Stimulus
o BFM Simulation Flow
Using the Create & Package IP Wizard
o Putting Together Custom IP Details
o Package IP Tab
Software Application Debugging
o Overview
o XMD Debugger
o GNU Debugger
o Debugging in SDK
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o Modifying the Hardware
o Advanced Debugging Capabilities
Debugging Using the Vivado Runtime Logic Analyzer
o Overview
o Hardware Debugging
o Debug Configuration Wizard
o Software Debugging
o Debugging in SDK
o Platform Debugging
Labs:
1. Building Custom AXI IP for an Embedded System
2. BFM Simulation for an AXI Peripheral
3. Integrating a Custom Peripheral
4. Application Debugging
5. Hardware/Software Co-Debugging using the Vivado Logic Analyzer
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Block 5:
Optimization of Embedded Systems
Objectives:
Apply software techniques to improve operability
Describe what profiling is and how it works
Write a software application for profiling Use the SDK profiling perspective
Use profiling reports to evaluate software efficiency Discuss software tradeoffs to
hardware
Identify when to use an AXI external connector component
List the AXI bridge components and describe when to use them Describe the differences
between AXI CDMA, DataMover and DMA
components
List the operational features of the Zynq® All Programmable SoC PS DMAC
Explain the usage of the AXI streaming FIFO component
Identify advanced methods of interfacing an embedded processing system to
programmable logic
Describe the two techniques to boot the second CPU
Outline the DMA features and services on the Zynq All Programmable SoC
Agenda:
Software Application Profiling
o Overview
o Writing Software for Profiling
o SDK Profiling
o Reading and Evaluating Profiling Reports
o Profiling in Linux
o Going to Programmable Logic
Meeting Performance Goals
o Performance Objectives
o Software or Programmable Logic?
o DDRx Memory Speed and Latency
o Achieving Maximum DMA Performance
o Sleep and Power Reduction
System Data Movement Low Latency and High Bandwidth
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o AXI Everything
o AXI Outside the Embedded Realm
o AXI Connector and Bridges
o AXI DMA
Advanced Processor and Peripheral Interface Options
o Data-Passing Mechanisms
o IP Catalog Components
o PS IOP Components in the Zynq All Programmable SoC
o Utility Components
Advanced Boot Methodology on the Zynq AP SoC
o Starting Your Engines
o Single-Processor Boot
o Dual-Processor Boot
o Programmable Logic Configuration
o Secure Boot
Advanced DMA Controller Configuration on the Zynq All Programmable SoC
o Optimizing DMA
o Zynq All Programmable SoC DMAC Basics
o Programming DMA on the Zynq All Programmable SoC
o Use Cases for Zynq All Programmable SoC DMA
Labs:
1. SDK Profiling
2. Extending Memory Space with Block RAM
3. Extending Memory Space with a DDR3 Controller
4. Configuring DMA on the Zynq All Programmable SoC
5. Boot Loading from Flash Memory
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Block 6:
Embedded Linux on Zynq Systems Part 1:
Objectives:
Describe processes, tasks and the scheduler
Use different file systems
Master the Linux command line and write custom shell scripts
Describe useful C-Libraries
Manage the development environment and the cross compiler
Use virtual file systems
Learn the basics of the root file systems
Debug your applications on Zynq SoC
Agenda:
Scheduler, processes, tasks, Users, Groups and file access
Root file system (File System Hierarchy Standard (FHS))
File systems like ext2,3 fat32 and the Memory Technology Deivice Framework for flash based
memory.
Using Linux command line
Creating shell scripts
Linux initialization system
Development environment and cross compiler
C-Libraries uclibc, glibc, eglibc
Using Xilinx SDK and JTAG debugger for Linux application debugging on Zynq
Creating and applying patches
Labs:
Formatting boot flash device
Getting to know Linux command line utilities
Shell scripting, an easy way to automate tasks
Updating of software sources with patches
Flash memory devices and the MTD framework
Using the sysfs GPIO driver
Installing and configuring SSH
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Block 7:
Embedded Linux on Zynq Systems Part 2
Objectives:
Describe the Linux boot procedure on Xilinx Zynq SoC
Build your own kernel, bootloader and root file system
Build a root file system from scratch
Build a simple webserver
Use the tools yocto or buildroot
Agenda:
Linux boot procedure on Xilinx Zynq SoC
Download, configuration and compilation of u-boot boot loader
Download, configuration and compilation of Linux kernel
Creating a console based root file system from scratch
o Device file creation
o init-process set up
o modify init scripts to adapt boot sequence
Automatic embedded Linux system creation with build system like yocto or buildroot
Labs:
Configuring the u-boot boot loader from sources
Configuring u-boot for network boot using TFTP
Compiling the Kernel
Creating a root file system
Using a build system for automated Linux development
Installing and configuration of a simple webserver using the build system
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Block 8:
Embedded Linux driver development on Zynq Systems
Objectives:
Linux basics for drvier development
o Everything we need to know about Linux to understand Linux driver and develop our
custom solutions
Linux driver modules
o Fundamentals about Linux loadable modules
Character Driver
o Most suitable interface between user space and kernel space for FPGA components on
XILINX Zynq
Platform Driver and device tree
o Interface of driver to XILINX Zynq FPGA fabric via AXI interconnect.
Linux Driver APIs
o Timer, delays, threads, work queues, semaphores, mutex, wait queues
