Progettazione di circuiti e sistemi VLSI

Interconnessioni e parassiti 1

Progettazione di circuiti e sistemi VLSIProgettazione di circuiti e sistemi VLSI

Anno Accademico 2010-2011

Lezione 9

29.4.2011

Interconnessioni e parassiti


Impact of Interconnect Parasitics

• Reduce Robustness

• Affect Performance• Increase delay• Increase power dissipation

Classes of Parasitics

• Capacitive

• Resistive

• Inductive


INTERCONNECT


Capacitive Cross Talk

X

YVX

CXY

CY


Capacitive Cross TalkDynamic Node

3 x 1 m overlap: 0.19 V disturbance

CY

CXY

VDD

PDN

CLK

CLK

In1

In2

In3

Y

X

2.5 V

0 V


Capacitive Cross TalkDriven Node

XY = RY(CXY+CY)

Keep time-constant smaller than rise time

0

0.5

0.45

0.4

0.35

0.3

0.25

0.2

0.15

0.1

0.05

010.80.6

t (nsec)

0.40.2

X

YVXRY

CXY

CY

tr↑


Dealing with Capacitive Cross Talk

• Avoid floating nodes• Protect sensitive nodes• Make rise and fall times as large as possible• Differential signaling• Do not run wires together for a long distance• Use shielding wires• Use shielding layers


Shielding

GND

GND

Shieldingwire

Substrate (GND )

Shieldinglayer

VDD


Cross Talk and Performance

Cc

- When neighboring lines switch in opposite direction of victim line, delay increases

DELAY DEPENDENT UPON ACTIVITY IN NEIGHBORING WIRES

Miller EffectMiller Effect

- Both terminals of capacitor are switched in opposite directions (0 Vdd, Vdd 0)

- Effective voltage is doubled and additional charge is needed (from Q=CV)


Structured Predictable Interconnect

S

S SV V S

G

S

SV

G

VS

S SV V S

G

S

SV

G

VExample: Dense Wire Fabric ([Sunil Kathri])Trade-off:• Cross-coupling capacitance 40x lower, 2% delay variation• Increase in area and overall capacitance Also: FPGAs, VPGAs


Encoding Data Avoids Worst-CaseConditions

Encoder

Decoder

Bus

In

Out


Driving Large Capacitances

V in Vout

CL

VDD

• Transistor Sizing• Cascaded Buffers


Using Cascaded Buffers

CL = 20 pF

In Out

1 2 N

0.25 m processCin = 2.5 fFtp0 = 30 ps

F = CL/Cin = 8000fopt = 3.6 N = 7tp = 0.76 ns

(See Chapter 5)


Optimal number of stages (lez. 5/35 ref.)

For a given load, CL and given input capacitance Cin

Find optimal sizing f

ff

fFtFNtt pN

pp lnln

ln1/ 0/1

0

0ln

1lnln2

0

f

ffFt

f

t pp

For = 0, f = e, N = lnF

f

FNCfCFC in

NinL ln

ln with

ff 1exp


Output Driver Design

Trade off Performance for Area and Energy

Given tpmax find N and f

• Area

• Energy

minminmin12

1

1

1

1...1 A

f

FA

f

fAfffA

NN

driver

22212

11

1...1 DD

LDDiDDi

Ndriver V

f

CVC

f

FVCfffE


Output Driver Design (2)

The optimal values of N and f, for minimal tp, can give too much area and transistors.

Increasing tpmax, the problem consists in the solution with minimal area and optimal energy dissipation

(see text paragraph 9.2.2)


Delay as a Function of F and N

101 3 5 7

Number of buffer stages N

9 11

10,000

1000

100

F = 100F = 1000

F = 10,000t p

/tp

0


How to Design Large Transistors

G(ate)

S(ource)

D(rain)

Multiple

Contacts

small transistors in parallel

Reduces diffusion capacitanceReduces gate resistance


Bonding Pad DesignBonding Pad

Out

InVDD GND

100 m

GND

Out


ESD Protection

• When a chip is connected to a board, there is unknown (potentially large) static voltage difference

• Equalizing potentials requires (large) charge flow through the pads

• Diodes sink this charge into the substrate – need guard rings to pick it up.


ESD Protection

Diode

PAD

VDD

R D1

D2

X

C


Chip Packaging

ChipL

L ´

Bonding wire

Mountingcavity

Leadframe

Pin

•Bond wires (~25m) are used to connect the package to the chip

• Pads are arranged in a frame around the chip

• Pads are relatively large (~100m in 0.25m technology),with large pitch (100m)

•Many chips areas are ‘pad limited’


Chip Packaging• An alternative is ‘flip-chip’:

– Pads are distributed around the chip– The soldering balls are placed on pads– The chip is ‘flipped’ onto the package– Can have many more pads


Tristate Buffers

InEn

En

VDD

Out

Out = In.En + Z.En

VDD

In

En

En

Out

Increased output drive


Reducing the swing

tpHL = CL Vswing/2

Iav

Reducing the swing potentially yields linear reduction in delay Also results in reduction in power dissipation Delay penalty is paid by the receiver Requires use of “sense amplifier” to restore signal level Frequently designed differentially (e.g. LVDS)


INTERCONNECT


Impact of Resistance

• We have already learned how to drive RC interconnect

• Impact of resistance is commonly seen in power supply distribution:– IR drop– Voltage variations

• Power supply is distributed to minimize the IR drop and the change in current due to switching of gates


IR Introduced Noise

M1

X

I

R’

RΔV

Фpre

ΔV

VDD

VDD - ΔVV

I


19

ASP DAC 2000

Power Dissipation TrendsPower Dissipation Trends

Power consumption is increasingPower consumption is increasing Better cooling technology neededBetter cooling technology needed

Supply current is increasing faster!Supply current is increasing faster!

OnOn--chip signal integrity will be a major chip signal integrity will be a major issueissue

Power and current distribution are criticalPower and current distribution are critical

Opportunities to slow power growthOpportunities to slow power growth Accelerate Accelerate VddVdd scalingscaling

Low κ dielectrics & thinner (Cu) Low κ dielectrics & thinner (Cu) interconnectinterconnect

SOI circuit innovations SOI circuit innovations

Clock system designClock system design

micromicro--architecturearchitecture

Power Dissipation

020406080

100120140160

EV4 EV5 EV6 EV7 EV8

Po

we

r (W

)

0

0.5

1

1.5

2

2.5

3

3.5

Vol

tage

(V

)

Supply Current

0

20

40

60

80

100

120

140

EV4 EV5 EV6 EV7 EV8

Curr

ent (

A)

0

0.5

1

1.5

2

2.5

3

3.5

Vo

ltag

e (

V)


Resistance and the Power Distribution Problem

• Requires fast and accurate peak current predictionRequires fast and accurate peak current prediction• Heavily influenced by packaging technologyHeavily influenced by packaging technology

BeforeBefore AfterAfter


Power Distribution

• Low-level distribution is in Metal 1• Power has to be ‘strapped’ in higher layers of

metal.• The spacing is set by IR drop,

electromigration, inductive effects• Always use multiple contacts on straps


3 Metal Layer Approach (EV4)

3rd “coarse and thick” metal layer added to thetechnology for EV4 design

Power supplied from two sides of the die via 3rd metal layer

2nd metal layer used to form power grid

90% of 3rd metal layer used for power/clock routing

Metal 3

Metal 2

Metal 1


2 reference plane metal layers added to thetechnology for EV6 designSolid planes dedicated to Vdd/Vss

Significantly lowers resistance of gridLowers on-chip inductance

6 Metal Layer Approach – EV6

Metal 4

Metal 2Metal 1

RP2/Vdd

RP1/Vss

Metal 3


Electromigration

Limits dc-current to 1 mA/m


The Global Wire Problem

Challenges• No further improvements to be expected after the

introduction of Copper (superconducting, optical?)• Design solutions

– Use of fat wires– Insert repeaters — but might become prohibitive (power, area)– Efficient chip floorplanning

• Towards “communication-based” design – How to deal with latency?– Is synchronicity an absolute necessity?

outwwdoutdwwd CRCRCRCRT 693.0377.0


Interconnect Projections: Copper

• Copper is planned in full sub-0.25 m process flows and large-scale designs (IBM, Motorola, IEDM97)

• With cladding and other effects, Cu ~ 2.2 -cm vs. 3.5 for Al(Cu) 40% reduction in resistance

• Electromigration improvement; 100X longer lifetime (IBM, IEDM97)

– Electromigration is a limiting factor beyond 0.18 m if Al is used (HP, IEDM95)

Vias


Diagonal Wiring

y

x

destination

Manhattan

source

diagonal

• 20+% Interconnect length reduction• Clock speed Signal integrity Power integrity • 15+% Smaller chips plus 30+% via reduction


Reducing RC-delay

Repeater

(chapter 5)


Repeater Insertion (Revisited)

Taking the repeater loading into account

For a given technology and a given interconnect layer, there exists For a given technology and a given interconnect layer, there exists an optimal length of the wire segments between repeaters. The an optimal length of the wire segments between repeaters. The delay of these wire segments is delay of these wire segments is independent of the routing layer!independent of the routing layer!

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