Progress towards Superlattice-Source Vertical Nanowire III ......2013/09/26 · SL source with...

Progress towards Superlattice-Source Vertical Nanowire III-V MOSFETs

Jesús A. del Alamo and Xin Zhao Microsystems Technology Laboratories

MIT

E3S TeleseminarSeptember 26, 2013

joyuenTypewritten TextFor E3S Internal Use ONLYThese slides may contain prepublication data and/or confidential information.

joyuenTypewritten Text

2

Outline

1. Device concept

2. Simulations

3. Nanowire FET fabrication technology

4. Electrical characteristics of InGaAs NW‐MOSFETs

5. Next steps


1. Device conceptNanowire FET with Superlattice Source

3



High‐energy tail of electrons at source of FET responsible for subthreshold current

Why S=60 mV/dec at best in FETs?

4

∝

High energy tail Subthreshold current

High‐energy tail of source electrons


5

Key idea: suppress electron tail at source by engineering DOS

Empty miniband

Partially filled miniband

Minigap

Source DOS engineered to eliminate high‐energy electrons subthreshold current suppressed

DOS at source


60 mV/dec

VGS

log ID

Steep S!

0

Source Channel Drain

Subthreshold Characteristics

6

A

AB

C

C

B

Three regimes of operation:1. Steep slope regime: limited by source to drain tunneling2. Subthreshold regime: thermionic emission of tail

electrons (minimized for narrow miniband)3. ON state: ballistic transport


How to create Miniband/Minigap DOS at Source?

7

Two essential ingredients:1. Superlattice source: to create miniband/minigap

structure in longitudinal direction2. Nanowire geometry: to impose transversal quantization,

create 1D subbands and open a true minigap

Esaki, TSF 1976

1D‐DOSBand structure of SL

Gnani, IEDM 2011


8

2. Simulations: Nanowire SL structures

Expected 1D subbandstructure

In0.53Ga0.47As NW, D=4.5 nm

• Nexnano• Start by calibrating simulator with simple nanowire structures

In0.53Ga0.47As NW, D=15 nm


9

SL source with lateral confinement: minibands split into subbands

3 nm In0.53Ga0.47As/1.2 nm In0.52Al0.48As SL, D=15 nm

• In NW configuration, SL minibands split into subbands• For wide diameters, subbands overlap in energy

Same miniband, different subbands


10

Tight transversal confinement:Minigap appears in all k directions

With NW diameter

11

Minigap widens as NW diameter shrinks

For small D, minigap between 1st and 2nd miniband

Same minibanddifferent subbands

Eg=0.23 eV between 1st and 2nd miniband

3 nm In0.53Ga0.47As/1.2 nm In0.52Al0.48As SL, D=4.5 nm

different miniband


Transmission coefficient of standard NW

InGaAs nanowire (D=4.5 nm)

1st subband

2nd subband(two‐fold degenerate)

Expected plateau structure

DOS

12


Transmission coefficient of SL NW

3 nm In0.53Ga0.47As/1.2 nm In0.52Al0.48As SL NW (D=4.5 nm,10 periods)

1st miniband

2nd miniband230 meV

Transmission coefficient clearly reveals minigap in SL NW DOS13


T(E) suppressed by >two decades in minigap14

3 nm In0.53Ga0.47As/1.2 nm In0.52Al0.48As SL NW (D=4.5 nm,10 periods)

Transmission coefficient of SL NW


• Dielectric/semiconductor interface:• Interface traps with allowed states• Roughness

• Sharpness of miniband edges:• Finite number of periods of SL• Imperfection of the crystal lattice:

• Doping• Phonons• Intermixing• Crystal defects: dislocations, etc

• Non‐uniformity of nanowire diameter

15

Non-idealities


16

3. NW MOSFET fabrication technology

• Nanowire MOSFET provides ultimate scalability• Vertical Nanowire uncouples footprint scaling and gate length

scaling can achieve excellent SCE on a tiny footprint

Gate‐All‐Around Nanowire MOSFET: ultimate CMOS device!

Kuhn, TED 2012


17

Vertical NW MOSFET fabrication technology

Key elements:• In0.53Ga0.47As source, drain and channel• Top‐down approach based on RIE (a first!)• High‐k dielectric by ALD, wrap‐around‐gate

Device vehicle: InGaAs NW‐MOSFET

Zhao, IEDM 2013



InGaAs

Adhesionlayer

HSQ

ALD‐Al2O3

ALD‐WN

SOG

Top View Side View

Starting substrate

Step 1Mask definition by EBL

Step 2RIE and cleaning

Step 3Digital Etch

Superlattice

Contact

Fabrication technology

18


Step 4High‐K/Gate metal depositionand patterning

Step 5Planarization andetch back

Step 62nd planarization, etch back and G/D contact opened

Gate

Gate Drain

Step 7Metalization Gate DrainSource

n+ InGaAssource

InGaAschannel

19

InGaAs

Adhesionlayer

HSQ

ALD‐Al2O3

ALD‐WN

SOG

Superlattice

Contact


20

Key enabling technology: RIE etch by BCl3/SiCl4/Ar Chemistry

• In compounds hard to etch• BCl3/SiCl4/Ar RIE chemistry used for III‐V optical devices• Never used for nm‐scale features• Substrate temperature during etch is key!


21

Key enabling technology: RIE etch by BCl3/SiCl4/Ar Chemistry

No notching in the etching of complex heterostructures


22

Nanowire RIE followed by digital etch

• Shrinks NW diameter by 2 nm per cycle• Unchanged shape• Improved sidewall roughness

Digital etch: self‐limiting O2 plasma oxidation + H2SO4 oxide removal

before after 10 cycles


23

After 1st planarization

Nanowire arrays Contacts

50 nm

5 µm5 µm

50 nm

40 nmGate metal

30 nm

After 2nd planarization

Nanowire

Gate

Source

Drain

Gate metal

Pictures along the fabrication process


24

4. Electrical characteristics of InGaAs NW-MOSFETs

Single nanowire MOSFET: D= 30 nm, LG= 80 nm, 4.5 nm Al2O3 (EOT = 2.2 nm)

At VDS=0.5 V (normalized by periphery):• gm,pk=280 μS/μm• S=200 mV/dec• Ron=759 Ω.μm

0.0 0.1 0.2 0.3 0.4 0.50

5

10

15

20

I d (

A)

Vds (V)

Vgs=-0.6 V to 0.8 V in 0.1 V stepRon=759 m(at Vgs=1 V)Lch=80 nmD=30 nm

0

50

100

150

200

Nor

mal

ized

I d (

A/m

)

-0.6 -0.4 -0.2 0.0 0.2 0.4 0.6

10-8

10-7

10-6

10-5

Vds=0.05V

I d (A

)

Vgs(V)

Vds=0.5VIg< 10-9 A

DIBL=195 mV/VS(Vds=0.05V)=145 mV/decS(Vds=0.5V)=200 mV/dec

10-7

10-6

10-5

10-4

Nor

mal

ized

I d (A

/m

)

-0.6 -0.4 -0.2 0.0 0.2 0.4 0.60

50

100

150

200

Vgs(V)

0

50

100

150

200

250

300gm, pk(Vds=0.5 V)=280 S/m

Vds=0.5V

Nor

maz

lied

I d (

A/m

)

Nor

mal

ized

gm (

S/

m)



25

D=50 nm InGaAs NW-MOSFETsSingle nanowire MOSFET:

D= 50 nm, LG= 80 nm, 4.5 nm Al2O3 (EOT = 2.2 nm)

At VDS=0.5 V:• gm,pk=730 μS/μm• S=305 mV/dec• Ron=310 Ω.μm

0.0 0.1 0.2 0.3 0.4 0.50

20

40

60

80

100

Vds (V)

I d (

A)

Vgs=-0.6 V to 0.8 V in 0.1 V stepRon=310m(at Vgs=1 V)LG=80 nmD=50 nm

0

100

200

300

400

500

600

700

Nor

mal

ized

I d (

A/m

)

-0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.810-7

10-6

10-5

10-4

I d (A

)

Vgs(V)

DIBL=360 mV/VS(Vds=0.05V)=210 mV/decS(Vds=0.5V)=305 mV/dec

Ig< 10-10 A

Vds=0.5V

Vds=0.05V

10-6

10-5

10-4

Nor

mal

ized

I d (A

/m

)

-1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.40

100

200

300

400

500

600

Nor

maz

lied

I d (

A/

m) gm, pk(Vds=0.5 V)

=730 S/m

Vds=0.5V

Vgs(V)

0

100

200

300

400

500

600

700

Nor

maz

lied

g m (

S/m

)


26

Impact of nanowire diameter

30 35 40 45 50

150

200

250

300

350

400

450

Nanowire Diameter (nm)

DIB

L (m

V/V

)

30 35 40 45 50

100200300400500600700800900

Nor

mal

ized

gm (

S/

m)


Vds=0.5 V

30 35 40 45 50200

400

600

800

1000

1200

Vgs=1 VNorm

aliz

ed R

on (

m

)


D↓ S↓, DIBL↓, gm↓, Ron↑

30 35 40 45 50

150

200

250

300

350S

(mV

/dec

)


Vds=0.5V

Vds=0.05V

Error bars indicate distribution of ~10 devices


27

Impact of digital etch

InGaAs NW‐MOSFETs with D= 40 nm (final diameter)

For same final diameter, digital etch:• Improves subthreshold swing• Improves peak transconductance• Reduces gate leakage current

-0.6 -0.4 -0.2 0.0 0.2 0.4

10-8

10-7

10-6

10-5

w/ digital etchw/o digital etch

Vgs(V)

I d (A

)

Vds=0.5V

Vds=0.05V

10-7

10-6

10-5

10-4

Nor

mal

ized

I d (A

/m

)

-1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.410-6

10-5

10-4

10-3Vds=1 V

I g (A

/cm

2 )Vgs(V)

w/ digital etch

w/o digital etch

better sidewall interfacial characteristics

-0.5 -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.20

100

200

300

400

500 w/ digital etch w/o digital etch

Vgs(V)

Nor

maz

lied

g m (

S/

m)



Benchmarking against bottom-up InGaAs NW-MOSFETs

• Fundamental trade‐off between transport and SCE• Top‐down NW‐MOSFETs as good as bottom up devices

28

Persson, DRC 2012

Tomioka, Nature 2012


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5. Next steps

1. Refine nanowire fabrication process• Make more robust• Reduce gate leakage current• Scale to D~20 nm

2. Study InGaAs Nanowire MOSFETs• Build simple models (ballistic transport, electrostatics) and compare with measurements• Study transport at low temperatures

3. Fabricate InGaAs Nanowire MOSFETs with SL source• Experimental observation of SL filtering

4. Simulations of SLS‐NW MOSFETs• Dispersion relations, DOS, transmission coefficient, etc.

5. Fabricate Nanowire Tunnel FETs• In collaboration with Theme I colleagues• Initially, follow Intel’s heterostructure design


30

Intel’s InGaAs Tunnel MOSFET

Dewey, IEDM 2011


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Progress towards Superlattice-Source Vertical Nanowire III ......2013/09/26 · SL source with...

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